/* * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ * * Based on davinci_dvevm.h. Original Copyrights follow: * * Copyright (C) 2007 Sergey Kubushyn * * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H /* * Board */ #define CONFIG_DRIVER_TI_EMAC /* check if direct NOR boot config is used */ #ifndef CONFIG_DIRECT_NOR_BOOT #define CONFIG_USE_SPIFLASH #endif /* * SoC Configuration */ #define CONFIG_MACH_DAVINCI_DA850_EVM #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_DA850_PLL_INIT #define CONFIG_SYS_DA850_DDR_INIT #ifdef CONFIG_DIRECT_NOR_BOOT #define CONFIG_ARCH_CPU_INIT #define CONFIG_DA8XX_GPIO #define CONFIG_SYS_TEXT_BASE 0x60000000 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) #define CONFIG_DA850_LOWLEVEL #else #define CONFIG_SYS_TEXT_BASE 0xc1080000 #endif /* * Memory Info */ #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ /* memtest start addr */ #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) /* memtest will be run on 16MB */ #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ DAVINCI_SYSCFG_SUSPSRC_UART2 | \ DAVINCI_SYSCFG_SUSPSRC_EMAC | \ DAVINCI_SYSCFG_SUSPSRC_I2C) /* * PLL configuration */ #define CONFIG_SYS_DV_CLKMODE 0 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 #define CONFIG_SYS_DA850_PLL0_PLLM 24 #define CONFIG_SYS_DA850_PLL1_PLLM 21 /* * DDR2 memory configuration */ #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ DV_DDR_PHY_EXT_STRBEN | \ (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ (0 << DV_DDR_SDTMR1_WTR_SHIFT)) #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ (0 << DV_DDR_SDTMR2_CKE_SHIFT)) #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 /* * Serial Driver info */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SPI #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_CMD_SF #define CONFIG_DAVINCI_SPI #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) #define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #ifdef CONFIG_USE_SPIFLASH #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 #endif /* * I2C Configuration */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_DAVINCI #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 /* * Flash & Environment */ #ifdef CONFIG_USE_NAND #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_NAND_DAVINCI #define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #define CONFIG_ENV_SIZE (128 << 10) #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K #define CONFIG_SYS_NAND_CS 3 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE #define CONFIG_SYS_NAND_MASK_CLE 0x10 #define CONFIG_SYS_NAND_MASK_ALE 0x8 #undef CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ CONFIG_SYS_NAND_U_BOOT_SIZE - \ CONFIG_SYS_MALLOC_LEN - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_NAND_ECCPOS { \ 24, 25, 26, 27, 28, \ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ 59, 60, 61, 62, 63 } #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 10 #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_NAND_LOAD #endif /* * Network & Ethernet Configuration */ #ifdef CONFIG_DRIVER_TI_EMAC #define CONFIG_MII #define CONFIG_BOOTP_DNS #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 #endif #ifdef CONFIG_USE_NOR #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ + 3) #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ #endif #ifdef CONFIG_USE_SPIFLASH #undef CONFIG_ENV_IS_IN_FLASH #undef CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SIZE (64 << 10) #define CONFIG_ENV_OFFSET (256 << 10) #define CONFIG_ENV_SECT_SIZE (64 << 10) #define CONFIG_SYS_NO_FLASH #endif /* * U-Boot general configuration */ #define CONFIG_MISC_INIT_R #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOOTFILE "uImage" /* Boot file name */ #define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) #define CONFIG_VERSION_VARIABLE #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_HUSH_PARSER #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_LONGHELP #define CONFIG_CRC32_VERIFY #define CONFIG_MX_CYCLIC /* * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) #define CONFIG_HWCONFIG /* enable hwconfig */ #define CONFIG_CMDLINE_TAG #define CONFIG_REVISION_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTARGS \ "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" #define CONFIG_BOOTDELAY 3 #define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes" /* * U-Boot commands */ #include #define CONFIG_CMD_ENV #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP #define CONFIG_CMD_DIAG #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_SAVES #define CONFIG_CMD_MEMORY #ifdef CONFIG_CMD_BDI #define CONFIG_CLOCKS #endif #ifndef CONFIG_DRIVER_TI_EMAC #undef CONFIG_CMD_NET #undef CONFIG_CMD_DHCP #undef CONFIG_CMD_MII #undef CONFIG_CMD_PING #endif #ifdef CONFIG_USE_NAND #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_IMLS #define CONFIG_CMD_NAND #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS #define CONFIG_LZO #define CONFIG_RBTREE #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS #endif #ifdef CONFIG_USE_SPIFLASH #undef CONFIG_CMD_IMLS #undef CONFIG_CMD_FLASH #define CONFIG_CMD_SPI #define CONFIG_CMD_SAVEENV #endif #if !defined(CONFIG_USE_NAND) && \ !defined(CONFIG_USE_NOR) && \ !defined(CONFIG_USE_SPIFLASH) #define CONFIG_ENV_IS_NOWHERE #define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_SIZE (16 << 10) #undef CONFIG_CMD_IMLS #undef CONFIG_CMD_ENV #endif /* SD/MMC configuration */ #ifndef CONFIG_USE_NOR #define CONFIG_MMC #define CONFIG_DAVINCI_MMC_SD1 #define CONFIG_GENERIC_MMC #define CONFIG_DAVINCI_MMC #endif /* * Enable MMC commands only when * MMC support is present */ #ifdef CONFIG_MMC #define CONFIG_DOS_PARTITION #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_MMC #endif #ifndef CONFIG_DIRECT_NOR_BOOT /* defines for SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" #define CONFIG_SPL_STACK 0x8001ff00 #define CONFIG_SPL_TEXT_BASE 0x80000000 #define CONFIG_SPL_MAX_FOOTPRINT 32768 #define CONFIG_SPL_PAD_TO 32768 #endif /* Load U-Boot Image From MMC */ #ifdef CONFIG_SPL_MMC_LOAD #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x75 #undef CONFIG_SPL_SPI_SUPPORT #undef CONFIG_SPL_SPI_LOAD #endif /* additions for new relocation code, must added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0xc0000000 #ifdef CONFIG_DIRECT_NOR_BOOT #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 #else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ GENERATED_GBL_DATA_SIZE) #endif /* CONFIG_DIRECT_NOR_BOOT */ #endif /* __CONFIG_H */