/* * (C) Copyright 2000, 2001 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * (C) Copyright 2001 * Torsten Stevens, FHG IMS, stevens@ims.fhg.de * Bruno Achauer, Exet AG, bruno@exet-ag.de. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ /* * board/config.h - configuration options, board specific * [derived from config_TQM850L.h] */ #ifndef __CONFIG_H #define __CONFIG_H /* * High Level Configuration Options * (easy to change) */ #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ #define CONFIG_LANTEC 2 /* ...on a Lantec rev.2 board */ /* * Port assignments (CONFIG_LANTEC == 1): * - SMC1: J11 (MDB) ? * - SMC2: J6 (Feature connector) * - SCC2: J9 (RJ45) * - SCC3: J8 (Sub-D9) * * Port assignments (CONFIG_LANTEC == 2): TBD */ #undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */ #define CONFIG_8xx_CONS_SCC3 #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ #if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ #else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_CMD_MINIMAL 0 #define CONFIG_CMD_TINY (CFG_CMD_FLASH | \ CFG_CMD_MEMORY | \ CFG_CMD_LOADS | \ CFG_CMD_LOADB) #define CONFIG_CMD_NORMAL (CONFIG_CMD_DFL & ~CFG_CMD_BOOTD) #define CONFIG_CMD_GDB (CONFIG_CMD_NORMAL | CFG_CMD_KGDB) #define CONFIG_CMD_FULL (CFG_CMD_ALL & ~CFG_CMD_BEDBUG \ & ~CFG_CMD_BMP \ & ~CFG_CMD_BSP \ & ~CFG_CMD_DOC \ & ~CFG_CMD_DTT \ & ~CFG_CMD_EEPROM \ & ~CFG_CMD_ELF \ & ~CFG_CMD_FDC \ & ~CFG_CMD_FDOS \ & ~CFG_CMD_HWFLOW \ & ~CFG_CMD_I2C \ & ~CFG_CMD_IDE \ & ~CFG_CMD_IRQ \ & ~CFG_CMD_JFFS2 \ & ~CFG_CMD_KGDB \ & ~CFG_CMD_MII \ & ~CFG_CMD_NAND \ & ~CFG_CMD_PCI \ & ~CFG_CMD_PCMCIA \ & ~CFG_CMD_SCSI \ & ~CFG_CMD_SPI \ & ~CFG_CMD_USB \ & ~CFG_CMD_VFD ) #if CONFIG_LANTEC >= 2 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ #endif #if CONFIG_LANTEC >= 2 # define CONFIG_COMMANDS CONFIG_CMD_FULL #else # define CONFIG_COMMANDS (CONFIG_CMD_FULL & ~CFG_CMD_DATE & ~CFG_CMD_NET) #endif /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ /*----------------------------------------------------------------------- * Internal Memory Mapped Register */ #define CFG_IMMR 0xFFF00000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ #define CFG_INIT_RAM_ADDR CFG_IMMR #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0x40000000 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_BASE CFG_FLASH_BASE #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ /*----------------------------------------------------------------------- * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif /*----------------------------------------------------------------------- * SYPCR - System Protection Control 11-9 * SYPCR can only be written once after reset! *----------------------------------------------------------------------- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) #endif /*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration 11-6 *----------------------------------------------------------------------- * PCMCIA config., multi-function pin tri-state */ #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK) /*----------------------------------------------------------------------- * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX] *----------------------------------------------------------------------- */ #define CONFIG_8xx_GCLK_FREQ 33000000 /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control 11-26 *----------------------------------------------------------------------- * Clear Reference Interrupt Status, Timebase freezing enabled */ #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) /*----------------------------------------------------------------------- * RTCSC - Real-Time Clock Status and Control Register 11-27 *----------------------------------------------------------------------- */ #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */ #define CFG_PISCR (PISCR_PS | PISCR_PITF) /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit * * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! */ /* up to 50 MHz we use a 1:1 clock */ #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 *----------------------------------------------------------------------- * Set clock output, timebase and RTC source and divider, * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 /* up to 50 MHz we use a 1:1 clock */ #define CFG_SCCR (SCCR_TBS | \ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) /*----------------------------------------------------------------------- * *----------------------------------------------------------------------- * */ #define CFG_DER 0 /* * Init Memory Controller: * * BR0/5 and OR0/5 (FLASH) */ #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ #define FLASH_BASE5_PRELIM 0x60000000 /* FLASH bank #1 */ /* used to re-map FLASH both when starting from SRAM or FLASH: * restrict access enough to keep SRAM working (if any) * but not too much to meddle with FLASH accesses */ #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ /* FLASH timing */ #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \ OR_SCY_5_CLK | OR_TRLX) #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) #define CFG_OR5_REMAP CFG_OR0_REMAP #define CFG_OR5_PRELIM CFG_OR0_PRELIM #define CFG_BR5_PRELIM ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V ) /* * BR2/3 and OR2/3 (SDRAM) * */ #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ /* SDRAM timing: Multiplexed addresses */ #define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM) #define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) /* * Memory Periodic Timer Prescaler */ /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ /* * MAMR settings for SDRAM */ /* periodic timer for refresh */ #define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ /* 8 column SDRAM */ #define CFG_MAMR_8COL \ ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) /* * Internal Definitions * * Boot Flags */ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ #endif /* __CONFIG_H */