/* * Copyright (C) 2015 Udoo * Author: Tungyi Lin * Richard Hu * Based on board/wandboard/spl.c * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_SPL_BUILD) #include /* * Driving strength: * 0x30 == 40 Ohm * 0x28 == 48 Ohm */ #define IMX6DQ_DRIVE_STRENGTH 0x30 #define IMX6SDL_DRIVE_STRENGTH 0x28 /* configure MX6Q/DUAL mmdc DDR io registers */ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, .dram_cas = IMX6DQ_DRIVE_STRENGTH, .dram_ras = IMX6DQ_DRIVE_STRENGTH, .dram_reset = IMX6DQ_DRIVE_STRENGTH, .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, .dram_sdba2 = 0x00000000, .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, }; /* configure MX6Q/DUAL mmdc GRP io registers */ static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { .grp_ddr_type = 0x000c0000, .grp_ddrmode_ctl = 0x00020000, .grp_ddrpke = 0x00000000, .grp_addds = IMX6DQ_DRIVE_STRENGTH, .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, .grp_ddrmode = 0x00020000, .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, }; /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, .dram_cas = IMX6SDL_DRIVE_STRENGTH, .dram_ras = IMX6SDL_DRIVE_STRENGTH, .dram_reset = IMX6SDL_DRIVE_STRENGTH, .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, .dram_sdba2 = 0x00000000, .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, }; /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { .grp_ddr_type = 0x000c0000, .grp_ddrmode_ctl = 0x00020000, .grp_ddrpke = 0x00000000, .grp_addds = IMX6SDL_DRIVE_STRENGTH, .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, .grp_ddrmode = 0x00020000, .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, }; /* MT41K128M16JT-125 */ static struct mx6_ddr3_cfg mt41k128m16jt_125 = { /* quad = 1066, duallite = 800 */ .mem_speed = 1066, .density = 2, .width = 16, .banks = 8, .rowaddr = 14, .coladdr = 10, .pagesz = 2, .trcd = 1375, .trcmin = 4875, .trasmin = 3500, .SRT = 0, }; static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = { .p0_mpwldectrl0 = 0x00350035, .p0_mpwldectrl1 = 0x001F001F, .p1_mpwldectrl0 = 0x00010001, .p1_mpwldectrl1 = 0x00010001, .p0_mpdgctrl0 = 0x43510360, .p0_mpdgctrl1 = 0x0342033F, .p1_mpdgctrl0 = 0x033F033F, .p1_mpdgctrl1 = 0x03290266, .p0_mprddlctl = 0x4B3E4141, .p1_mprddlctl = 0x47413B4A, .p0_mpwrdlctl = 0x42404843, .p1_mpwrdlctl = 0x4C3F4C45, }; static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = { .p0_mpwldectrl0 = 0x002F0038, .p0_mpwldectrl1 = 0x001F001F, .p1_mpwldectrl0 = 0x001F001F, .p1_mpwldectrl1 = 0x001F001F, .p0_mpdgctrl0 = 0x425C0251, .p0_mpdgctrl1 = 0x021B021E, .p1_mpdgctrl0 = 0x021B021E, .p1_mpdgctrl1 = 0x01730200, .p0_mprddlctl = 0x45474C45, .p1_mprddlctl = 0x44464744, .p0_mpwrdlctl = 0x3F3F3336, .p1_mpwrdlctl = 0x32383630, }; /* DDR 64bit 1GB */ static struct mx6_ddr_sysinfo mem_qdl = { .dsize = 2, .cs1_mirror = 0, /* config for full 4GB range so that get_mem_size() works */ .cs_density = 32, .ncs = 1, .bi_on = 1, /* quad = 2, duallite = 1 */ .rtt_nom = 2, /* quad = 2, duallite = 1 */ .rtt_wr = 2, .ralat = 5, .walat = 0, .mif3_mode = 3, .rst_to_cke = 0x23, .sde_to_rst = 0x10, }; static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; /* set the default clock gate to save power */ writel(0x00C03F3F, &ccm->CCGR0); writel(0x0030FC03, &ccm->CCGR1); writel(0x0FFFC000, &ccm->CCGR2); writel(0x3FF00000, &ccm->CCGR3); writel(0x00FFF300, &ccm->CCGR4); writel(0x0F0000C3, &ccm->CCGR5); writel(0x000003FF, &ccm->CCGR6); } static void gpr_init(void) { struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; /* enable AXI cache for VDOA/VPU/IPU */ writel(0xF00000FF, &iomux->gpr[4]); /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ writel(0x007F007F, &iomux->gpr[6]); writel(0x007F007F, &iomux->gpr[7]); } static void spl_dram_init(void) { if (is_cpu_type(MXC_CPU_MX6DL)) { mt41k128m16jt_125.mem_speed = 800; mem_qdl.rtt_nom = 1; mem_qdl.rtt_wr = 1; mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125); } else if (is_cpu_type(MXC_CPU_MX6Q)) { mt41k128m16jt_125.mem_speed = 1066; mem_qdl.rtt_nom = 2; mem_qdl.rtt_wr = 2; mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); mx6_dram_cfg(&mem_qdl, &mx6q_1g_mmdc_calib, &mt41k128m16jt_125); } udelay(100); } void board_init_f(ulong dummy) { ccgr_init(); /* setup AIPS and disable watchdog */ arch_cpu_init(); gpr_init(); /* iomux */ board_early_init_f(); /* setup GP timer */ timer_init(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* DDR initialization */ spl_dram_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); } #endif