/* * Most of this taken from Redboot hal_platform_setup.h with cleanup * * NOTE: I haven't clean this up considerably, just enough to get it * running. See hal_platform_setup.h for the source. See * board/cradle/memsetup.S for another PXA250 setup that is * much cleaner. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include #include #include DRAM_SIZE: .long CFG_DRAM_SIZE /* wait for coprocessor write complete */ .macro CPWAIT reg mrc p15,0,\reg,c2,c0,0 mov \reg,\reg sub pc,pc,#4 .endm .globl memsetup memsetup: mov r10, lr /* Set up GPIO pins first */ ldr r0, =GPSR0 ldr r1, =CFG_GPSR0_VAL str r1, [r0] ldr r0, =GPSR1 ldr r1, =CFG_GPSR1_VAL str r1, [r0] ldr r0, =GPSR2 ldr r1, =CFG_GPSR2_VAL str r1, [r0] ldr r0, =GPCR0 ldr r1, =CFG_GPCR0_VAL str r1, [r0] ldr r0, =GPCR1 ldr r1, =CFG_GPCR1_VAL str r1, [r0] ldr r0, =GPCR2 ldr r1, =CFG_GPCR2_VAL str r1, [r0] ldr r0, =GPDR0 ldr r1, =CFG_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 ldr r1, =CFG_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 ldr r1, =CFG_GPDR2_VAL str r1, [r0] ldr r0, =GAFR0_L ldr r1, =CFG_GAFR0_L_VAL str r1, [r0] ldr r0, =GAFR0_U ldr r1, =CFG_GAFR0_U_VAL str r1, [r0] ldr r0, =GAFR1_L ldr r1, =CFG_GAFR1_L_VAL str r1, [r0] ldr r0, =GAFR1_U ldr r1, =CFG_GAFR1_U_VAL str r1, [r0] ldr r0, =GAFR2_L ldr r1, =CFG_GAFR2_L_VAL str r1, [r0] ldr r0, =GAFR2_U ldr r1, =CFG_GAFR2_U_VAL str r1, [r0] /* enable GPIO pins */ ldr r0, =PSSR ldr r1, =CFG_PSSR_VAL str r1, [r0] ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */ ldr r2, =CFG_MSC1_VAL /* high - bank 3 Ethernet Controller */ str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */ ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */ ldr r1, =LED_BLANK mov r0, #0xFF str r0, [r1] /* turn on hex leds */ loop: ldr r0, =0xB0070001 ldr r1, =_LED str r0, [r1] /* hex display */ /********************************************************************* Initlialize Memory Controller The sequence below is based on the recommended init steps detailed in the EAS, chapter 5 (Chapter 10, Operating Systems Developers Guide) pause for 200 uSecs- allow internal clocks to settle *Note: only need this if hard reset... doing it anyway for now */ @ ---- Wait 200 usec ldr r3, =OSCR @ reset the OS Timer Count to zero mov r2, #0 str r2, [r3] ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty 1: ldr r2, [r3] cmp r4, r2 bgt 1b mem_init: @ get memory controller base address ldr r1, =MEMC_BASE @**************************************************************************** @ Step 1 @ @ write msc0, read back to ensure data latches @ ldr r2, =CFG_MSC0_VAL str r2, [r1, #MSC0_OFFSET] ldr r2, [r1, #MSC0_OFFSET] @ write msc1 ldr r2, =CFG_MSC1_VAL str r2, [r1, #MSC1_OFFSET] ldr r2, [r1, #MSC1_OFFSET] @ write msc2 ldr r2, =CFG_MSC2_VAL str r2, [r1, #MSC2_OFFSET] ldr r2, [r1, #MSC2_OFFSET] @ write mecr ldr r2, =CFG_MECR_VAL str r2, [r1, #MECR_OFFSET] @ write mcmem0 ldr r2, =CFG_MCMEM0_VAL str r2, [r1, #MCMEM0_OFFSET] @ write mcmem1 ldr r2, =CFG_MCMEM1_VAL str r2, [r1, #MCMEM1_OFFSET] @ write mcatt0 ldr r2, =CFG_MCATT0_VAL str r2, [r1, #MCATT0_OFFSET] @ write mcatt1 ldr r2, =CFG_MCATT1_VAL str r2, [r1, #MCATT1_OFFSET] @ write mcio0 ldr r2, =CFG_MCIO0_VAL str r2, [r1, #MCIO0_OFFSET] @ write mcio1 ldr r2, =CFG_MCIO1_VAL str r2, [r1, #MCIO1_OFFSET] @------------------------------------------------------- @ 3rd bullet, Step 1 @ @ get the mdrefr settings ldr r3, =CFG_MDREFR_VAL_100 @ extract DRI field (we need a valid DRI field) @ ldr r2, =0xFFF @ valid DRI field in r3 @ and r3, r3, r2 @ get the reset state of MDREFR @ ldr r4, [r1, #MDREFR_OFFSET] @ clear the DRI field @ bic r4, r4, r2 @ insert the valid DRI field loaded above @ orr r4, r4, r3 @ write back mdrefr @ str r4, [r1, #MDREFR_OFFSET] @ *Note: preserve the mdrefr value in r4 * @**************************************************************************** @ Step 2 @ /* This should be for SRAM, why is it commented out??? */ @ fetch sxcnfg value @ @ldr r2, =0 @ write back sxcnfg @str r2, [r1, #SXCNFG_OFFSET] /* @if sxcnfg=0, don't program for synch-static memory */ @cmp r2, #0 @beq 1f @program sxmrs @ldr r2, =SXMRS_SETTINGS @str r2, [r1, #SXMRS_OFFSET] @**************************************************************************** @ Step 3 @ @ Assumes previous mdrefr value in r4, if not then read current mdrefr @ clear the free-running clock bits @ (clear K0Free, K1Free, K2Free @ bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000) @ set K1RUN if bank 0 installed @ orr r4, r4, #0x00010000 #ifdef THIS @ 100MHz. @ @ Adjust MSC0 for MemClks > 100 MHz @ ldreq r0, [r1, #MSC0_OFFSET] ldreq r3, =0x7F007F00 biceq r0, r0, r3 @ clear MSC0[14:12, 11:8] (RRR, RDN) ldreq r3, =0x46004600 orreq r0, r0, r3 @ set MSC0[14, 10:9] (doubling RRR, RDN) streq r0, [r1, #MSC0_OFFSET] ldreq r0, [r1, #MSC0_OFFSET] @ read it back to ensure that the data latches @ @ Adjust MSC1.LH for MemClks > 100 MHz @ ldreq r0, [r1, #MSC1_OFFSET] ldreq r3, =0x7FF0 biceq r0, r0, r3 @ clear MSC1[14:12, 11:8, 7:4] (RRR, RDN, RDF) ldreq r3, =0x4880 orreq r0, r0, r3 @ set MSC1[14, 11, 7] (doubling RRR, RDN, RDF) streq r0, [r1, #MSC1_OFFSET] ldreq r0, [r1, #MSC1_OFFSET] @ read it back to ensure that the data latches @ @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ #endif @