From fd428c05c863aefb575b12b2a1916b02d5bfa759 Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Fri, 12 Mar 2010 10:01:12 +0100 Subject: mpc5xxx: Remove all references to MGT5100 We do not support a processor that never reached a real customer. Signed-off-by: Detlev Zundel --- include/configs/BC3450.h | 9 +--- include/configs/IceCube.h | 13 +----- include/configs/PM520.h | 11 ----- include/configs/TB5200.h | 5 --- include/configs/TQM5200.h | 5 --- include/configs/Total5200.h | 23 +--------- include/configs/aev.h | 5 --- include/configs/cpci5200.h | 11 ----- include/configs/hmi1001.h | 5 --- include/configs/inka4x0.h | 5 --- include/configs/ipek01.h | 5 --- include/configs/manroland/mpc5200-common.h | 5 --- include/configs/mecp5200.h | 14 ------ include/configs/o2dnt.h | 7 --- include/configs/pf5200.h | 11 ----- include/configs/smmaco4.h | 5 --- include/configs/spieval.h | 5 --- include/configs/v38b.h | 2 - include/mpc5xxx.h | 69 +----------------------------- 19 files changed, 6 insertions(+), 209 deletions(-) (limited to 'include') diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 8c5a742290..44befe9edf 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -471,13 +471,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) -# define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -# define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -# define CONFIG_SYS_HID0_INIT 0 -# define CONFIG_SYS_HID0_FINAL 0 -#endif +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI +#define CONFIG_SYS_HID0_FINAL HID0_ICE #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 5ef0b7798e..5d3a744fff 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -30,6 +30,7 @@ */ #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ #define CONFIG_ICECUBE 1 /* ... on IceCube board */ #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ @@ -47,7 +48,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -77,10 +77,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 -#else -#define CONFIG_MII 1 -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -169,7 +165,6 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ @@ -178,7 +173,6 @@ #else #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif -#endif /* CONFIG_MPC5200 */ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 @@ -338,13 +332,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #if defined(CONFIG_LITE5200B) #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE diff --git a/include/configs/PM520.h b/include/configs/PM520.h index f9687d2743..22de2075f9 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -50,7 +50,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -75,7 +74,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #undef CONFIG_NS8382X -#endif /* Partitions */ #define CONFIG_DOS_PARTITION @@ -111,9 +109,7 @@ #define CONFIG_CMD_SNTP #define CONFIG_CMD_USB -#if defined(CONFIG_MPC5200) #define CONFIG_CMD_PCI -#endif /* @@ -147,12 +143,10 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -301,13 +295,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #if defined(CONFIG_BOOT_ROM) #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 3438abaeaa..6da18ebca1 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -430,13 +430,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 2154c7870e..107bff19ff 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -633,13 +633,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 1daa5746ee..7510ab10e4 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -41,6 +41,7 @@ */ #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ #define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ @@ -73,7 +74,6 @@ #define CONFIG_SPLASH_SCREEN -#ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -98,12 +98,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 -#else /* MGT5100 */ - -#define CONFIG_MII 1 - -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -127,9 +121,7 @@ */ #include -#if defined(CONFIG_MPC5200) - #define CONFIG_CMD_PCI -#endif +#define CONFIG_CMD_PCI #define CONFIG_CMD_BMP #define CONFIG_CMD_EEPROM @@ -176,12 +168,10 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration @@ -326,17 +316,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif - -#if defined (CONFIG_MGT5100) -# define CONFIG_BOARD_EARLY_INIT_R /* switch from CS_BOOT to CS0 */ -#endif #if CONFIG_TOTAL5200_REV==1 # define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE diff --git a/include/configs/aev.h b/include/configs/aev.h index 2b4826d90e..98958a6237 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -362,13 +362,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index 52df16af14..f7290d6eb4 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -59,7 +59,6 @@ #define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -90,8 +89,6 @@ #define CONFIG_NS8382X 1 #endif -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -169,8 +166,6 @@ #define CONFIG_BOOTCOMMAND "run flash_vxworks0" -#if defined(CONFIG_MPC5200) - #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfd010000 #define CONFIG_SYS_NVRAM_SIZE 32*1024 @@ -179,7 +174,6 @@ * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -303,13 +297,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index a81527ebed..f9cdcbc3ce 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -261,13 +261,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 14f7826705..c5b1565e34 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -366,13 +366,8 @@ static inline void tws_data_config_output(unsigned output) /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h index d0cb1e1d60..6903b36146 100644 --- a/include/configs/ipek01.h +++ b/include/configs/ipek01.h @@ -324,13 +324,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h index b29ef9b655..d25e093ac6 100644 --- a/include/configs/manroland/mpc5200-common.h +++ b/include/configs/manroland/mpc5200-common.h @@ -170,13 +170,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h index 4a93b58885..73405eabb9 100644 --- a/include/configs/mecp5200.h +++ b/include/configs/mecp5200.h @@ -63,9 +63,6 @@ #endif #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ - #define CONFIG_MII #if 0 /* test-only !!! */ #define CONFIG_NET_MULTI 1 @@ -74,10 +71,6 @@ #define CONFIG_NS8382X 1 #endif -#else /* MPC5100 */ - -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -152,12 +145,10 @@ #define CONFIG_BOOTCOMMAND "run flash_vxworks0" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -288,13 +279,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index 18e7cc2a9c..bdc0f7944a 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -138,7 +138,6 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ @@ -154,7 +153,6 @@ */ #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ #endif -#endif /* * I2C configuration @@ -276,13 +274,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index 8ca55d78ec..80a0bc609a 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -61,7 +61,6 @@ #endif #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -87,7 +86,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 #endif -#endif /* Partitions */ #define CONFIG_MAC_PARTITION @@ -121,9 +119,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE -#ifdef CONFIG_MPC5200 #define CONFIG_CMD_PCI -#endif #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ @@ -166,12 +162,10 @@ #define CONFIG_BOOTCOMMAND "run flash_vxworks0" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -289,13 +283,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h index 5a2ef3aa8c..060026bb64 100644 --- a/include/configs/smmaco4.h +++ b/include/configs/smmaco4.h @@ -358,13 +358,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/spieval.h b/include/configs/spieval.h index 27dda253fb..d377e199d8 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -438,13 +438,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 92bcdb33fb..d462ed0f1e 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -170,12 +170,10 @@ #define CONFIG_BOOTCOMMAND "run net_nfs" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index 4dcf90c037..2d343c7b08 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -1,7 +1,7 @@ /* * include/asm-ppc/mpc5xxx.h * - * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx + * Prototypes, etc. for the Motorola MPC5xxx * embedded cpu chips * * 2003 (c) MontaVista, Software, Inc. @@ -33,24 +33,15 @@ #include /* Processor name */ -#if defined(CONFIG_MPC5200) #define CPU_ID_STR "MPC5200" -#elif defined(CONFIG_MGT5100) -#define CPU_ID_STR "MGT5100" -#endif /* Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 #define _START_OFFSET EXC_OFF_SYS_RESET /* useful macros for manipulating CSx_START/STOP */ -#if defined(CONFIG_MGT5100) -#define START_REG(start) ((start) >> 15) -#define STOP_REG(start, size) (((start) + (size) - 1) >> 15) -#elif defined(CONFIG_MPC5200) #define START_REG(start) ((start) >> 16) #define STOP_REG(start, size) (((start) + (size) - 1) >> 16) -#endif /* Internal memory map */ @@ -70,21 +61,12 @@ #define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050) #define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_SDRAM_START (CONFIG_SYS_MBAR + 0x0034) -#define MPC5XXX_SDRAM_STOP (CONFIG_SYS_MBAR + 0x0038) -#define MPC5XXX_PCI1_START (CONFIG_SYS_MBAR + 0x003c) -#define MPC5XXX_PCI1_STOP (CONFIG_SYS_MBAR + 0x0040) -#define MPC5XXX_PCI2_START (CONFIG_SYS_MBAR + 0x0044) -#define MPC5XXX_PCI2_STOP (CONFIG_SYS_MBAR + 0x0048) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058) #define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c) #define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060) #define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064) #define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034) #define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038) -#endif #define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100) #define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200) @@ -99,18 +81,12 @@ #define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200) #define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000) -#define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2400) -#define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2800) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000) #define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200) #define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400) #define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600) #define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800) #define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00) -#endif #define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000) #define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00) @@ -118,22 +94,14 @@ #define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00) #define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x4000) -#define MPC5XXX_SRAM_SIZE (8*1024) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000) #define MPC5XXX_SRAM_SIZE (16*1024) -#endif /* SDRAM Controller */ #define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000) #define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004) #define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008) #define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010) -#endif #define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090) /* Clock Distribution Module */ @@ -155,19 +123,15 @@ #define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG #define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018) #define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c) -#if defined(CONFIG_MPC5200) #define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020) #define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024) #define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028) #define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c) -#endif -#if defined(CONFIG_MPC5200) /* XLB Arbiter registers */ #define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40) #define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64) #define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68) -#endif /* GPIO registers */ #define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000) @@ -242,14 +206,6 @@ #define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c) #define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10) #define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68) -#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c) -#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70) -#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74) -#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78) -#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60) #define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64) #define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68) @@ -262,7 +218,6 @@ #define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88) #define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c) #define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8) -#endif /* Interrupt Controller registers */ #define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000) @@ -495,31 +450,16 @@ struct mpc5xxx_mmap_ctl { volatile u32 cs4_stop; volatile u32 cs5_start; /* 0x002c */ volatile u32 cs5_stop; -#if defined(CONFIG_MGT5100) - volatile u32 sdram_start; /* 0x0034 */ - volatile u32 sdram_stop; /* 0x0038 */ - volatile u32 pci1_start; /* 0x003c */ - volatile u32 pci1_stop; /* 0x0040 */ - volatile u32 pci2_start; /* 0x0044 */ - volatile u32 pci2_stop; /* 0x0048 */ -#elif defined(CONFIG_MPC5200) volatile u32 sdram0; /* 0x0034 */ volatile u32 sdram1; /* 0x0038 */ volatile u32 dummy1[4]; /* 0x003c */ -#endif volatile u32 boot_start; /* 0x004c */ volatile u32 boot_stop; -#if defined(CONFIG_MGT5100) - volatile u32 addecr; /* 0x0054 */ -#elif defined(CONFIG_MPC5200) volatile u32 ipbi_ws_ctrl; /* 0x0054 */ -#endif -#if defined(CONFIG_MPC5200) volatile u32 cs6_start; /* 0x0058 */ volatile u32 cs6_stop; volatile u32 cs7_start; /* 0x0060 */ volatile u32 cs7_stop; -#endif }; /* Clock distribution module */ @@ -546,12 +486,7 @@ struct mpc5xxx_sdram { volatile u32 ctrl; volatile u32 config1; volatile u32 config2; -#if defined(CONFIG_MGT5100) - volatile u32 xlbsel; - volatile u32 dummy[31]; -#else volatile u32 dummy[32]; -#endif volatile u32 sdelay; }; @@ -564,12 +499,10 @@ struct mpc5xxx_lpb { volatile u32 cs5_cfg; volatile u32 cs_ctrl; volatile u32 cs_status; -#if defined(CONFIG_MPC5200) volatile u32 cs6_cfg; volatile u32 cs7_cfg; volatile u32 cs_burst; volatile u32 cs_deadcycle; -#endif }; -- cgit v1.2.1 From 352745ad487f72e839986ddbb020e1fe86c1d482 Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Tue, 16 Mar 2010 12:12:48 -0400 Subject: nios2: use generic unaligned.h Signed-off-by: Scott McNutt --- include/asm-nios2/unaligned.h | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 include/asm-nios2/unaligned.h (limited to 'include') diff --git a/include/asm-nios2/unaligned.h b/include/asm-nios2/unaligned.h new file mode 100644 index 0000000000..779117c4bc --- /dev/null +++ b/include/asm-nios2/unaligned.h @@ -0,0 +1,6 @@ +#ifndef _ASM_NIOS2_UNALIGNED_H +#define _ASM_NIOS2_UNALIGNED_H + +#include + +#endif /* _ASM_NIOS2_UNALIGNED_H */ -- cgit v1.2.1 From a6a04967bc2957d20799f4bb2a6b3dd0353c1cfd Mon Sep 17 00:00:00 2001 From: Renato Andreola Date: Tue, 16 Mar 2010 16:01:29 -0400 Subject: nios2: Added support to YANU UART Signed-off-by: Scott McNutt --- include/nios2-yanu.h | 115 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 include/nios2-yanu.h (limited to 'include') diff --git a/include/nios2-yanu.h b/include/nios2-yanu.h new file mode 100644 index 0000000000..1c9a967932 --- /dev/null +++ b/include/nios2-yanu.h @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2006, Imagos S.a.s + * Renato Andreola + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * Altera NiosII YANU serial interface by Imagos + * please see http://www.opencores.org/project,yanu for + * information/downloads + ************************************************************************/ + +#ifndef __NIOS2_YANU_H__ +#define __NIOS2_YANU_H__ + +#define YANU_MAX_PRESCALER_N ((1 << 4) - 1) /* 15 */ +#define YANU_MAX_PRESCALER_M ((1 << 11) -1) /* 2047 */ +#define YANU_FIFO_SIZE (16) +#define YANU_RXFIFO_SIZE (YANU_FIFO_SIZE) +#define YANU_TXFIFO_SIZE (YANU_FIFO_SIZE) + +#define YANU_RXFIFO_DLY (10*11) +#define YANU_TXFIFO_THR (10) +#define YANU_DATA_CHAR_MASK (0xFF) + +/* data register */ +#define YANU_DATA_OFFSET (0) /* data register offset */ + +#define YANU_CONTROL_OFFSET (4) /* control register offset */ +/* interrupt enable */ +#define YANU_CONTROL_IE_RRDY (1<<0) /* ie on received character ready */ +#define YANU_CONTROL_IE_OE (1<<1) /* ie on rx overrun */ +#define YANU_CONTROL_IE_BRK (1<<2) /* ie on break detect */ +#define YANU_CONTROL_IE_FE (1<<3) /* ie on framing error */ +#define YANU_CONTROL_IE_PE (1<<4) /* ie on parity error */ +#define YANU_CONTROL_IE_TRDY (1<<5) /* ie interrupt on tranmitter ready */ +/* control bits */ +#define YANU_CONTROL_BITS_POS (6) /* bits number pos */ +#define YANU_CONTROL_BITS (1< Date: Mon, 1 Mar 2010 11:47:36 +0200 Subject: POST: add progress API Add POST progress API implemented as weak calls before and after each call to the POST test callback in the post_run_single routine of the post.c file. Signed-off-by: Michael Zaidman Acked-by: Detlev Zundel --- include/post.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/post.h b/include/post.h index 9fcd3cec2f..ff83bce6b4 100644 --- a/include/post.h +++ b/include/post.h @@ -53,6 +53,11 @@ #define POST_FAIL_SAVE 0x80 +#define POST_BEFORE 1 +#define POST_AFTER 0 +#define POST_PASSED 1 +#define POST_FAILED 0 + #ifndef __ASSEMBLY__ struct post_test { -- cgit v1.2.1 From 3c950e2ebfde083084cc926b020e3a22a536bf85 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Tue, 16 Mar 2010 17:10:05 +0100 Subject: fdt_support: add partitions fixup in mtd node Allow overwriting defined partitions in the device tree blob using partition info defined in the 'mtdparts' environment variable. Signed-off-by: Anatolij Gustschin Cc: Gerald Van Baren --- include/fdt_support.h | 2 ++ include/jffs2/load_kernel.h | 1 + include/mtd_node.h | 11 +++++++++++ 3 files changed, 14 insertions(+) create mode 100644 include/mtd_node.h (limited to 'include') diff --git a/include/fdt_support.h b/include/fdt_support.h index 0a9dd0dd84..a3d5f8cbfe 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -81,5 +81,7 @@ int fdt_resize(void *blob); int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size); +void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size); + #endif /* ifdef CONFIG_OF_LIBFDT */ #endif /* ifndef __FDT_SUPPORT_H */ diff --git a/include/jffs2/load_kernel.h b/include/jffs2/load_kernel.h index 8b2720e951..906eb3d3cd 100644 --- a/include/jffs2/load_kernel.h +++ b/include/jffs2/load_kernel.h @@ -78,5 +78,6 @@ struct mtdids { extern int mtdparts_init(void); extern int find_dev_and_part(const char *id, struct mtd_device **dev, u8 *part_num, struct part_info **part); +extern struct mtd_device *device_find(u8 type, u8 num); #endif /* load_kernel_h */ diff --git a/include/mtd_node.h b/include/mtd_node.h new file mode 100644 index 0000000000..5aae0859da --- /dev/null +++ b/include/mtd_node.h @@ -0,0 +1,11 @@ +#ifndef _NODE_INFO +#define _NODE_INFO + +/* + * Info we use to search for a flash node in DTB. + */ +struct node_info { + const char *compat; /* compatible string */ + int type; /* mtd flash type */ +}; +#endif -- cgit v1.2.1 From cc41a59a74ca9095d518d6d69655c6735dd00809 Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Wed, 17 Mar 2010 10:03:10 -0400 Subject: TI: Davinci: NAND Driver Cleanup Modified to use IO accessor routines consistently. Eliminated volatile usage to keep checkpatch.pl happy. Signed-off-by: Cyril Chemparathy --- include/asm-arm/arch-davinci/emif_defs.h | 77 +++++++++++++++----------------- 1 file changed, 36 insertions(+), 41 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h index aa57703c68..b48ec17e97 100644 --- a/include/asm-arm/arch-davinci/emif_defs.h +++ b/include/asm-arm/arch-davinci/emif_defs.h @@ -24,47 +24,42 @@ #include -typedef struct davinci_emif_regs { - dv_reg ERCSR; - dv_reg AWCCR; - dv_reg SDBCR; - dv_reg SDRCR; - dv_reg AB1CR; - dv_reg AB2CR; - dv_reg AB3CR; - dv_reg AB4CR; - dv_reg SDTIMR; - dv_reg DDRSR; - dv_reg DDRPHYCR; - dv_reg DDRPHYSR; - dv_reg TOTAR; - dv_reg TOTACTR; - dv_reg DDRPHYID_REV; - dv_reg SDSRETR; - dv_reg EIRR; - dv_reg EIMR; - dv_reg EIMSR; - dv_reg EIMCR; - dv_reg IOCTRLR; - dv_reg IOSTATR; - u_int8_t RSVD0[8]; - dv_reg NANDFCR; - dv_reg NANDFSR; - u_int8_t RSVD1[8]; - dv_reg NANDFECC[4]; - u_int8_t RSVD2[60]; - dv_reg NAND4BITECCLOAD; - dv_reg NAND4BITECC1; - dv_reg NAND4BITECC2; - dv_reg NAND4BITECC3; - dv_reg NAND4BITECC4; - dv_reg NANDERRADD1; - dv_reg NANDERRADD2; - dv_reg NANDERRVAL1; - dv_reg NANDERRVAL2; -} emif_registers; - -typedef emif_registers *emifregs; +struct davinci_emif_regs { + u_int32_t ercsr; + u_int32_t awccr; + u_int32_t sdbcr; + u_int32_t sdrcr; + u_int32_t ab1cr; + u_int32_t ab2cr; + u_int32_t ab3cr; + u_int32_t ab4cr; + u_int32_t sdtimr; + u_int32_t ddrsr; + u_int32_t ddrphycr; + u_int32_t ddrphysr; + u_int32_t totar; + u_int32_t totactr; + u_int32_t ddrphyid_rev; + u_int32_t sdsretr; + u_int32_t eirr; + u_int32_t eimr; + u_int32_t eimsr; + u_int32_t eimcr; + u_int32_t ioctrlr; + u_int32_t iostatr; + u_int8_t rsvd0[8]; + u_int32_t nandfcr; + u_int32_t nandfsr; + u_int8_t rsvd1[8]; + u_int32_t nandfecc[4]; + u_int8_t rsvd2[60]; + u_int32_t nand4biteccload; + u_int32_t nand4bitecc[4]; + u_int32_t nanderradd1; + u_int32_t nanderradd2; + u_int32_t nanderrval1; + u_int32_t nanderrval2; +}; #define davinci_emif_regs \ ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) -- cgit v1.2.1 From 9d79e5758c3a6776be9a86856823d28e7154a481 Mon Sep 17 00:00:00 2001 From: Wolfgang Wegner Date: Mon, 25 Jan 2010 11:27:44 +0100 Subject: add ASTRO MCF5373L board This patch adds support for ASTRO board(s) based on MCF5373L. Signed-off-by: Wolfgang Wegner --- include/configs/astro_mcf5373l.h | 389 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 389 insertions(+) create mode 100644 include/configs/astro_mcf5373l.h (limited to 'include') diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h new file mode 100644 index 0000000000..1fe42f682a --- /dev/null +++ b/include/configs/astro_mcf5373l.h @@ -0,0 +1,389 @@ +/* + * Configuration settings for the Sentec Cobra Board. + * + * (C) Copyright 2003 Josef Baumgartner + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * configuration for ASTRO "Urmel" board. + * Originating from Cobra5272 configuration, messed up by + * Wolfgang Wegner + * Please do not bother the original author with bug reports + * concerning this file. + */ + +#ifndef _CONFIG_ASTRO_MCF5373L_H +#define _CONFIG_ASTRO_MCF5373L_H + +/* + * set the card type to actually compile for; either of + * the possibilities listed below has to be used! + */ +#define CONFIG_ASTRO_V532 1 + +#if CONFIG_ASTRO_V532 +#define ASTRO_ID 0xF8 +#elif CONFIG_ASTRO_V512 +#define ASTRO_ID 0xFA +#elif CONFIG_ASTRO_TWIN7S2 +#define ASTRO_ID 0xF9 +#elif CONFIG_ASTRO_V912 +#define ASTRO_ID 0xFC +#elif CONFIG_ASTRO_COFDMDUOS2 +#define ASTRO_ID 0xFB +#else +#error No card type defined! +#endif + +/* + * Define processor + * possible values for Urmel board: only Coldfire M5373 processor supported + * (please do not change) + */ + +/* it seems not clear yet which processor defines we should use */ +#define CONFIG_MCF537x /* define processor family */ +#define CONFIG_MCF532x /* define processor family */ +#define CONFIG_M5373 /* define processor type */ +#define CONFIG_ASTRO5373L /* define board type */ + +/* Command line configuration */ +#include + +/* + * CONFIG_MK_RAM defines if u-boot is loaded via BDM (or started from + * a different bootloader that has already performed RAM setup) or + * started directly from flash, which is the regular case for production + * boards. + */ +#ifdef CONFIG_MK_RAM +#define CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_TEXT_BASE 0x40020000 +#define ENABLE_JFFS 0 +#else +#define CONFIG_TEXT_BASE 0x00000000 +#define ENABLE_JFFS 1 +#endif + +/* Define which commmands should be available at u-boot command prompt */ + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_XIMG +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#if ENABLE_JFFS +#define CONFIG_CMD_JFFS2 +#endif +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_FPGA +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_MCFRTC +#undef RTC_DEBUG + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SPEED 80000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* + * Defines processor clock - important for correct timings concerning serial + * interface etc. + * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms + */ + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CLK 80000000 +#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) +#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ + +#define CONFIG_SYS_CORE_SRAM_SIZE 0x8000 +#define CONFIG_SYS_CORE_SRAM 0x80000000 + +#define CONFIG_SYS_UNIFY_CACHE + +/* + * Define baudrate for UART1 (console output, tftp, ...) + * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud + * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected + * in u-boot command interface + */ + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (2) +#define CONFIG_SYS_UART2_ALT3_GPIO + +/* + * Watchdog configuration; Watchdog is disabled for running from RAM + * and set to highest possible value else. Beware there is no check + * in the watchdog code to validate the timeout value set here! + */ + +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */ +#endif + +/* + * Configuration for environment + * Environment is located in the last sector of the flash + */ + +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_ENV_OFFSET 0x1FF8000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_IN_FLASH 1 +#else +/* + * environment in RAM - This is used to use a single PC-based application + * to load an image, load U-Boot, load an environment and then start U-Boot + * to execute the commands from the environment. Feedback is done via setting + * and reading memory locations. + */ +#define CONFIG_ENV_ADDR 0x40060000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif + +/* here we put our FPGA configuration... */ +#define CONFIG_MISC_INIT_R 1 + +/* Define user parameters that have to be customized most likely */ + +/* AUTOBOOT settings - booting images automatically by u-boot after power on */ + +/* + * used for autoboot, delay in seconds u-boot will wait before starting + * defined (auto-)boot command, setting to -1 disables delay, setting to + * 0 will too prevent access to u-boot command interface: u-boot then has + * to be reflashed + * beware - watchdog is not serviced during autoboot delay time! + */ +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_BOOTDELAY 1 +#else +#define CONFIG_BOOTDELAY 1 +#endif + +/* + * The following settings will be contained in the environment block ; if you + * want to use a neutral environment all those settings can be manually set in + * u-boot: 'set' command + */ + +#define _QUOTEME(x) #x +#define QUOTEME(x) _QUOTEME(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loaderversion=11\0" \ + "card_id="QUOTEME(ASTRO_ID)"\0" \ + "alterafile=0\0" \ + "xilinxfile=0\0" \ + "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\ + "fpga load 0 0x41000000 $filesize\0" \ + "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\ + "fpga load 1 0x41000000 $filesize\0" \ + "env_default=1\0" \ + "env_check=if test $env_default -eq 1;"\ + " then setenv env_default 0;saveenv;fi\0" + +/* + * "update" is a non-standard command that has to be supplied + * by external update.c; This is not included in mainline because + * it needs non-blocking CFI routines. + */ +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */ +#else +#if CONFIG_ASTRO_V532 +#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ + "run xilinxload&&run alteraload&&bootm 0x80000;"\ + "update;reset" +#else +#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ + "run xilinxload&&bootm 0x80000;update;reset" +#endif +#endif + +/* default bootargs that are considered during boot */ +#define CONFIG_BOOTARGS " console=ttyS2,115200 rootfstype=romfs"\ + " loaderversion=$loaderversion" + +#define CONFIG_SYS_PROMPT "URMEL > " + +/* default RAM address for user programs */ +#define CONFIG_SYS_LOAD_ADDR 0x20000 + +#define CONFIG_SYS_LONGHELP + +#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 +#else +#define CONFIG_SYS_CBSIZE 256 +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_FPGA_ALTERA +#define CONFIG_FPGA_CYCLON2 +#define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_SYS_FPGA_WAIT 1000 + +/* End of user parameters to be customized */ + +/* Defines memory range for test */ + +#define CONFIG_SYS_MEMTEST_START 0x40020000 +#define CONFIG_SYS_MEMTEST_END 0x41ffffff + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/* Base register address */ + +#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ + +/* System Conf. Reg. & System Protection Reg. */ + +#define CONFIG_SYS_SCR 0x0003; +#define CONFIG_SYS_SPR 0xffff; + +/* + * Definitions for initial stack pointer and data area (in internal SRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_END 0x8000 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +/* + * Chipselect bank definitions + * + * CS0 - Flash 32MB (first 16MB) + * CS1 - Flash 32MB (second half) + * CS2 - FPGA + * CS3 - FPGA + * CS4 - unused + * CS5 - unused + */ +#define CONFIG_SYS_CS0_BASE 0 +#define CONFIG_SYS_CS0_MASK 0x00ff0001 +#define CONFIG_SYS_CS0_CTRL 0x00001fc0 + +#define CONFIG_SYS_CS1_BASE 0x01000000 +#define CONFIG_SYS_CS1_MASK 0x00ff0001 +#define CONFIG_SYS_CS1_CTRL 0x00001fc0 + +#define CONFIG_SYS_CS2_BASE 0x20000000 +#define CONFIG_SYS_CS2_MASK 0x00ff0001 +#define CONFIG_SYS_CS2_CTRL 0x0000fec0 + +#define CONFIG_SYS_CS3_BASE 0x21000000 +#define CONFIG_SYS_CS3_MASK 0x00ff0001 +#define CONFIG_SYS_CS3_CTRL 0x0000fec0 + +#define CONFIG_SYS_FLASH_BASE 0x00000000 + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_BASE CONFIG_TEXT_BASE +#else +/* This is mainly used during relocation in start.S */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif +/* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) + +#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) +/* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/* FLASH organization */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 259 +#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 + +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_SIZE 0x2000000 +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_CFI_NONBLOCK 1 + +#if ENABLE_JFFS +/* JFFS Partition offset set */ +#define CONFIG_SYS_JFFS2_FIRST_BANK 0 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40 +#endif + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#endif /* _CONFIG_ASTRO_MCF5373L_H */ -- cgit v1.2.1 From 89083346d0627a5e6e271e61bd34ab5121f9462b Mon Sep 17 00:00:00 2001 From: Wolfgang Wegner Date: Fri, 30 Oct 2009 16:55:02 +0100 Subject: add block write function to spartan3 slave serial load Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds Signed-off-by: Wolfgang Wegner --- include/spartan3.h | 1 + include/xilinx.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/spartan3.h b/include/spartan3.h index 30b1c2d62d..d5a589d099 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -57,6 +57,7 @@ typedef struct { Xilinx_done_fn done; Xilinx_wr_fn wr; Xilinx_post_fn post; + Xilinx_bwr_fn bwr; /* block write function */ } Xilinx_Spartan3_Slave_Serial_fns; /* Device Image Sizes diff --git a/include/xilinx.h b/include/xilinx.h index d0799bc572..2cb2e5b6aa 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -100,5 +100,6 @@ typedef int (*Xilinx_busy_fn)( int cookie ); typedef int (*Xilinx_abort_fn)( int cookie ); typedef int (*Xilinx_pre_fn)( int cookie ); typedef int (*Xilinx_post_fn)( int cookie ); +typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie ); #endif /* _XILINX_H_ */ -- cgit v1.2.1 From d04c1efae3d834db6e21e9976e338bf1e588e987 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Tue, 9 Mar 2010 18:32:16 -0600 Subject: ColdFire: Correct bit definition Use correct definition for _MASK and _UNMASK. It was combined in the previous used and causes confusion. Signed-off-by: TsiChung Liew --- include/asm-m68k/m520x.h | 89 ++++++++++++++++++------------------ include/asm-m68k/m5227x.h | 108 ++++++++++++++++++++++---------------------- include/asm-m68k/m5235.h | 4 +- include/asm-m68k/m5301x.h | 112 +++++++++++++++++++++++----------------------- include/asm-m68k/m5445x.h | 56 +++++++++++------------ 5 files changed, 183 insertions(+), 186 deletions(-) (limited to 'include') diff --git a/include/asm-m68k/m520x.h b/include/asm-m68k/m520x.h index 267bfd994a..71f147e751 100644 --- a/include/asm-m68k/m520x.h +++ b/include/asm-m68k/m520x.h @@ -70,7 +70,6 @@ #define PACR_TP 1 #define SCM_BMT_BME (0x00000008) -#define SCM_BMT_BMT_MASK (0x07) #define SCM_BMT_BMT(x) ((x) & 0x07) #define SCM_BMT_BMT1024 (0x0000) #define SCM_BMT_BMT512 (0x0001) @@ -179,7 +178,7 @@ #define CCM_CCR_PLL_MODE (0x0002) #define CCM_CCR_RESERVED (0x0001) -#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) +#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) #define CCM_CIR_PRN(x) ((x) & 0x003F) /* *** General Purpose I/O (GPIO) *** */ @@ -196,7 +195,7 @@ #define GPIO_PAR_FBCTL_OE (0x10) #define GPIO_PAR_FBCTL_TA (0x08) #define GPIO_PAR_FBCTL_RWB (0x04) -#define GPIO_PAR_FBCTL_TS_MASK (0xFC) +#define GPIO_PAR_FBCTL_TS_UNMASK (0xFC) #define GPIO_PAR_FBCTL_TS_TS (0x03) #define GPIO_PAR_FBCTL_TS_DMA (0x02) @@ -207,39 +206,39 @@ #define GPIO_PAR_CS3 (0x08) #define GPIO_PAR_CS2 (0x04) -#define GPIO_PAR_CS1_MASK (0xFC) +#define GPIO_PAR_CS1_UNMASK (0xFC) #define GPIO_PAR_CS1_CS1 (0x03) #define GPIO_PAR_CS1_SDCS1 (0x02) -#define GPIO_PAR_FECI2C_RMII_MASK (0x0F) -#define GPIO_PAR_FECI2C_MDC_MASK (0x3F) +#define GPIO_PAR_FECI2C_RMII_UNMASK (0x0F) +#define GPIO_PAR_FECI2C_MDC_UNMASK (0x3F) #define GPIO_PAR_FECI2C_MDC_MDC (0xC0) #define GPIO_PAR_FECI2C_MDC_SCL (0x80) #define GPIO_PAR_FECI2C_MDC_U2TXD (0x40) -#define GPIO_PAR_FECI2C_MDIO_MASK (0xCF) +#define GPIO_PAR_FECI2C_MDIO_UNMASK (0xCF) #define GPIO_PAR_FECI2C_MDIO_MDIO (0x30) #define GPIO_PAR_FECI2C_MDIO_SDA (0x20) #define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10) -#define GPIO_PAR_FECI2C_I2C_MASK (0xF0) -#define GPIO_PAR_FECI2C_SCL_MASK (0xF3) +#define GPIO_PAR_FECI2C_I2C_UNMASK (0xF0) +#define GPIO_PAR_FECI2C_SCL_UNMASK (0xF3) #define GPIO_PAR_FECI2C_SCL_SCL (0x0C) #define GPIO_PAR_FECI2C_SCL_U2RXD (0x04) -#define GPIO_PAR_FECI2C_SDA_MASK (0xFC) +#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFC) #define GPIO_PAR_FECI2C_SDA_SDA (0x03) #define GPIO_PAR_FECI2C_SDA_U2TXD (0x01) -#define GPIO_PAR_QSPI_PCS2_MASK (0x3F) +#define GPIO_PAR_QSPI_PCS2_UNMASK (0x3F) #define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0) #define GPIO_PAR_QSPI_PCS2_DACK0 (0x80) #define GPIO_PAR_QSPI_PCS2_U2RTS (0x40) -#define GPIO_PAR_QSPI_DIN_MASK (0xCF) +#define GPIO_PAR_QSPI_DIN_UNMASK (0xCF) #define GPIO_PAR_QSPI_DIN_DIN (0x30) #define GPIO_PAR_QSPI_DIN_DREQ0 (0x20) #define GPIO_PAR_QSPI_DIN_U2CTS (0x10) -#define GPIO_PAR_QSPI_DOUT_MASK (0xF3) +#define GPIO_PAR_QSPI_DOUT_UNMASK (0xF3) #define GPIO_PAR_QSPI_DOUT_DOUT (0x0C) #define GPIO_PAR_QSPI_DOUT_SDA (0x08) -#define GPIO_PAR_QSPI_SCK_MASK (0xFC) +#define GPIO_PAR_QSPI_SCK_UNMASK (0xFC) #define GPIO_PAR_QSPI_SCK_SCK (0x03) #define GPIO_PAR_QSPI_SCK_SCL (0x02) @@ -247,50 +246,50 @@ #define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4) #define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2) #define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03) -#define GPIO_PAR_TMR_TIN3_MASK (0x3F) +#define GPIO_PAR_TMR_TIN3_UNMASK (0x3F) #define GPIO_PAR_TMR_TIN3_TIN3 (0xC0) #define GPIO_PAR_TMR_TIN3_TOUT3 (0x80) #define GPIO_PAR_TMR_TIN3_U2CTS (0x40) -#define GPIO_PAR_TMR_TIN2_MASK (0xCF) +#define GPIO_PAR_TMR_TIN2_UNMASK (0xCF) #define GPIO_PAR_TMR_TIN2_TIN2 (0x30) #define GPIO_PAR_TMR_TIN2_TOUT2 (0x20) #define GPIO_PAR_TMR_TIN2_U2RTS (0x10) -#define GPIO_PAR_TMR_TIN1_MASK (0xF3) +#define GPIO_PAR_TMR_TIN1_UNMASK (0xF3) #define GPIO_PAR_TMR_TIN1_TIN1 (0x0C) #define GPIO_PAR_TMR_TIN1_TOUT1 (0x08) #define GPIO_PAR_TMR_TIN1_U2RXD (0x04) -#define GPIO_PAR_TMR_TIN0_MASK (0xFC) +#define GPIO_PAR_TMR_TIN0_UNMASK (0xFC) #define GPIO_PAR_TMR_TIN0_TIN0 (0x03) #define GPIO_PAR_TMR_TIN0_TOUT0 (0x02) #define GPIO_PAR_TMR_TIN0_U2TXD (0x01) -#define GPIO_PAR_UART1_MASK (0xF03F) -#define GPIO_PAR_UART0_MASK (0xFFC0) -#define GPIO_PAR_UART_U1CTS_MASK (0xF3FF) +#define GPIO_PAR_UART1_UNMASK (0xF03F) +#define GPIO_PAR_UART0_UNMASK (0xFFC0) +#define GPIO_PAR_UART_U1CTS_UNMASK (0xF3FF) #define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00) #define GPIO_PAR_UART_U1CTS_TIN1 (0x0800) #define GPIO_PAR_UART_U1CTS_PCS1 (0x0400) -#define GPIO_PAR_UART_U1RTS_MASK (0xFCFF) +#define GPIO_PAR_UART_U1RTS_UNMASK (0xFCFF) #define GPIO_PAR_UART_U1RTS_U1RTS (0x0300) #define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200) #define GPIO_PAR_UART_U1RTS_PCS1 (0x0100) #define GPIO_PAR_UART_U1TXD (0x0080) #define GPIO_PAR_UART_U1RXD (0x0040) -#define GPIO_PAR_UART_U0CTS_MASK (0xFFCF) +#define GPIO_PAR_UART_U0CTS_UNMASK (0xFFCF) #define GPIO_PAR_UART_U0CTS_U0CTS (0x0030) #define GPIO_PAR_UART_U0CTS_TIN0 (0x0020) #define GPIO_PAR_UART_U0CTS_PCS0 (0x0010) -#define GPIO_PAR_UART_U0RTS_MASK (0xFFF3) +#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFF3) #define GPIO_PAR_UART_U0RTS_U0RTS (0x000C) #define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008) #define GPIO_PAR_UART_U0RTS_PCS0 (0x0004) #define GPIO_PAR_UART_U0TXD (0x0002) #define GPIO_PAR_UART_U0RXD (0x0001) -#define GPIO_PAR_FEC_7W_MASK (0xF3) +#define GPIO_PAR_FEC_7W_UNMASK (0xF3) #define GPIO_PAR_FEC_7W_FEC (0x0C) #define GPIO_PAR_FEC_7W_U1RTS (0x04) -#define GPIO_PAR_FEC_MII_MASK (0xFC) +#define GPIO_PAR_FEC_MII_UNMASK (0xFC) #define GPIO_PAR_FEC_MII_FEC (0x03) #define GPIO_PAR_FEC_MII_UnCTS (0x01) @@ -300,17 +299,17 @@ #define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4) #define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2) #define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03) -#define GPIO_MSCR_FB_FBCLK_MASK (0x3F) -#define GPIO_MSCR_FB_DUP_MASK (0xCF) -#define GPIO_MSCR_FB_DLO_MASK (0xF3) -#define GPIO_MSCR_FB_ADRCTL_MASK (0xFC) +#define GPIO_MSCR_FB_FBCLK_UNMASK (0x3F) +#define GPIO_MSCR_FB_DUP_UNMASK (0xCF) +#define GPIO_MSCR_FB_DLO_UNMASK (0xF3) +#define GPIO_MSCR_FB_ADRCTL_UNMASK (0xFC) #define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4) #define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2) #define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03) -#define GPIO_MSCR_SDR_SDCLKB_MASK (0xCF) -#define GPIO_MSCR_SDR_SDCLK_MASK (0xF3) -#define GPIO_MSCR_SDR_SDRAM_MASK (0xFC) +#define GPIO_MSCR_SDR_SDCLKB_UNMASK (0xCF) +#define GPIO_MSCR_SDR_SDCLK_UNMASK (0xF3) +#define GPIO_MSCR_SDR_SDRAM_UNMASK (0xFC) #define MSCR_25VDDR (0x03) #define MSCR_18VDDR_FULL (0x02) @@ -318,27 +317,27 @@ #define MSCR_18VDDR_HALF (0x00) #define GPIO_DSCR_I2C(x) ((x) & 0x03) -#define GPIO_DSCR_I2C_MASK (0xFC) +#define GPIO_DSCR_I2C_UNMASK (0xFC) #define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4) -#define GPIO_DSCR_MISC_DBG_MASK (0xCF) +#define GPIO_DSCR_MISC_DBG_UNMASK (0xCF) #define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2) -#define GPIO_DSCR_MISC_RSTOUT_MASK (0xF3) +#define GPIO_DSCR_MISC_RSTOUT_UNMASK (0xF3) #define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03) -#define GPIO_DSCR_MISC_TIMER_MASK (0xFC) +#define GPIO_DSCR_MISC_TIMER_UNMASK (0xFC) #define GPIO_DSCR_FEC(x) ((x) & 0x03) -#define GPIO_DSCR_FEC_MASK (0xFC) +#define GPIO_DSCR_FEC_UNMASK (0xFC) #define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4) -#define GPIO_DSCR_UART_UART1_MASK (0xCF) +#define GPIO_DSCR_UART_UART1_UNMASK (0xCF) #define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2) -#define GPIO_DSCR_UART_UART0_MASK (0xF3) +#define GPIO_DSCR_UART_UART0_UNMASK (0xF3) #define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03) -#define GPIO_DSCR_UART_IRQ_MASK (0xFC) +#define GPIO_DSCR_UART_IRQ_UNMASK (0xFC) #define GPIO_DSCR_QSPI(x) ((x) & 0x03) -#define GPIO_DSCR_QSPI_MASK (0xFC) +#define GPIO_DSCR_QSPI_UNMASK (0xFC) #define DSCR_50PF (0x03) #define DSCR_30PF (0x02) @@ -347,12 +346,12 @@ /* *** Phase Locked Loop (PLL) *** */ #define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4) -#define PLL_PODR_CPUDIV_MASK (0x0F) +#define PLL_PODR_CPUDIV_UNMASK (0x0F) #define PLL_PODR_BUSDIV(x) ((x) & 0x0F) -#define PLL_PODR_BUSDIV_MASK (0xF0) +#define PLL_PODR_BUSDIV_UNMASK (0xF0) #define PLL_PCR_DITHEN (0x80) #define PLL_PCR_DITHDEV(x) ((x) & 0x07) -#define PLL_PCR_DITHDEV_MASK (0xF8) +#define PLL_PCR_DITHDEV_UNMASK (0xF8) #endif /* __M520X__ */ diff --git a/include/asm-m68k/m5227x.h b/include/asm-m68k/m5227x.h index 824d333114..c77d5dd657 100644 --- a/include/asm-m68k/m5227x.h +++ b/include/asm-m68k/m5227x.h @@ -117,36 +117,34 @@ /* Bit definitions and macros for CCR */ #define CCM_CCR_DRAMSEL (0x0100) -#define CCM_CCR_CSC_MASK (0xFF3F) +#define CCM_CCR_CSC_UNMASK (0xFF3F) #define CCM_CCR_CSC_FBCS5_CS4 (0x00C0) #define CCM_CCR_CSC_FBCS5_A22 (0x0080) #define CCM_CCR_CSC_FB_A23_A22 (0x0040) #define CCM_CCR_LIMP (0x0020) #define CCM_CCR_LOAD (0x0010) -#define CCM_CCR_BOOTPS_MASK (0xFFF3) +#define CCM_CCR_BOOTPS_UNMASK (0xFFF3) #define CCM_CCR_BOOTPS_PS16 (0x0008) #define CCM_CCR_BOOTPS_PS8 (0x0004) #define CCM_CCR_BOOTPS_PS32 (0x0000) #define CCM_CCR_OSCMODE_OSCBYPASS (0x0002) /* Bit definitions and macros for RCON */ -#define CCM_RCON_CSC_MASK (0xFF3F) +#define CCM_RCON_CSC_UNMASK (0xFF3F) #define CCM_RCON_CSC_FBCS5_CS4 (0x00C0) #define CCM_RCON_CSC_FBCS5_A22 (0x0080) #define CCM_RCON_CSC_FB_A23_A22 (0x0040) #define CCM_RCON_LIMP (0x0020) #define CCM_RCON_LOAD (0x0010) -#define CCM_RCON_BOOTPS_MASK (0xFFF3) +#define CCM_RCON_BOOTPS_UNMASK (0xFFF3) #define CCM_RCON_BOOTPS_PS16 (0x0008) #define CCM_RCON_BOOTPS_PS8 (0x0004) #define CCM_RCON_BOOTPS_PS32 (0x0000) #define CCM_RCON_OSCMODE_OSCBYPASS (0x0002) /* Bit definitions and macros for CIR */ -#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */ -#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */ -#define CCM_CIR_PIN_MASK (0xFFC0) -#define CCM_CIR_PRN_MASK (0x003F) +#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) +#define CCM_CIR_PRN(x) ((x) & 0x003F) #define CCM_CIR_PIN_MCF52277 (0x0000) /* Bit definitions and macros for MISCCR */ @@ -195,7 +193,7 @@ * General Purpose I/O Module (GPIO) *********************************************************************/ /* Bit definitions and macros for PAR_BE */ -#define GPIO_PAR_BE_MASK (0x0F) +#define GPIO_PAR_BE_UNMASK (0x0F) #define GPIO_PAR_BE_BE3_BE3 (0x08) #define GPIO_PAR_BE_BE3_GPIO (0x00) #define GPIO_PAR_BE_BE2_BE2 (0x04) @@ -217,111 +215,111 @@ #define GPIO_PAR_FBCTL_OE (0x80) #define GPIO_PAR_FBCTL_TA (0x40) #define GPIO_PAR_FBCTL_RW (0x20) -#define GPIO_PAR_FBCTL_TS_MASK (0xE7) +#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) #define GPIO_PAR_FBCTL_TS_FBTS (0x18) #define GPIO_PAR_FBCTL_TS_DMAACK (0x10) #define GPIO_PAR_FBCTL_TS_GPIO (0x00) /* Bit definitions and macros for PAR_FECI2C */ -#define GPIO_PAR_I2C_SCL_MASK (0xF3) +#define GPIO_PAR_I2C_SCL_UNMASK (0xF3) #define GPIO_PAR_I2C_SCL_SCL (0x0C) #define GPIO_PAR_I2C_SCL_CANTXD (0x08) #define GPIO_PAR_I2C_SCL_U2TXD (0x04) #define GPIO_PAR_I2C_SCL_GPIO (0x00) -#define GPIO_PAR_I2C_SDA_MASK (0xFC) +#define GPIO_PAR_I2C_SDA_UNMASK (0xFC) #define GPIO_PAR_I2C_SDA_SDA (0x03) #define GPIO_PAR_I2C_SDA_CANRXD (0x02) #define GPIO_PAR_I2C_SDA_U2RXD (0x01) #define GPIO_PAR_I2C_SDA_GPIO (0x00) /* Bit definitions and macros for PAR_UART */ -#define GPIO_PAR_UART_U1CTS_MASK (0x3FFF) +#define GPIO_PAR_UART_U1CTS_UNMASK (0x3FFF) #define GPIO_PAR_UART_U1CTS_U1CTS (0xC000) #define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000) #define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000) #define GPIO_PAR_UART_U1CTS_GPIO (0x0000) -#define GPIO_PAR_UART_U1RTS_MASK (0xCFFF) +#define GPIO_PAR_UART_U1RTS_UNMASK (0xCFFF) #define GPIO_PAR_UART_U1RTS_U1RTS (0x3000) #define GPIO_PAR_UART_U1RTS_SSIFS (0x2000) #define GPIO_PAR_UART_U1RTS_LCDPS (0x1000) #define GPIO_PAR_UART_U1RTS_GPIO (0x0000) -#define GPIO_PAR_UART_U1RXD_MASK (0xF3FF) +#define GPIO_PAR_UART_U1RXD_UNMASK (0xF3FF) #define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) #define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800) #define GPIO_PAR_UART_U1RXD_GPIO (0x0000) -#define GPIO_PAR_UART_U1TXD_MASK (0xFCFF) +#define GPIO_PAR_UART_U1TXD_UNMASK (0xFCFF) #define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) #define GPIO_PAR_UART_U1TXD_SSITXD (0x0200) #define GPIO_PAR_UART_U1TXD_GPIO (0x0000) -#define GPIO_PAR_UART_U0CTS_MASK (0xFF3F) +#define GPIO_PAR_UART_U0CTS_UNMASK (0xFF3F) #define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0) #define GPIO_PAR_UART_U0CTS_T1OUT (0x0080) #define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040) #define GPIO_PAR_UART_U0CTS_GPIO (0x0000) -#define GPIO_PAR_UART_U0RTS_MASK (0xFFCF) +#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFCF) #define GPIO_PAR_UART_U0RTS_U0RTS (0x0030) #define GPIO_PAR_UART_U0RTS_T1IN (0x0020) #define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010) #define GPIO_PAR_UART_U0RTS_GPIO (0x0000) -#define GPIO_PAR_UART_U0RXD_MASK (0xFFF3) +#define GPIO_PAR_UART_U0RXD_UNMASK (0xFFF3) #define GPIO_PAR_UART_U0RXD_U0RXD (0x000C) #define GPIO_PAR_UART_U0RXD_CANRX (0x0008) #define GPIO_PAR_UART_U0RXD_GPIO (0x0000) -#define GPIO_PAR_UART_U0TXD_MASK (0xFFFC) +#define GPIO_PAR_UART_U0TXD_UNMASK (0xFFFC) #define GPIO_PAR_UART_U0TXD_U0TXD (0x0003) #define GPIO_PAR_UART_U0TXD_CANTX (0x0002) #define GPIO_PAR_UART_U0TXD_GPIO (0x0000) /* Bit definitions and macros for PAR_DSPI */ -#define GPIO_PAR_DSPI_PCS0_MASK (0x3F) +#define GPIO_PAR_DSPI_PCS0_UNMASK (0x3F) #define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0) #define GPIO_PAR_DSPI_PCS0_U2RTS (0x80) #define GPIO_PAR_DSPI_PCS0_GPIO (0x00) -#define GPIO_PAR_DSPI_SIN_MASK (0xCF) +#define GPIO_PAR_DSPI_SIN_UNMASK (0xCF) #define GPIO_PAR_DSPI_SIN_SIN (0x30) #define GPIO_PAR_DSPI_SIN_U2RXD (0x20) #define GPIO_PAR_DSPI_SIN_GPIO (0x00) -#define GPIO_PAR_DSPI_SOUT_MASK (0xF3) +#define GPIO_PAR_DSPI_SOUT_UNMASK (0xF3) #define GPIO_PAR_DSPI_SOUT_SOUT (0x0C) #define GPIO_PAR_DSPI_SOUT_U2TXD (0x08) #define GPIO_PAR_DSPI_SOUT_GPIO (0x00) -#define GPIO_PAR_DSPI_SCK_MASK (0xFC) +#define GPIO_PAR_DSPI_SCK_UNMASK (0xFC) #define GPIO_PAR_DSPI_SCK_SCK (0x03) #define GPIO_PAR_DSPI_SCK_U2CTS (0x02) #define GPIO_PAR_DSPI_SCK_GPIO (0x00) /* Bit definitions and macros for PAR_TIMER */ -#define GPIO_PAR_TIMER_T3IN_MASK (0x3F) +#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) #define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) #define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) #define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40) #define GPIO_PAR_TIMER_T3IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T2IN_MASK (0xCF) +#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) #define GPIO_PAR_TIMER_T2IN_T2IN (0x30) #define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) #define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10) #define GPIO_PAR_TIMER_T2IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T1IN_MASK (0xF3) +#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) #define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) #define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) #define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04) #define GPIO_PAR_TIMER_T1IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T0IN_MASK (0xFC) +#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) #define GPIO_PAR_TIMER_T0IN_T0IN (0x03) #define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) #define GPIO_PAR_TIMER_T0IN_LCDREV (0x01) #define GPIO_PAR_TIMER_T0IN_GPIO (0x00) /* Bit definitions and macros for GPIO_PAR_LCDCTL */ -#define GPIO_PAR_LCDCTL_ACDOE_MASK (0xE7) +#define GPIO_PAR_LCDCTL_ACDOE_UNMASK (0xE7) #define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18) #define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10) #define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00) @@ -330,141 +328,141 @@ #define GPIO_PAR_LCDCTL_LSCLK (0x01) /* Bit definitions and macros for PAR_IRQ */ -#define GPIO_PAR_IRQ_IRQ4_MASK (0xF3) +#define GPIO_PAR_IRQ_IRQ4_UNMASK (0xF3) #define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C) #define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08) #define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) -#define GPIO_PAR_IRQ_IRQ1_MASK (0xFC) +#define GPIO_PAR_IRQ_IRQ1_UNMASK (0xFC) #define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03) #define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02) #define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01) #define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) /* Bit definitions and macros for GPIO_PAR_LCDH */ -#define GPIO_PAR_LCDH_LD17_MASK (0xFFFFF3FF) +#define GPIO_PAR_LCDH_LD17_UNMASK (0xFFFFF3FF) #define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00) #define GPIO_PAR_LCDH_LD17_LD11 (0x00000800) #define GPIO_PAR_LCDH_LD17_GPIO (0x00000000) -#define GPIO_PAR_LCDH_LD16_MASK (0xFFFFFCFF) +#define GPIO_PAR_LCDH_LD16_UNMASK (0xFFFFFCFF) #define GPIO_PAR_LCDH_LD16_LD16 (0x00000300) #define GPIO_PAR_LCDH_LD16_LD10 (0x00000200) #define GPIO_PAR_LCDH_LD16_GPIO (0x00000000) -#define GPIO_PAR_LCDH_LD15_MASK (0xFFFFFF3F) +#define GPIO_PAR_LCDH_LD15_UNMASK (0xFFFFFF3F) #define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0) #define GPIO_PAR_LCDH_LD15_LD9 (0x00000080) #define GPIO_PAR_LCDH_LD15_GPIO (0x00000000) -#define GPIO_PAR_LCDH_LD14_MASK (0xFFFFFFCF) +#define GPIO_PAR_LCDH_LD14_UNMASK (0xFFFFFFCF) #define GPIO_PAR_LCDH_LD14_LD14 (0x00000030) #define GPIO_PAR_LCDH_LD14_LD8 (0x00000020) #define GPIO_PAR_LCDH_LD14_GPIO (0x00000000) -#define GPIO_PAR_LCDH_LD13_MASK (0xFFFFFFF3) +#define GPIO_PAR_LCDH_LD13_UNMASK (0xFFFFFFF3) #define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C) #define GPIO_PAR_LCDH_LD13_CANTX (0x00000008) #define GPIO_PAR_LCDH_LD13_GPIO (0x00000000) -#define GPIO_PAR_LCDH_LD12_MASK (0xFFFFFFFC) +#define GPIO_PAR_LCDH_LD12_UNMASK (0xFFFFFFFC) #define GPIO_PAR_LCDH_LD12_LD12 (0x00000003) #define GPIO_PAR_LCDH_LD12_CANRX (0x00000002) #define GPIO_PAR_LCDH_LD12_GPIO (0x00000000) /* Bit definitions and macros for GPIO_PAR_LCDL */ -#define GPIO_PAR_LCDL_LD11_MASK (0x3FFFFFFF) +#define GPIO_PAR_LCDL_LD11_UNMASK (0x3FFFFFFF) #define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000) #define GPIO_PAR_LCDL_LD11_LD7 (0x80000000) #define GPIO_PAR_LCDL_LD11_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD10_MASK (0xCFFFFFFF) +#define GPIO_PAR_LCDL_LD10_UNMASK (0xCFFFFFFF) #define GPIO_PAR_LCDL_LD10_LD10 (0x30000000) #define GPIO_PAR_LCDL_LD10_LD6 (0x20000000) #define GPIO_PAR_LCDL_LD10_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD9_MASK (0xF3FFFFFF) +#define GPIO_PAR_LCDL_LD9_UNMASK (0xF3FFFFFF) #define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000) #define GPIO_PAR_LCDL_LD9_LD5 (0x08000000) #define GPIO_PAR_LCDL_LD9_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD8_MASK (0xFCFFFFFF) +#define GPIO_PAR_LCDL_LD8_UNMASK (0xFCFFFFFF) #define GPIO_PAR_LCDL_LD8_LD8 (0x03000000) #define GPIO_PAR_LCDL_LD8_LD4 (0x02000000) #define GPIO_PAR_LCDL_LD8_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD7_MASK (0xFF3FFFFF) +#define GPIO_PAR_LCDL_LD7_UNMASK (0xFF3FFFFF) #define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000) #define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000) #define GPIO_PAR_LCDL_LD7_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD6_MASK (0xFFCFFFFF) +#define GPIO_PAR_LCDL_LD6_UNMASK (0xFFCFFFFF) #define GPIO_PAR_LCDL_LD6_LD6 (0x00300000) #define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000) #define GPIO_PAR_LCDL_LD6_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD5_MASK (0xFFF3FFFF) +#define GPIO_PAR_LCDL_LD5_UNMASK (0xFFF3FFFF) #define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000) #define GPIO_PAR_LCDL_LD5_LD3 (0x00080000) #define GPIO_PAR_LCDL_LD5_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD4_MASK (0xFFFCFFFF) +#define GPIO_PAR_LCDL_LD4_UNMASK (0xFFFCFFFF) #define GPIO_PAR_LCDL_LD4_LD4 (0x00030000) #define GPIO_PAR_LCDL_LD4_LD2 (0x00020000) #define GPIO_PAR_LCDL_LD4_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD3_MASK (0xFFFF3FFF) +#define GPIO_PAR_LCDL_LD3_UNMASK (0xFFFF3FFF) #define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000) #define GPIO_PAR_LCDL_LD3_LD1 (0x00008000) #define GPIO_PAR_LCDL_LD3_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD2_MASK (0xFFFFCFFF) +#define GPIO_PAR_LCDL_LD2_UNMASK (0xFFFFCFFF) #define GPIO_PAR_LCDL_LD2_LD2 (0x00003000) #define GPIO_PAR_LCDL_LD2_LD0 (0x00002000) #define GPIO_PAR_LCDL_LD2_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD1_MASK (0xFFFFF3FF) +#define GPIO_PAR_LCDL_LD1_UNMASK (0xFFFFF3FF) #define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00) #define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800) #define GPIO_PAR_LCDL_LD1_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD0_MASK (0xFFFFFCFF) +#define GPIO_PAR_LCDL_LD0_UNMASK (0xFFFFFCFF) #define GPIO_PAR_LCDL_LD0_LD0 (0x00000300) #define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200) #define GPIO_PAR_LCDL_LD0_GPIO (0x00000000) /* Bit definitions and macros for MSCR_FB */ -#define GPIO_MSCR_FB_DUPPER_MASK (0xCF) +#define GPIO_MSCR_FB_DUPPER_UNMASK (0xCF) #define GPIO_MSCR_FB_DUPPER_25V_33V (0x30) #define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20) #define GPIO_MSCR_FB_DUPPER_OD (0x10) #define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00) -#define GPIO_MSCR_FB_DLOWER_MASK (0xF3) +#define GPIO_MSCR_FB_DLOWER_UNMASK (0xF3) #define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C) #define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08) #define GPIO_MSCR_FB_DLOWER_OD (0x04) #define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00) -#define GPIO_MSCR_FB_ADDRCTL_MASK (0xFC) +#define GPIO_MSCR_FB_ADDRCTL_UNMASK (0xFC) #define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03) #define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02) #define GPIO_MSCR_FB_ADDRCTL_OD (0x01) #define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00) /* Bit definitions and macros for MSCR_SDRAM */ -#define GPIO_MSCR_SDRAM_SDCLKB_MASK (0xCF) +#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK (0xCF) #define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30) #define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20) #define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10) #define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00) -#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3) +#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) #define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C) #define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08) #define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04) #define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00) -#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC) +#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) #define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03) #define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02) #define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01) diff --git a/include/asm-m68k/m5235.h b/include/asm-m68k/m5235.h index 22987ac778..71a40d33d2 100644 --- a/include/asm-m68k/m5235.h +++ b/include/asm-m68k/m5235.h @@ -557,8 +557,8 @@ #define CCM_RCON_MODE (0x0001) /* Bit definitions and macros for CCM_CIR */ -#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) -#define CCM_CIR_PRN(x) ((x)&0x003F) +#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) +#define CCM_CIR_PRN(x) ((x) & 0x003F) /********************************************************************* * PLL Clock Module diff --git a/include/asm-m68k/m5301x.h b/include/asm-m68k/m5301x.h index 80cefc40aa..0920a0dc2a 100644 --- a/include/asm-m68k/m5301x.h +++ b/include/asm-m68k/m5301x.h @@ -254,7 +254,7 @@ #define CCM_MISCCR_PLL_LOCK (0x2000) #define CCM_MISCCR_LIMP (0x1000) #define CCM_MISCCR_BME (0x8000) -#define CCM_MISCCR_BMT_MASK (0xF8FF) +#define CCM_MISCCR_BMT_UNMASK (0xF8FF) #define CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8) #define CCM_MISCCR_BMT_512 (0x0700) #define CCM_MISCCR_BMT_1024 (0x0600) @@ -330,32 +330,32 @@ #define GPIO_PAR_CS5 (0x40) #define GPIO_PAR_CS4 (0x10) -#define GPIO_PAR_CS1_MASK (0xF3) +#define GPIO_PAR_CS1_UNMASK (0xF3) #define GPIO_PAR_CS1_CS1 (0x0C) #define GPIO_PAR_CS1_SDCS1 (0x08) -#define GPIO_PAR_CS0_MASK (0xFC) +#define GPIO_PAR_CS0_UNMASK (0xFC) #define GPIO_PAR_CS0_CS0 (0x03) #define GPIO_PAR_CS0_CS4 (0x02) -#define GPIO_PAR_DSPIH_SIN_MASK (0x3F) +#define GPIO_PAR_DSPIH_SIN_UNMASK (0x3F) #define GPIO_PAR_DSPIH_SIN (0xC0) #define GPIO_PAR_DSPIH_SIN_U2RXD (0x80) -#define GPIO_PAR_DSPIH_SOUT_MASK (0xCF) +#define GPIO_PAR_DSPIH_SOUT_UNMASK (0xCF) #define GPIO_PAR_DSPIH_SOUT (0x30) #define GPIO_PAR_DSPIH_SOUT_U2TXD (0x20) -#define GPIO_PAR_DSPIH_SCK_MASK (0xF3) +#define GPIO_PAR_DSPIH_SCK_UNMASK (0xF3) #define GPIO_PAR_DSPIH_SCK (0x0C) #define GPIO_PAR_DSPIH_SCK_U2CTS (0x08) -#define GPIO_PAR_DSPIH_PCS0_MASK (0xFC) +#define GPIO_PAR_DSPIH_PCS0_UNMASK (0xFC) #define GPIO_PAR_DSPIH_PCS0 (0x03) #define GPIO_PAR_DSPIH_PCS0_U2RTS (0x02) -#define GPIO_PAR_DSPIL_PCS1_MASK (0x3F) +#define GPIO_PAR_DSPIL_PCS1_UNMASK (0x3F) #define GPIO_PAR_DSPIL_PCS1 (0xC0) -#define GPIO_PAR_DSPIL_PCS2_MASK (0xCF) +#define GPIO_PAR_DSPIL_PCS2_UNMASK (0xCF) #define GPIO_PAR_DSPIL_PCS2 (0x30) #define GPIO_PAR_DSPIL_PCS2_USBH_OC (0x20) -#define GPIO_PAR_DSPIL_PCS3_MASK (0xF3) +#define GPIO_PAR_DSPIL_PCS3_UNMASK (0xF3) #define GPIO_PAR_DSPIL_PCS3 (0x0C) #define GPIO_PAR_DSPIL_PCS3_USBH_EN (0x08) @@ -365,30 +365,30 @@ #define GPIO_PAR_FEC0_RMII_FEC (0x01) /* GPIO_PAR_FECI2C */ -#define GPIO_PAR_FECI2C_RMII0_MASK (0x3F) +#define GPIO_PAR_FECI2C_RMII0_UNMASK (0x3F) #define GPIO_PAR_FECI2C_MDC0 (0x80) #define GPIO_PAR_FECI2C_MDIO0 (0x40) -#define GPIO_PAR_FECI2C_RMII1_MASK (0xCF) +#define GPIO_PAR_FECI2C_RMII1_UNMASK (0xCF) #define GPIO_PAR_FECI2C_MDC1 (0x20) #define GPIO_PAR_FECI2C_MDIO1 (0x10) -#define GPIO_PAR_FECI2C_SDA_MASK (0xF3) +#define GPIO_PAR_FECI2C_SDA_UNMASK (0xF3) #define GPIO_PAR_FECI2C_SDA(x) (((x) & 0x03) << 2) #define GPIO_PAR_FECI2C_SDA_SDA (0x0C) #define GPIO_PAR_FECI2C_SDA_U2TXD (0x08) #define GPIO_PAR_FECI2C_SDA_MDIO1 (0x04) -#define GPIO_PAR_FECI2C_SCL_MASK (0xFC) +#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFC) #define GPIO_PAR_FECI2C_SCL(x) ((x) & 0x03) #define GPIO_PAR_FECI2C_SCL_SCL (0x03) #define GPIO_PAR_FECI2C_SCL_U2RXD (0x02) #define GPIO_PAR_FECI2C_SCL_MDC1 (0x01) -#define GPIO_PAR_IRQ0H_IRQ07_MASK (0x3F) -#define GPIO_PAR_IRQ0H_IRQ06_MASK (0xCF) +#define GPIO_PAR_IRQ0H_IRQ07_UNMASK (0x3F) +#define GPIO_PAR_IRQ0H_IRQ06_UNMASK (0xCF) #define GPIO_PAR_IRQ0H_IRQ06_USBCLKIN (0x10) -#define GPIO_PAR_IRQ0H_IRQ04_MASK (0xFC) +#define GPIO_PAR_IRQ0H_IRQ04_UNMASK (0xFC) #define GPIO_PAR_IRQ0H_IRQ04_DREQ0 (0x02) -#define GPIO_PAR_IRQ0L_IRQ01_MASK (0xF3) +#define GPIO_PAR_IRQ0L_IRQ01_UNMASK (0xF3) #define GPIO_PAR_IRQ0L_IRQ01_DREQ1 (0x08) #define GPIO_PAR_IRQ1H_IRQ17_DDATA3 (0x40) @@ -401,24 +401,24 @@ #define GPIO_PAR_IRQ1L_IRQ11_PST1 (0x04) #define GPIO_PAR_IRQ1L_IRQ10_PST0 (0x01) -#define GPIO_PAR_SIMP1H_DATA1_MASK (0x3F) +#define GPIO_PAR_SIMP1H_DATA1_UNMASK (0x3F) #define GPIO_PAR_SIMP1H_DATA1_SIMDATA1 (0xC0) #define GPIO_PAR_SIMP1H_DATA1_SSITXD (0x80) #define GPIO_PAR_SIMP1H_DATA1_U1TXD (0x40) -#define GPIO_PAR_SIMP1H_VEN1_MASK (0xCF) +#define GPIO_PAR_SIMP1H_VEN1_UNMASK (0xCF) #define GPIO_PAR_SIMP1H_VEN1_SIMVEN1 (0x30) #define GPIO_PAR_SIMP1H_VEN1_SSIRXD (0x20) #define GPIO_PAR_SIMP1H_VEN1_U1RXD (0x10) -#define GPIO_PAR_SIMP1H_RST1_MASK (0xF3) +#define GPIO_PAR_SIMP1H_RST1_UNMASK (0xF3) #define GPIO_PAR_SIMP1H_RST1_SIMRST1 (0x0C) #define GPIO_PAR_SIMP1H_RST1_SSIFS (0x08) #define GPIO_PAR_SIMP1H_RST1_U1RTS (0x04) -#define GPIO_PAR_SIMP1H_PD1_MASK (0xFC) +#define GPIO_PAR_SIMP1H_PD1_UNMASK (0xFC) #define GPIO_PAR_SIMP1H_PD1_SIMPD1 (0x03) #define GPIO_PAR_SIMP1H_PD1_SSIBCLK (0x02) #define GPIO_PAR_SIMP1H_PD1_U1CTS (0x01) -#define GPIO_PAR_SIMP1L_CLK_MASK (0x3F) +#define GPIO_PAR_SIMP1L_CLK_UNMASK (0x3F) #define GPIO_PAR_SIMP1L_CLK_CLK1 (0xC0) #define GPIO_PAR_SIMP1L_CLK_SSIMCLK (0x80) @@ -432,19 +432,19 @@ #define GPIO_PAR_TIN2(x) (((x) & 0x03) << 4) #define GPIO_PAR_TIN1(x) (((x) & 0x03) << 2) #define GPIO_PAR_TIN0(x) ((x) & 0x03) -#define GPIO_PAR_TIN3_MASK (0x3F) +#define GPIO_PAR_TIN3_UNMASK (0x3F) #define GPIO_PAR_TIN3_TIN3 (0xC0) #define GPIO_PAR_TIN3_TOUT3 (0x80) #define GPIO_PAR_TIN3_IRQ03 (0x40) -#define GPIO_PAR_TIN2_MASK (0xCF) +#define GPIO_PAR_TIN2_UNMASK (0xCF) #define GPIO_PAR_TIN2_TIN2 (0x30) #define GPIO_PAR_TIN2_TOUT2 (0x20) #define GPIO_PAR_TIN2_IRQ02 (0x10) -#define GPIO_PAR_TIN1_MASK (0xF3) +#define GPIO_PAR_TIN1_UNMASK (0xF3) #define GPIO_PAR_TIN1_TIN1 (0x0C) #define GPIO_PAR_TIN1_TOUT1 (0x08) #define GPIO_PAR_TIN1_DACK1 (0x04) -#define GPIO_PAR_TIN0_MASK (0xFC) +#define GPIO_PAR_TIN0_UNMASK (0xFC) #define GPIO_PAR_TIN0_TIN0 (0x03) #define GPIO_PAR_TIN0_TOUT0 (0x02) #define GPIO_PAR_TIN0_CODEC_ALTCLK (0x01) @@ -455,10 +455,10 @@ #define GPIO_PAR_UART_U0RXD (0x10) #define GPIO_PAR_UART_RTS0(x) (((x) & 0x03) << 2) #define GPIO_PAR_UART_CTS0(x) ((x) & 0x03) -#define GPIO_PAR_UART_RTS0_MASK (0xF3) +#define GPIO_PAR_UART_RTS0_UNMASK (0xF3) #define GPIO_PAR_UART_RTS0_U0RTS (0x0C) #define GPIO_PAR_UART_RTS0_USBO_VBOC (0x08) -#define GPIO_PAR_UART_CTS0_MASK (0xFC) +#define GPIO_PAR_UART_CTS0_UNMASK (0xFC) #define GPIO_PAR_UART_CTS0_U0CTS (0x03) #define GPIO_PAR_UART_CTS0_USB0_VBEN (0x02) #define GPIO_PAR_UART_CTS0_USB_PULLUP (0x01) @@ -476,20 +476,20 @@ #define GPIO_PAR_SSIH_TXD(x) (((x) & 0x03) << 4) #define GPIO_PAR_SSIH_FS(x) (((x) & 0x03) << 2) #define GPIO_PAR_SSIH_MCLK(x) ((x) & 0x03) -#define GPIO_PAR_SSIH_RXD_MASK (0x3F) +#define GPIO_PAR_SSIH_RXD_UNMASK (0x3F) #define GPIO_PAR_SSIH_RXD_SSIRXD (0xC0) #define GPIO_PAR_SSIH_RXD_U1RXD (0x40) -#define GPIO_PAR_SSIH_TXD_MASK (0xCF) +#define GPIO_PAR_SSIH_TXD_UNMASK (0xCF) #define GPIO_PAR_SSIH_TXD_SSIRXD (0x30) #define GPIO_PAR_SSIH_TXD_U1TXD (0x10) -#define GPIO_PAR_SSIH_FS_MASK (0xF3) +#define GPIO_PAR_SSIH_FS_UNMASK (0xF3) #define GPIO_PAR_SSIH_FS_SSIFS (0x0C) #define GPIO_PAR_SSIH_FS_U1RTS (0x04) -#define GPIO_PAR_SSIH_MCLK_MASK (0xFC) +#define GPIO_PAR_SSIH_MCLK_UNMASK (0xFC) #define GPIO_PAR_SSIH_MCLK_SSIMCLK (0x03) #define GPIO_PAR_SSIH_MCLK_SSICLKIN (0x01) -#define GPIO_PAR_SSIL_MASK (0x3F) +#define GPIO_PAR_SSIL_UNMASK (0x3F) #define GPIO_PAR_SSIL_BCLK (0xC0) #define GPIO_PAR_SSIL_U1CTS (0x40) @@ -497,40 +497,40 @@ #define GPIO_MSCR_MSCR2(x) (((x) & 0x07) << 5) #define GPIO_MSCR_MSCR3(x) (((x) & 0x07) << 5) #define GPIO_MSCR_MSCR4(x) (((x) & 0x07) << 5) -#define GPIO_MSCR_MSCRn_MASK (0x1F) +#define GPIO_MSCR_MSCRn_UNMASK (0x1F) #define GPIO_MSCR_MSCRn_SDR (0xE0) #define GPIO_MSCR_MSCRn_25VDDR (0x60) #define GPIO_MSCR_MSCRn_18VDDR_FULL (0x20) #define GPIO_MSCR_MSCRn_18VDDR_HALF (0x00) #define GPIO_MSCR_MSCR5(x) (((x) & 0x07) << 2) -#define GPIO_MSCR_MSCR5_MASK (0xE3) +#define GPIO_MSCR_MSCR5_UNMASK (0xE3) #define GPIO_MSCR_MSCR5_SDR (0x1C) #define GPIO_MSCR_MSCR5_25VDDR (0x0C) #define GPIO_MSCR_MSCR5_18VDDR_FULL (0x04) #define GPIO_MSCR_MSCR5_18VDDR_HALF (0x00) -#define GPIO_SRCR_DSPI_MASK (0xFC) +#define GPIO_SRCR_DSPI_UNMASK (0xFC) #define GPIO_SRCR_DSPI(x) ((x) & 0x03) -#define GPIO_SRCR_I2C_MASK (0xFC) +#define GPIO_SRCR_I2C_UNMASK (0xFC) #define GPIO_SRCR_I2C(x) ((x) & 0x03) -#define GPIO_SRCR_IRQ_IRQ0_MASK (0xF3) +#define GPIO_SRCR_IRQ_IRQ0_UNMASK (0xF3) #define GPIO_SRCR_IRQ_IRQ0(x) (((x) & 0x03) << 2) -#define GPIO_SRCR_IRQ_IRQ1DBG_MASK (0xFC) +#define GPIO_SRCR_IRQ_IRQ1DBG_UNMASK (0xFC) #define GPIO_SRCR_IRQ_IRQ1DBG(x) ((x) & 0x03) -#define GPIO_SRCR_SIM_SIMP0_MASK (0xF3) +#define GPIO_SRCR_SIM_SIMP0_UNMASK (0xF3) #define GPIO_SRCR_SIM_SIMP0(x) (((x) & 0x03) << 2) -#define GPIO_SRCR_SIM_SIMP1_MASK (0xFC) +#define GPIO_SRCR_SIM_SIMP1_UNMASK (0xFC) #define GPIO_SRCR_SIM_SIMP1(x) ((x) & 0x03) -#define GPIO_SRCR_TIMER_MASK (0xFC) +#define GPIO_SRCR_TIMER_UNMASK (0xFC) #define GPIO_SRCR_TIMER(x) ((x) & 0x03) -#define GPIO_SRCR_UART2_MASK (0xF3) +#define GPIO_SRCR_UART2_UNMASK (0xF3) #define GPIO_SRCR_UART2(x) (((x) & 0x03) << 2) -#define GPIO_SRCR_UART0_MASK (0xFC) +#define GPIO_SRCR_UART0_UNMASK (0xFC) #define GPIO_SRCR_UART0(x) ((x) & 0x03) -#define GPIO_SRCR_SDHC_MASK (0xFC) +#define GPIO_SRCR_SDHC_UNMASK (0xFC) #define GPIO_SRCR_SDHC(x) ((x) & 0x03) -#define GPIO_SRCR_SSI_MASK (0xFC) +#define GPIO_SRCR_SSI_UNMASK (0xFC) #define GPIO_SRCR_SSI(x) ((x) & 0x03) #define SRCR_HIGHEST (0x03) @@ -538,11 +538,11 @@ #define SRCR_LOW (0x01) #define SRCR_LOWEST (0x00) -#define GPIO_DSCR_FEC_RMIICLK_MASK (0xCF) +#define GPIO_DSCR_FEC_RMIICLK_UNMASK (0xCF) #define GPIO_DSCR_FEC_RMIICLK(x) (((x) & 0x03) << 4) -#define GPIO_DSCR_FEC_RMII0_MASK (0xF3) +#define GPIO_DSCR_FEC_RMII0_UNMASK (0xF3) #define GPIO_DSCR_FEC_RMII0(x) (((x) & 0x03) << 2) -#define GPIO_DSCR_FEC_RMII1_MASK (0xFC) +#define GPIO_DSCR_FEC_RMII1_UNMASK (0xFC) #define GPIO_DSCR_FEC_RMII1(x) ((x) & 0x03) #define DSCR_50PF (0x03) @@ -572,18 +572,18 @@ #define PLL_PCR_LOL_IRQ (0x00004000) #define PLL_PCR_LOL_RE (0x00002000) #define PLL_PCR_LOL_EN (0x00001000) -#define PLL_PCR_REFDIV_MASK (0xFFFFF8FF) +#define PLL_PCR_REFDIV_UNMASK (0xFFFFF8FF) #define PLL_PCR_REFDIV(x) (((x) & 0x07) << 8) -#define PLL_PCR_FBDIV_MASK (0xFFFFFFC0) +#define PLL_PCR_FBDIV_UNMASK (0xFFFFFFC0) #define PLL_PCR_FBDIV(x) ((x) & 0x3F) -#define PLL_PDR_OUTDIV4_MASK (0x0FFF) +#define PLL_PDR_OUTDIV4_UNMASK (0x0FFF) #define PLL_PDR_OUTDIV4(x) (((x) & 0x0000000F) << 12) -#define PLL_PDR_OUTDIV3_MASK (0xF0FF) +#define PLL_PDR_OUTDIV3_UNMASK (0xF0FF) #define PLL_PDR_OUTDIV3(x) (((x) & 0x0000000F) << 8) -#define PLL_PDR_OUTDIV2_MASK (0xFF0F) +#define PLL_PDR_OUTDIV2_UNMASK (0xFF0F) #define PLL_PDR_OUTDIV2(x) (((x) & 0x0000000F) << 4) -#define PLL_PDR_OUTDIV1_MASK (0xFFF0) +#define PLL_PDR_OUTDIV1_UNMASK (0xFFF0) #define PLL_PDR_OUTDIV1(x) ((x) & 0x0000000F) #define PLL_PDR_USB(x) PLL_PDR_OUTDIV4(x) #define PLL_PDR_SDRAM(x) PLL_PDR_OUTDIV3(x) diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h index 596662191c..dfddde62ad 100644 --- a/include/asm-m68k/m5445x.h +++ b/include/asm-m68k/m5445x.h @@ -286,13 +286,13 @@ /* Bit definitions and macros for PAR_FEC */ #define GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) #define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) -#define GPIO_PAR_FEC_FEC1_MASK (0x8F) +#define GPIO_PAR_FEC_FEC1_UNMASK (0x8F) #define GPIO_PAR_FEC_FEC1_MII (0x70) #define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30) #define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20) #define GPIO_PAR_FEC_FEC1_ATA (0x10) #define GPIO_PAR_FEC_FEC1_GPIO (0x00) -#define GPIO_PAR_FEC_FEC0_MASK (0xF8) +#define GPIO_PAR_FEC_FEC0_UNMASK (0xF8) #define GPIO_PAR_FEC_FEC0_MII (0x07) #define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) #define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02) @@ -304,15 +304,15 @@ #define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) #define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) #define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) -#define GPIO_PAR_DMA_DACK1_MASK (0x3F) +#define GPIO_PAR_DMA_DACK1_UNMASK (0x3F) #define GPIO_PAR_DMA_DACK1_DACK1 (0xC0) #define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40) #define GPIO_PAR_DMA_DACK1_GPIO (0x00) -#define GPIO_PAR_DMA_DREQ1_MASK (0xCF) +#define GPIO_PAR_DMA_DREQ1_UNMASK (0xCF) #define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30) #define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10) #define GPIO_PAR_DMA_DREQ1_GPIO (0x00) -#define GPIO_PAR_DMA_DACK0_MASK (0xF3) +#define GPIO_PAR_DMA_DACK0_UNMASK (0xF3) #define GPIO_PAR_DMA_DACK0_DACK1 (0x0C) #define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04) #define GPIO_PAR_DMA_DACK0_GPIO (0x00) @@ -330,7 +330,7 @@ #define GPIO_PAR_FBCTL_TA_GPIO (0x00) #define GPIO_PAR_FBCTL_RW_RW (0x20) #define GPIO_PAR_FBCTL_RW_GPIO (0x00) -#define GPIO_PAR_FBCTL_TS_MASK (0xE7) +#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) #define GPIO_PAR_FBCTL_TS_TS (0x18) #define GPIO_PAR_FBCTL_TS_ALE (0x10) #define GPIO_PAR_FBCTL_TS_TBST (0x08) @@ -364,11 +364,11 @@ #define GPIO_PAR_BE_BS1 (0x04) #define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) #define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) -#define GPIO_PAR_BE_BE3_MASK (0x3F) +#define GPIO_PAR_BE_BE3_UNMASK (0x3F) #define GPIO_PAR_BE_BE3_BE3 (0xC0) #define GPIO_PAR_BE_BE3_TSIZ1 (0x80) #define GPIO_PAR_BE_BE3_GPIO (0x00) -#define GPIO_PAR_BE_BE2_MASK (0xCF) +#define GPIO_PAR_BE_BE2_UNMASK (0xCF) #define GPIO_PAR_BE_BE2_BE2 (0x30) #define GPIO_PAR_BE_BE2_TSIZ0 (0x20) #define GPIO_PAR_BE_BE2_GPIO (0x00) @@ -393,22 +393,22 @@ #define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) #define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) #define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) -#define GPIO_PAR_TIMER_T3IN_MASK (0x3F) +#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) #define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) #define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) #define GPIO_PAR_TIMER_T3IN_U2RXD (0x40) #define GPIO_PAR_TIMER_T3IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T2IN_MASK (0xCF) +#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) #define GPIO_PAR_TIMER_T2IN_T2IN (0x30) #define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) #define GPIO_PAR_TIMER_T2IN_U2TXD (0x10) #define GPIO_PAR_TIMER_T2IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T1IN_MASK (0xF3) +#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) #define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) #define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) #define GPIO_PAR_TIMER_T1IN_U2CTS (0x04) #define GPIO_PAR_TIMER_T1IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T0IN_MASK (0xFC) +#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) #define GPIO_PAR_TIMER_T0IN_T0IN (0x03) #define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) #define GPIO_PAR_TIMER_T0IN_U2RTS (0x01) @@ -417,12 +417,12 @@ /* Bit definitions and macros for PAR_USB */ #define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) #define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) -#define GPIO_PAR_USB_VBUSEN_MASK (0xF3) +#define GPIO_PAR_USB_VBUSEN_UNMASK (0xF3) #define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C) #define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08) #define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04) #define GPIO_PAR_USB_VBUSEN_GPIO (0x00) -#define GPIO_PAR_USB_VBUSOC_MASK (0xFC) +#define GPIO_PAR_USB_VBUSOC_UNMASK (0xFC) #define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03) #define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01) #define GPIO_PAR_USB_VBUSOC_GPIO (0x00) @@ -460,11 +460,11 @@ #define GPIO_PAR_FECI2C_MDC0 (0x0040) #define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) #define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) -#define GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF) +#define GPIO_PAR_FECI2C_MDC1_UNMASK (0xF3FF) #define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00) #define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800) #define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000) -#define GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF) +#define GPIO_PAR_FECI2C_MDIO1_UNMASK (0xFCFF) #define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300) #define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200) #define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000) @@ -472,11 +472,11 @@ #define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000) #define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010) #define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000) -#define GPIO_PAR_FECI2C_SCL_MASK (0xFFF3) +#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFFF3) #define GPIO_PAR_FECI2C_SCL_SCL (0x000C) #define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004) #define GPIO_PAR_FECI2C_SCL_GPIO (0x0000) -#define GPIO_PAR_FECI2C_SDA_MASK (0xFFFC) +#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFFFC) #define GPIO_PAR_FECI2C_SDA_SDA (0x0003) #define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001) #define GPIO_PAR_FECI2C_SDA_GPIO (0x0000) @@ -487,19 +487,19 @@ #define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) #define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) #define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) -#define GPIO_PAR_SSI_BCLK_MASK (0xFCFF) +#define GPIO_PAR_SSI_BCLK_UNMASK (0xFCFF) #define GPIO_PAR_SSI_BCLK_BCLK (0x0300) #define GPIO_PAR_SSI_BCLK_U1CTS (0x0200) #define GPIO_PAR_SSI_BCLK_GPIO (0x0000) -#define GPIO_PAR_SSI_FS_MASK (0xFF3F) +#define GPIO_PAR_SSI_FS_UNMASK (0xFF3F) #define GPIO_PAR_SSI_FS_FS (0x00C0) #define GPIO_PAR_SSI_FS_U1RTS (0x0080) #define GPIO_PAR_SSI_FS_GPIO (0x0000) -#define GPIO_PAR_SSI_SRXD_MASK (0xFFCF) +#define GPIO_PAR_SSI_SRXD_UNMASK (0xFFCF) #define GPIO_PAR_SSI_SRXD_SRXD (0x0030) #define GPIO_PAR_SSI_SRXD_U1RXD (0x0020) #define GPIO_PAR_SSI_SRXD_GPIO (0x0000) -#define GPIO_PAR_SSI_STXD_MASK (0xFFF3) +#define GPIO_PAR_SSI_STXD_UNMASK (0xFFF3) #define GPIO_PAR_SSI_STXD_STXD (0x000C) #define GPIO_PAR_SSI_STXD_U1TXD (0x0008) #define GPIO_PAR_SSI_STXD_GPIO (0x0000) @@ -552,7 +552,7 @@ #define GPIO_PAR_PCI_GNT1 (0x0400) #define GPIO_PAR_PCI_GNT2 (0x1000) #define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) -#define GPIO_PAR_PCI_GNT3_MASK (0x3FFF) +#define GPIO_PAR_PCI_GNT3_UNMASK (0x3FFF) #define GPIO_PAR_PCI_GNT3_GNT3 (0xC000) #define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000) #define GPIO_PAR_PCI_GNT3_GPIO (0x0000) @@ -562,7 +562,7 @@ #define GPIO_PAR_PCI_GNT1_GPIO (0x0000) #define GPIO_PAR_PCI_GNT0_GNT0 (0x0100) #define GPIO_PAR_PCI_GNT0_GPIO (0x0000) -#define GPIO_PAR_PCI_REQ3_MASK (0xFF3F) +#define GPIO_PAR_PCI_REQ3_UNMASK (0xFF3F) #define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0) #define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080) #define GPIO_PAR_PCI_REQ3_GPIO (0x0000) @@ -578,22 +578,22 @@ #define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) #define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) #define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) -#define GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F) +#define GPIO_MSCR_SDRAM_SDDATA_UNMASK (0x3F) #define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0) #define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80) #define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40) #define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00) -#define GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF) +#define GPIO_MSCR_SDRAM_SDDQS_UNMASK (0xCF) #define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30) #define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20) #define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10) #define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00) -#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3) +#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) #define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C) #define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08) #define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04) #define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00) -#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC) +#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) #define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03) #define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02) #define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01) -- cgit v1.2.1 From 52affe04fa5493597d8a5f6202507190950a32e6 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Tue, 9 Mar 2010 19:17:52 -0600 Subject: ColdFire: Update processors' serial port configuration Provide parameter passing to uart_port_config(). Update port configuration - un-mask it before enable the bits. Signed-off-by: TsiChung Liew --- include/asm-m68k/immap_5253.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h index b5a4cb54a7..28cd107a82 100644 --- a/include/asm-m68k/immap_5253.h +++ b/include/asm-m68k/immap_5253.h @@ -37,6 +37,7 @@ #define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x00010000) #define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x00011000) +#define MMAP_PAR (CONFIG_SYS_MBAR2 + 0x0000019C) #define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440) #define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00) -- cgit v1.2.1 From ac265f7fcab1a09b9a837a34ef8b10acc101695e Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Wed, 10 Mar 2010 11:56:36 -0600 Subject: ColdFire: Update M5253DEMO configuration file Fix incorrect default environment for flash erase or protect range. Change offset from 0 to 0xff80nnnn. Remove default ethernet setup and MAC address. Signed-off-by: TsiChung Liew --- include/configs/M5253DEMO.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 5e86e4cb90..f813f8891b 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -95,11 +95,6 @@ # define DM9000_DATA (CONFIG_DM9000_BASE + 4) # undef CONFIG_DM9000_DEBUG -# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 -# define CONFIG_IPADDR 10.82.121.249 -# define CONFIG_NETMASK 255.255.252.0 -# define CONFIG_SERVERIP 10.82.120.80 -# define CONFIG_GATEWAYIP 10.82.123.254 # define CONFIG_OVERWRITE_ETHADDR_ONCE # define CONFIG_EXTRA_ENV_SETTINGS \ @@ -109,8 +104,8 @@ "u-boot=u-boot.bin\0" \ "load=tftp ${loadaddr) ${u-boot}\0" \ "upd=run load; run prog\0" \ - "prog=prot off 0 2ffff;" \ - "era 0 2ffff;" \ + "prog=prot off 0xff800000 0xff82ffff;" \ + "era 0xff800000 0xff82ffff;" \ "cp.b ${loadaddr} 0 ${filesize};" \ "save\0" \ "" -- cgit v1.2.1 From 0e8a75550695aba9d8cfe9c7f7713da42c1f3e89 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Wed, 10 Mar 2010 16:33:03 -0600 Subject: ColdFire: Update Extra environment Data for M5275EVB Provide extra environment Data. Remove default network address and MAC address. Signed-off-by: TsiChung Liew --- include/configs/M5275EVB.h | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index b380159812..f8d43f0a5b 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -121,11 +121,6 @@ #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) -#ifdef CONFIG_MCFFEC -#define CONFIG_ETHADDR 00:06:3b:01:41:55 -#define CONFIG_ETH1ADDR 00:0e:0c:bc:e5:60 -#endif - #define CONFIG_SYS_PROMPT "-> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -145,6 +140,23 @@ #define CONFIG_SYS_MEMTEST_START 0x400 #define CONFIG_SYS_MEMTEST_END 0x380000 +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_RETRY_COUNT 5 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${uboot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" + #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 150000000 -- cgit v1.2.1 From 9e8e927023582231b034e199568e49f84ac032a9 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Wed, 10 Mar 2010 18:24:07 -0600 Subject: ColdFire: Misc update for M53017 Reside Ethernet buffer descriptors in SRAM instead of DRAM. Add CONFIG_SYS_TX_ETH_BUFFER in platform configuration file. Update DRAM control and SRAM control register setting. Update cache setting where size does not write to proper region. Signed-off-by: TsiChung Liew Signed-off-by: Jason Jin --- include/configs/M53017EVB.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 30855bdaa2..c351d415cf 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -69,6 +69,8 @@ # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_TX_ETH_BUFFER 8 +# define CONFIG_SYS_FEC_BUF_USE_SRAM # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_HAS_ETH1 @@ -166,7 +168,7 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_END 0x20000 /* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET @@ -180,7 +182,7 @@ #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ #define CONFIG_SYS_SDRAM_CFG1 0x43711630 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 +#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 -- cgit v1.2.1 From f628e2f72daee810aa568619b6629da68ad042d6 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Wed, 10 Mar 2010 18:50:22 -0600 Subject: ColdFire: Fix SDRAM size on M5208evb rev E The proper SDRAM size is 32MB not 64MB Signed-off-by: Jingchang Lu --- include/configs/M5208EVBE.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 32123d2f54..3cc259ffd1 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -158,7 +158,7 @@ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ #define CONFIG_SYS_SDRAM_CFG1 0x43711630 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000 -- cgit v1.2.1 From dd9f054ede433de73b137987fb3dc066e8d24ebb Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Thu, 11 Mar 2010 22:12:53 -0600 Subject: ColdFire: Cache update for all platforms The CF will call cache functions in lib_m68/cache.c and the cache settings are defined in platform configuration file. Signed-off-by: TsiChung Liew --- include/asm-m68k/cache.h | 210 +++++++++++++++++++++++++++++++++++++++ include/configs/EB+MCF-EV123.h | 12 +++ include/configs/M5208EVBE.h | 13 +++ include/configs/M52277EVB.h | 13 +++ include/configs/M5235EVB.h | 12 +++ include/configs/M5249EVB.h | 15 +++ include/configs/M5253DEMO.h | 15 +++ include/configs/M5253EVBE.h | 15 +++ include/configs/M5271EVB.h | 14 +++ include/configs/M5272C3.h | 14 +++ include/configs/M5275EVB.h | 14 +++ include/configs/M5282EVB.h | 13 +++ include/configs/M53017EVB.h | 11 ++ include/configs/M5329EVB.h | 11 ++ include/configs/M5373EVB.h | 11 ++ include/configs/M54451EVB.h | 15 +++ include/configs/M54455EVB.h | 17 +++- include/configs/M5475EVB.h | 16 +++ include/configs/M5485EVB.h | 16 +++ include/configs/TASREG.h | 11 ++ include/configs/astro_mcf5373l.h | 11 ++ include/configs/cobra5272.h | 13 +++ include/configs/idmr.h | 13 +++ 23 files changed, 504 insertions(+), 1 deletion(-) create mode 100644 include/asm-m68k/cache.h (limited to 'include') diff --git a/include/asm-m68k/cache.h b/include/asm-m68k/cache.h new file mode 100644 index 0000000000..7c84e48471 --- /dev/null +++ b/include/asm-m68k/cache.h @@ -0,0 +1,210 @@ +/* + * ColdFire cache + * + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CACHE_H +#define __CACHE_H + +#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \ + defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x) +#define CONFIG_CF_V2 +#endif + +#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x) +#define CONFIG_CF_V3 +#endif + +#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x) +#define CONFIG_CF_V4 +#if defined(CONFIG_MCF5441x) +#define CONFIG_CF_V4E /* Four Extra ACRn */ +#endif +#endif + +/* ***** CACR ***** */ +/* V2 Core */ +#ifdef CONFIG_CF_V2 + +#define CF_CACR_CENB (1 << 31) +#define CF_CACR_CPD (1 << 28) +#define CF_CACR_CFRZ (1 << 27) +#define CF_CACR_CEIB (1 << 10) +#define CF_CACR_DCM (1 << 9) +#define CF_CACR_DBWE (1 << 8) + +#if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253) +#define CF_CACR_DWP (1 << 6) +#else +#define CF_CACR_CINV (1 << 24) +#define CF_CACR_DISI (1 << 23) +#define CF_CACR_DISD (1 << 22) +#define CF_CACR_INVI (1 << 21) +#define CF_CACR_INVD (1 << 20) +#define CF_CACR_DWP (1 << 5) +#define CF_CACR_EUSP (1 << 4) +#endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */ + +#endif /* CONFIG_CF_V2 */ + +/* V3 Core */ +#ifdef CONFIG_CF_V3 + +#define CF_CACR_EC (1 << 31) +#define CF_CACR_ESB (1 << 29) +#define CF_CACR_DPI (1 << 28) +#define CF_CACR_HLCK (1 << 27) +#define CF_CACR_CINVA (1 << 24) +#define CF_CACR_DNFB (1 << 10) +#define CF_CACR_DCM_UNMASK 0xFFFFFCFF +#define CF_CACR_DCM_WT (0 << 8) +#define CF_CACR_DCM_CB (1 << 8) +#define CF_CACR_DCM_P (2 << 8) +#define CF_CACR_DCM_IP (3 << 8) +#define CF_CACR_DW (1 << 5) +#define CF_CACR_EUSP (1 << 4) + +#endif /* CONFIG_CF_V3 */ + +/* V4 Core */ +#ifdef CONFIG_CF_V4 + +#define CF_CACR_DEC (1 << 31) +#define CF_CACR_DW (1 << 30) +#define CF_CACR_DESB (1 << 29) +#define CF_CACR_DDPI (1 << 28) +#define CF_CACR_DHLCK (1 << 27) +#define CF_CACR_DDCM_UNMASK (0xF9FFFFFF) +#define CF_CACR_DDCM_WT (0 << 25) +#define CF_CACR_DDCM_CB (1 << 25) +#define CF_CACR_DDCM_P (2 << 25) +#define CF_CACR_DDCM_IP (3 << 25) +#define CF_CACR_DCINVA (1 << 24) + +#define CF_CACR_DDSP (1 << 23) +#define CF_CACR_BEC (1 << 19) +#define CF_CACR_BCINVA (1 << 18) +#define CF_CACR_IEC (1 << 15) +#define CF_CACR_DNFB (1 << 13) +#define CF_CACR_IDPI (1 << 12) +#define CF_CACR_IHLCK (1 << 11) +#define CF_CACR_IDCM (1 << 10) +#define CF_CACR_ICINVA (1 << 8) +#define CF_CACR_IDSP (1 << 7) +#define CF_CACR_EUSP (1 << 5) + +#ifdef CONFIG_MCF5445x +#define CF_CACR_IVO (1 << 20) +#define CF_CACR_SPA (1 << 14) +#else +#define CF_CACR_DF (1 << 4) +#endif + +#endif /* CONFIG_CF_V4 */ + +/* ***** ACR ***** */ +#define CF_ACR_ADR_UNMASK (0x00FFFFFF) +#define CF_ACR_ADR(x) ((x & 0xFF) << 24) +#define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF) +#define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16) +#define CF_ACR_EN (1 << 15) +#define CF_ACR_SM_UNMASK (0xFFFF9FFF) +#define CF_ACR_SM_UM (0 << 13) +#define CF_ACR_SM_SM (1 << 13) +#define CF_ACR_SM_ALL (3 << 13) +#define CF_ACR_WP (1 << 2) + +/* V2 Core */ +#ifdef CONFIG_CF_V2 +#define CF_ACR_CM (1 << 6) +#define CF_ACR_BWE (1 << 5) +#else +/* V3 & V4 */ +#define CF_ACR_CM_UNMASK (0xFFFFFF9F) +#define CF_ACR_CM_WT (0 << 5) +#define CF_ACR_CM_CB (1 << 5) +#define CF_ACR_CM_P (2 << 5) +#define CF_ACR_CM_IP (3 << 5) +#endif /* CONFIG_CF_V2 */ + +/* V4 Core */ +#ifdef CONFIG_CF_V4 +#define CF_ACR_AMM (1 << 10) +#define CF_ACR_SP (1 << 3) +#endif /* CONFIG_CF_V4 */ + + +#ifndef CONFIG_SYS_CACHE_ICACR +#define CONFIG_SYS_CACHE_ICACR 0 +#endif + +#ifndef CONFIG_SYS_CACHE_DCACR +#ifdef CONFIG_SYS_CACHE_ICACR +#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR +#else +#define CONFIG_SYS_CACHE_DCACR 0 +#endif +#endif + +#ifndef CONFIG_SYS_CACHE_ACR0 +#define CONFIG_SYS_CACHE_ACR0 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR1 +#define CONFIG_SYS_CACHE_ACR1 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR2 +#define CONFIG_SYS_CACHE_ACR2 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR3 +#define CONFIG_SYS_CACHE_ACR3 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR4 +#define CONFIG_SYS_CACHE_ACR4 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR5 +#define CONFIG_SYS_CACHE_ACR5 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR6 +#define CONFIG_SYS_CACHE_ACR6 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR7 +#define CONFIG_SYS_CACHE_ACR7 0 +#endif + +#define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16) + +#ifndef __ASSEMBLY__ /* put C only stuff in this section */ + +void icache_invalid(void); +void dcache_invalid(void); + +#endif + +#endif /* __CACHE_H */ diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index a0b27a89c4..880cb4ee6b 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -208,6 +208,18 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DBWE | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 3cc259ffd1..e6632acbe7 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -207,6 +207,19 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /* Chipselect bank definitions */ /* * CS0 - NOR Flash diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index 1801d9d7d5..6c6b5d6d57 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -302,6 +302,19 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 2b816ceae2..5c0dc842aa 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -237,6 +237,18 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index e3830e5369..33ac2859df 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -60,6 +60,7 @@ * Command line configuration. */ #include +#define CONFIG_CMD_CACHE #undef CONFIG_CMD_NET #define CONFIG_SYS_PROMPT "=> " @@ -165,6 +166,20 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(2) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index f813f8891b..9944e12fe4 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -57,6 +57,7 @@ */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_LOADB #define CONFIG_CMD_LOADS #define CONFIG_CMD_EXT2 @@ -226,6 +227,20 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(8) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /* Port configuration */ #define CONFIG_SYS_FECI2C 0xF0 diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index df6970cdfa..206d1152ee 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -64,6 +64,7 @@ * Command line configuration. */ #include +#define CONFIG_CMD_CACHE #undef CONFIG_CMD_NET #define CONFIG_CMD_LOADB #define CONFIG_CMD_LOADS @@ -179,6 +180,20 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(2) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /* Port configuration */ #define CONFIG_SYS_FECI2C 0xF0 diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index 50b3ab2808..798949cc56 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -72,6 +72,7 @@ */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_PING #define CONFIG_CMD_NET #define CONFIG_CMD_MII @@ -229,6 +230,19 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /* Chip Select 0 : Boot Flash */ #define CONFIG_SYS_CS0_BASE 0xFFE00000 #define CONFIG_SYS_CS0_MASK 0x001F0001 diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index f824158a69..f704bb3ff7 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -74,6 +74,7 @@ */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_MII #define CONFIG_CMD_NET #define CONFIG_CMD_PING @@ -211,6 +212,19 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index f8d43f0a5b..981670ac06 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -72,6 +72,7 @@ /* Available command configuration */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_PING #define CONFIG_CMD_MII #define CONFIG_CMD_NET @@ -220,6 +221,19 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 15590cfcd5..6e0aa14d3a 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -64,6 +64,7 @@ * Command line configuration. */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_NET #define CONFIG_CMD_PING #define CONFIG_CMD_MII @@ -209,6 +210,18 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DBWE | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index c351d415cf..d983a8fedb 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -233,6 +233,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 8180c05e67..159b178f40 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -237,6 +237,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 8652a80aa1..af1988ce0a 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -237,6 +237,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index a5acfd2846..a80d33047f 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -309,6 +309,21 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 7737284aab..5b4bba8c26 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -279,7 +279,7 @@ * Definitions for initial stack pointer and data area (in DPRAM) */ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x221 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32) @@ -408,6 +408,21 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index 4534002e47..d0077667f3 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -286,6 +286,22 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ + CF_CACR_IDCM) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ + CF_CACR_IEC | CF_CACR_ICINVA) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index 971cb67bad..f23b8b0efa 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -272,6 +272,22 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ + CF_CACR_IDCM) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ + CF_CACR_IEC | CF_CACR_ICINVA) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h index 25f3a26f35..b69f015c7c 100644 --- a/include/configs/TASREG.h +++ b/include/configs/TASREG.h @@ -252,6 +252,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 1fe42f682a..7c8281cae7 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -386,4 +386,15 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + #endif /* _CONFIG_ASTRO_MCF5373L_H */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 1c3ea23c77..330e3ac667 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -331,6 +331,19 @@ from which user programs will be started */ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions * diff --git a/include/configs/idmr.h b/include/configs/idmr.h index 841affb7cc..61e3bad4f3 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -224,6 +224,19 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /* Port configuration */ #define CONFIG_SYS_FECI2C 0xF0 -- cgit v1.2.1 From f26a247308568e32857a5cc054f7219510a7d44e Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Mon, 15 Mar 2010 19:39:21 -0500 Subject: ColdFire: Fix incorrect M5253DEMO default environment The flash location is at 0xff800000, not 0 Signed-off-by: TsiChung Liew --- include/configs/M5253DEMO.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 9944e12fe4..b5af493b80 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -107,7 +107,7 @@ "upd=run load; run prog\0" \ "prog=prot off 0xff800000 0xff82ffff;" \ "era 0xff800000 0xff82ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ + "cp.b ${loadaddr} 0xff800000 ${filesize};" \ "save\0" \ "" #endif -- cgit v1.2.1 From fd03ea89641d6f6ade6d1a8580c1bb9f52b8542c Mon Sep 17 00:00:00 2001 From: Frans Meulenbroeks Date: Fri, 26 Mar 2010 09:46:42 +0100 Subject: i2c: made unused function i2c_mux_add_device static and removed it from the .h file Signed-off-by: Frans Meulenbroeks --- include/i2c.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/i2c.h b/include/i2c.h index 31088b675a..d828964256 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -127,8 +127,6 @@ typedef struct _mux_device { struct _mux_device *next; } I2C_MUX_DEVICE; -int i2c_mux_add_device(I2C_MUX_DEVICE *dev); - I2C_MUX_DEVICE *i2c_mux_search_device(int id); I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf); int i2x_mux_select_mux(int bus); -- cgit v1.2.1