From 250e039da8c7e485dabdc84f0457b2a901757e28 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 27 Jan 2015 22:13:27 -0700 Subject: pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/pci.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/include/pci.h b/include/pci.h index 4fbb8f6729..004a048d2f 100644 --- a/include/pci.h +++ b/include/pci.h @@ -644,8 +644,7 @@ extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); -extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code, - int wanted_prog_if, int index); +pci_dev_t pci_find_class(unsigned int find_class, int index); extern int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev, -- cgit v1.2.1 From 34236238359253ef5342843a3cca09dcca939262 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 27 Jan 2015 22:13:28 -0700 Subject: x86: pci: Add PCI IDs for Minnowboard Max This board includes a few IDs we have not seen before. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/pci_ids.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/pci_ids.h b/include/pci_ids.h index 26f4748685..1012abecef 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1346,6 +1346,7 @@ #define PCI_VENDOR_ID_REALTEK 0x10ec #define PCI_DEVICE_ID_REALTEK_8139 0x8139 +#define PCI_DEVICE_ID_REALTEK_8168 0x8168 #define PCI_VENDOR_ID_XILINX 0x10ee #define PCI_DEVICE_ID_RME_DIGI96 0x3fc0 @@ -2594,6 +2595,10 @@ #define PCI_DEVICE_ID_INTEL_I960 0x0960 #define PCI_DEVICE_ID_INTEL_I960RM 0x0962 #define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60 +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO 0x0f15 +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD 0x0f16 +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC 0x0f1c +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA 0x0f23 #define PCI_DEVICE_ID_INTEL_82541ER 0x1078 #define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c #define PCI_DEVICE_ID_INTEL_82542 0x1000 -- cgit v1.2.1 From bc17d8f4ac41a6a4bcc4b28f1c6216a5a034fa63 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 27 Jan 2015 22:13:34 -0700 Subject: x86: video: Allow video ROM execution to fall back to the other method If the BIOS emulator is not available, allow use of native execution if available, and vice versa. This can be controlled by the caller. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/pci_rom.h | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/pci_rom.h b/include/pci_rom.h index 4ba36eb1b7..2f1665d17a 100644 --- a/include/pci_rom.h +++ b/include/pci_rom.h @@ -33,14 +33,25 @@ struct pci_rom_data { uint16_t reserved_2; }; +/* + * Determines which execution method is used and whether we allow falling back + * to the other if the requested method is not available. + */ +enum pci_rom_emul { + PCI_ROM_EMULATE = 0 << 0, + PCI_ROM_USE_NATIVE = 1 << 0, + PCI_ROM_ALLOW_FALLBACK = 1 << 1, +}; + /** * pci_run_vga_bios() - Run the VGA BIOS in an x86 PC * * @dev: Video device containing the BIOS * @int15_handler: Function to call to handle int 0x15 - * @emulate: true to use the x86 emulator, false to run native + * @exec_method: flags from enum pci_rom_emul */ -int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate); +int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), + int exec_method); /** * board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects -- cgit v1.2.1 From 91785f70b9b7ebfd1a2da4772a8268b36f58fa3d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 27 Jan 2015 22:13:39 -0700 Subject: x86: mmc: Move common FSP functions into a common file Since these board functions seem to be the same for all boards which use FSP, move them into a common file. We can adjust this later if future FSPs need more flexibility. This creates a generic PCI MMC device. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- include/mmc.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include') diff --git a/include/mmc.h b/include/mmc.h index 09101e2c87..56d97bbdcf 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -438,6 +438,20 @@ int board_mmc_init(bd_t *bis); int cpu_mmc_init(bd_t *bis); int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); +struct pci_device_id; + +/** + * pci_mmc_init() - set up PCI MMC devices + * + * This finds all the matching PCI IDs and sets them up as MMC devices. + * + * @name: Name to use for devices + * @mmc_supported: PCI IDs to search for + * @num_ids: Number of elements in @mmc_supported + */ +int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported, + int num_ids); + /* Set block count limit because of 16 bit register limit on some hardware*/ #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 -- cgit v1.2.1 From abbdb262570f415b5eaea036486076669eff1e76 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 27 Jan 2015 22:13:44 -0700 Subject: scsi: bootstage: Measure time taken to scan the bus On some hardware this time can be significant. Add bootstage support for measuring this. The result can be obtained using 'bootstage report' or passed on to the Linux via the device tree. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/bootstage.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/bootstage.h b/include/bootstage.h index df13ab2f63..6b7588d38f 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -194,6 +194,7 @@ enum bootstage_id { BOOTSTAGE_ID_MAIN_CPU_READY, BOOTSTAGE_ID_ACCUM_LCD, + BOOTSTAGE_ID_ACCUM_SCSI, /* a few spare for the user, from here */ BOOTSTAGE_ID_USER, -- cgit v1.2.1 From 8b4d659f4b3ce0e27253fa14066d380ea02b6695 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 27 Jan 2015 22:13:45 -0700 Subject: x86: Enable bootstage features Allow measuring of boot time using bootstage. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- include/configs/x86-common.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index ecedfc3ab1..66d4894256 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -245,6 +245,9 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTSTAGE +#define CONFIG_CMD_BOOTSTAGE + #define CONFIG_CMD_USB #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v1.2.1 From 3a1a18ff1867d6f94921a24992354d3a547666d6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 27 Jan 2015 22:13:47 -0700 Subject: x86: Add support for Intel Minnowboard Max This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/configs/minnowmax.h | 72 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 include/configs/minnowmax.h (limited to 'include') diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h new file mode 100644 index 0000000000..823e051eb1 --- /dev/null +++ b/include/configs/minnowmax.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_X86_SERIAL +#define CONFIG_SMSC_LPC47M + +#define CONFIG_PCI_MEM_BUS 0xd0000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_PREF_BUS 0xc0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x2000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xe000 + +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP +#define CONFIG_RTL8169 +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ + "stdout=vga,serial\0" \ + "stderr=vga,serial\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA} +#define CONFIG_SPI_FLASH_SST + +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA +#define CONFIG_CMD_MMC + +#undef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_X86_OPTION_ROM_FILE vga.bin +#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 + +#ifndef CONFIG_SYS_COREBOOT +#define CONFIG_VIDEO_VESA +#endif +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO +#define CONFIG_VGA_AS_SINGLE_DEVICE + +#define CONFIG_FIT_SIGNATURE +#define CONFIG_RSA + +/* Avoid a warning in the Realtek Ethernet driver */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From 7df546a653462c91bc88bf9bf465ff2e39fde59e Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sat, 24 Jan 2015 17:17:08 +0800 Subject: x86: Remove CONFIG_SATA_INTEL from x86-common.h CONFIG_SATA_INTEL is not referenced anywhere, so remove it. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/configs/x86-common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 66d4894256..062e6c2219 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -39,7 +39,6 @@ /* SATA AHCI storage */ #define CONFIG_SCSI_AHCI -#define CONFIG_SATA_INTEL #ifdef CONFIG_SCSI_AHCI #define CONFIG_LIBATA #define CONFIG_SYS_64BIT_LBA -- cgit v1.2.1 From afee3fb8c807e1ac9713ecb31d895008e3b5251a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 2 Feb 2015 22:35:28 +0800 Subject: x86: Add basic Intel Galileo board support New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng Reviewed-by: Simon Glass Acked-by: Simon Glass --- include/configs/galileo.h | 53 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 include/configs/galileo.h (limited to 'include') diff --git a/include/configs/galileo.h b/include/configs/galileo.h new file mode 100644 index 0000000000..bead2fc64e --- /dev/null +++ b/include/configs/galileo.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_X86_SERIAL + +/* ns16550 UART is memory-mapped in Quark SoC */ +#undef CONFIG_SYS_NS16550_PORT_MAPPED + +#define CONFIG_PCI_MEM_BUS 0x90000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x20000000 + +#define CONFIG_PCI_PREF_BUS 0xb0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x20000000 + +#define CONFIG_PCI_IO_BUS 0x2000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xe000 + +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +/* SATA is not supported in Quark SoC */ +#undef CONFIG_SCSI_AHCI +#undef CONFIG_CMD_SCSI + +/* Video is not supported in Quark SoC */ +#undef CONFIG_VIDEO +#undef CONFIG_CFB_CONSOLE + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From c89ada017fe24891818c08a9e4b7c5ae4a9224e5 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 5 Feb 2015 23:42:26 +0800 Subject: fdtdec: Add compatible id and string for Intel Quark MRC Add COMPAT_INTEL_QRK_MRC and "intel,quark-mrc" so that fdtdec can decode Intel Quark MRC node. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/fdtdec.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index 231eed7892..1bc70dba21 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -167,6 +167,7 @@ enum fdt_compat_id { COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */ COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ + COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ COMPAT_COUNT, }; -- cgit v1.2.1 From b1420c813074d39cd2452d7bc45374561d1cf223 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 5 Feb 2015 23:42:27 +0800 Subject: dt-bindings: Add Intel Quark MRC bindings Add standard dt-bindings macros to be used by Intel Quark MRC node. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/dt-bindings/mrc/quark.h | 83 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 include/dt-bindings/mrc/quark.h (limited to 'include') diff --git a/include/dt-bindings/mrc/quark.h b/include/dt-bindings/mrc/quark.h new file mode 100644 index 0000000000..e3ca8a25a3 --- /dev/null +++ b/include/dt-bindings/mrc/quark.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Intel Quark MRC bindings include several properties + * as part of an Intel Quark MRC node. In most cases, + * the value of these properties uses the standard values + * defined in this header. + */ + +#ifndef _DT_BINDINGS_QRK_MRC_H_ +#define _DT_BINDINGS_QRK_MRC_H_ + +/* MRC platform data flags */ +#define MRC_FLAG_ECC_EN 0x00000001 +#define MRC_FLAG_SCRAMBLE_EN 0x00000002 +#define MRC_FLAG_MEMTEST_EN 0x00000004 +/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */ +#define MRC_FLAG_TOP_TREE_EN 0x00000008 +/* If set ODR signal is asserted to DRAM devices on writes */ +#define MRC_FLAG_WR_ODT_EN 0x00000010 + +/* DRAM width */ +#define DRAM_WIDTH_X8 0 +#define DRAM_WIDTH_X16 1 +#define DRAM_WIDTH_X32 2 + +/* DRAM speed */ +#define DRAM_FREQ_800 0 +#define DRAM_FREQ_1066 1 + +/* DRAM type */ +#define DRAM_TYPE_DDR3 0 +#define DRAM_TYPE_DDR3L 1 + +/* DRAM rank mask */ +#define DRAM_RANK(n) (1 << (n)) + +/* DRAM channel mask */ +#define DRAM_CHANNEL(n) (1 << (n)) + +/* DRAM channel width */ +#define DRAM_CHANNEL_WIDTH_X8 0 +#define DRAM_CHANNEL_WIDTH_X16 1 +#define DRAM_CHANNEL_WIDTH_X32 2 + +/* DRAM address mode */ +#define DRAM_ADDR_MODE0 0 +#define DRAM_ADDR_MODE1 1 +#define DRAM_ADDR_MODE2 2 + +/* DRAM refresh rate */ +#define DRAM_REFRESH_RATE_195US 1 +#define DRAM_REFRESH_RATE_39US 2 +#define DRAM_REFRESH_RATE_785US 3 + +/* DRAM SR temprature range */ +#define DRAM_SRT_RANGE_NORMAL 0 +#define DRAM_SRT_RANGE_EXTENDED 1 + +/* DRAM ron value */ +#define DRAM_RON_34OHM 0 +#define DRAM_RON_40OHM 1 + +/* DRAM rtt nom value */ +#define DRAM_RTT_NOM_40OHM 0 +#define DRAM_RTT_NOM_60OHM 1 +#define DRAM_RTT_NOM_120OHM 2 + +/* DRAM rd odt value */ +#define DRAM_RD_ODT_OFF 0 +#define DRAM_RD_ODT_60OHM 1 +#define DRAM_RD_ODT_120OHM 2 +#define DRAM_RD_ODT_180OHM 3 + +/* DRAM density */ +#define DRAM_DENSITY_512M 0 +#define DRAM_DENSITY_1G 1 +#define DRAM_DENSITY_2G 2 +#define DRAM_DENSITY_4G 3 + +#endif /* _DT_BINDINGS_QRK_MRC_H_ */ -- cgit v1.2.1 From 38fc1cdae0fb7a429222b7b85f8cdaefbd078e21 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 4 Feb 2015 16:26:11 +0800 Subject: x86: pci: Add pci ids for Quark SoC Add pci ids for Intel Quark SoC. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/pci_ids.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/pci_ids.h b/include/pci_ids.h index 1012abecef..dc2ca218a6 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2592,6 +2592,10 @@ #define PCI_DEVICE_ID_INTEL_MFD_EMMC0 0x0823 #define PCI_DEVICE_ID_INTEL_MFD_EMMC1 0x0824 #define PCI_DEVICE_ID_INTEL_MRST_SD2 0x084F +#define PCI_DEVICE_ID_INTEL_QRK_SDIO 0x08A7 +#define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936 +#define PCI_DEVICE_ID_INTEL_QRK_EMAC 0x0937 +#define PCI_DEVICE_ID_INTEL_QRK_ILB 0x095E #define PCI_DEVICE_ID_INTEL_I960 0x0960 #define PCI_DEVICE_ID_INTEL_I960RM 0x0962 #define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60 -- cgit v1.2.1 From 6df7ffea1399de57e5b3be6e3cd0986869087663 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 4 Feb 2015 16:26:13 +0800 Subject: x86: Add SD/MMC support to quark/galileo Intel Galileo board has a microSD slot which is routed from Quark SoC SDIO controller. Enable SD/MMC support so that we can use an SD card. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/configs/galileo.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/configs/galileo.h b/include/configs/galileo.h index bead2fc64e..d745f4eb89 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -50,4 +50,11 @@ #undef CONFIG_VIDEO #undef CONFIG_CFB_CONSOLE +/* SD/MMC support */ +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA +#define CONFIG_CMD_MMC + #endif /* __CONFIG_H */ -- cgit v1.2.1 From 1b15fac15d9720b4a31a54fe07fd181ff0a28a80 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 2 Feb 2015 21:25:08 +0800 Subject: bootstage: Fix typos in the comment There are two typos in the comment block in bootstage.h, fix them. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/bootstage.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/bootstage.h b/include/bootstage.h index 6b7588d38f..0276cb3f60 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -86,9 +86,9 @@ enum bootstage_id { BOOTSTAGE_ID_POST_FAIL_R, /* Post failure reported after reloc */ /* - * This set is reported ony by x86, and the meaning is different. In + * This set is reported only by x86, and the meaning is different. In * this case we are reporting completion of a particular stage. - * This should probably change in he x86 code (which doesn't report + * This should probably change in the x86 code (which doesn't report * errors in any case), but discussion this can perhaps wait until we * have a generic board implementation. */ -- cgit v1.2.1