From 96ac18c9ccc77c7f57dff5651b34a3cc914c8abd Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Wed, 26 Feb 2014 09:38:37 +0530 Subject: powerpc/t104xrdb: Update DDR initialization related settings Update following DDR related settings for T1040RDB, T1042RDB_PI -Correct number of chip selects to two as t1040 supports two Chip selects. -Update board_specific_parameters udimm structure with settings derived via calibration. -Update ddr_raw_timing sructure corresponding to DIMM. -Set ODT to off. Typically on FSL board, ODT is set to 75 ohm, but on T104xRDB, on setting this , DDR instability is observed. Board-level debugging is in progress. Verified the updated settings to be working fine with dual-ranked Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s. Signed-off-by: Priyanka Jain Signed-off-by: York Sun --- include/configs/T1040RDB.h | 2 +- include/configs/T1042RDB_PI.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index fd010c057c..395845bd68 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -147,7 +147,7 @@ /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD #define CONFIG_SYS_DDR_RAW_TIMING diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index 6d07805ffd..68656e6ef1 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -147,7 +147,7 @@ /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD #define CONFIG_SYS_DDR_RAW_TIMING -- cgit v1.2.1