From 5f603761c3de00423cad405e064cd2fc822feab1 Mon Sep 17 00:00:00 2001 From: Praveen Rao Date: Mon, 9 Mar 2015 17:12:06 -0500 Subject: ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870 This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well. Signed-off-by: Praveen Rao Signed-off-by: Angela Stegmaier Signed-off-by: Nishanth Menon Tested-by: Matt Porter Reviewed-by: Tom Rini --- include/configs/ti_omap5_common.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 925cb42dd3..09f05f18a7 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -21,6 +21,9 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_ARCH_CPU_INIT +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_798870 + #define CONFIG_SYS_CACHELINE_SIZE 64 /* Use General purpose timer 1 */ -- cgit v1.2.1