From 44d50f0b54ef14534440bc5d789ec65240dfc0f8 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 13 Sep 2011 17:55:11 +0800 Subject: powerpc/p2041rdb: set sysclk according to status of physical switch SW1 P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8], software need to read the SW1 status to decide what the sysclk needs. SW1[8~6] : frequency 0 0 1 : 83.3MHz 0 1 0 : 100MHz others: 66.667MHz Signed-off-by: Shaohui Xie Signed-off-by: Kumar Gala --- include/configs/P2041RDB.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 37e98bb7e9..c7f076122c 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -102,7 +102,10 @@ #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#define CONFIG_SYS_CLK_FREQ 66666666 +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(unsigned long dummy); +#endif +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* * These can be toggled for performance analysis, otherwise use default. -- cgit v1.2.1