From cf1971c1c0a76c3105a347102db083027a3d7b91 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 25 Oct 2010 18:32:08 +0200 Subject: ppc4xx: t3corp: Add support for the Xilinx DS617 flash chip The t3corp board has an Xilinx DS617 flash chip connected to the onboard FPGA. This patch adds support for these chips. Board specific flash accessor functions are needed, since the chips can only be read correctly in 16bit mode. Additionally the FPGA chip-selects are configured for device-paced transfers (ready is enabled). Signed-off-by: Stefan Roese --- include/configs/t3corp.h | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 6115a5f413..2a731a637b 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -120,11 +120,16 @@ */ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */ +#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + (CONFIG_SYS_FPGA1_BASE + 0x01000000) } +#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff, /* don't set */ \ + 0xbddf } /* set async read mode */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors p. chip*/ #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms*/ @@ -355,6 +360,7 @@ "ramdisk_addr=fc200000\0" \ "pciconfighost=1\0" \ "pcie_mode=RP:RP\0" \ + "unlock=yes\0" \ "" /* @@ -423,7 +429,7 @@ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ - EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_RE_ENABLED | \ EBC_BXAP_SOR_DELAYED | \ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) @@ -440,7 +446,7 @@ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ - EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_RE_ENABLED | \ EBC_BXAP_SOR_DELAYED | \ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) @@ -457,7 +463,7 @@ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ - EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_RE_ENABLED | \ EBC_BXAP_SOR_DELAYED | \ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) -- cgit v1.2.1 From a321148b5b38150b011a1df4ad198329a49e98a3 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 26 Nov 2010 15:45:48 +0100 Subject: ppc4xx: Update lwmon5 board support This patch includes the following changes for the lwmon5 board support: - Enable cache in SDRAM - Use common EHCI driver instead of the PPC4xx specific OHCI driver This can be done since only high-speed devices are connected. - Remove cached TLB entry again after ECC setup - Use correct define for cache enabling (CONFIG_4xx_DCACHE instead of CONFIG_SYS_ENABLE_SDRAM_CACHE) - Enable FIT image support Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 4c9744ca4f..aedf495104 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -43,6 +43,8 @@ #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ +#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */ + #define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ #define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */ @@ -321,6 +323,8 @@ /* Update size in "reg" property of NOR FLASH device tree nodes */ #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE +#define CONFIG_FIT /* enable FIT image support */ + #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ #define CONFIG_PREBOOT "setenv bootdelay 15" @@ -393,16 +397,18 @@ #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_SPLASH_SCREEN -/* USB */ -#ifdef CONFIG_440EPX -#define CONFIG_USB_OHCI +/* + * USB/EHCI + */ +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */ +#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300 +#define CONFIG_EHCI_DCACHE /* with dcache handling support */ +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */ #define CONFIG_USB_STORAGE -/* Comment this out to enable USB 1.1 device */ -#define USB_2_0_DEVICE - -#endif /* CONFIG_440EPX */ - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -- cgit v1.2.1 From d20b9991154241466802ceb17169dc8b5f7e58df Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 7 Dec 2010 14:27:56 +0100 Subject: xilinx-ppc4xx-generic: Use common u-boot.lds Use common ppc4xx linker script for xilinx ppc440 and ppc405 related boards. Signed-off-by: Ricardo Ribalda Delgado Signed-off-by: Stefan Roese --- include/configs/xilinx-ppc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h index 2422c0b0c3..bd7bac0976 100644 --- a/include/configs/xilinx-ppc.h +++ b/include/configs/xilinx-ppc.h @@ -50,6 +50,7 @@ #undef CONFIG_CMD_DHCP #undef CONFIG_CMD_EEPROM #undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_NFS /*Misc*/ #define CONFIG_BOOTDELAY 5/* autoboot after 5 seconds */ -- cgit v1.2.1