From 22ff3d01348e0a2dc369b7efcbac30e4ce86d178 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Fri, 21 Nov 2008 16:31:29 +0800 Subject: fsl-ddr: clean up the ddr code for DDR3 controller - The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by: Dave Liu Acked-by: Andy Fleming --- include/asm-ppc/fsl_ddr_sdram.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index c1ea7cd6bb..0006c21a02 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -34,7 +34,10 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; #elif defined(CONFIG_FSL_DDR3) #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 #endif +#endif /* #if defined(CONFIG_FSL_DDR1) */ /* define bank(chip select) interleaving mode */ #define FSL_DDR_CS0_CS1 0x40 -- cgit v1.2.1