From 42d1f0394bef0624fc9664714d54bb137931d6a6 Mon Sep 17 00:00:00 2001 From: wdenk Date: Wed, 15 Oct 2003 23:53:47 +0000 Subject: * Patches by Xianghua Xiao, 15 Oct 2003: - Added Motorola CPU 8540/8560 support (cpu/85xx) - Added Motorola MPC8540ADS board support (board/mpc8540ads) - Added Motorola MPC8560ADS board support (board/mpc8560ads) * Minor code cleanup --- include/mpc85xx.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 include/mpc85xx.h (limited to 'include/mpc85xx.h') diff --git a/include/mpc85xx.h b/include/mpc85xx.h new file mode 100644 index 0000000000..a4f5c619d1 --- /dev/null +++ b/include/mpc85xx.h @@ -0,0 +1,32 @@ +/* + * Copyright(c) 2003 Motorola Inc. + * Xianghua Xiao (x.xiao@motorola.com) + */ + +#ifndef __MPC85xx_H__ +#define __MPC85xx_H__ + +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ + +#if defined(CONFIG_E500) +#include +#endif + +#if defined(CONFIG_DDR_ECC) +void dma_init(void); +uint dma_check(void); +int dma_xfer(void *dest, uint count, void *src); +#endif +/*----------------------------------------------------------------------- + * SCCR - System Clock Control Register 9-8 + */ +#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ +#define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */ +#define SCCR_DFBRG_SHIFT 0 + +#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ +#define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/ +#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ +#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ + +#endif /* __MPC85xx_H__ */ -- cgit v1.2.1