From 0d79f4f490352f6e1500cdd12a3b0e8b17265bde Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 18 Jul 2013 12:13:40 -0700 Subject: ARM: tegra: Make cache line size SoC specific Currently all Tegra SoCs are assumed to have 32 byte cache lines. This isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and therefore uses a cache line size of 64 bytes. Move the cache line size setting to the per-SoC common configuration file. Signed-off-by: Thierry Reding Tested-by: Stephen Warren Reviewed-by: Stephen Warren Signed-off-by: Tom Warren --- include/configs/tegra114-common.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/configs/tegra114-common.h') diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 44e98e5019..c3de9a999e 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -18,6 +18,9 @@ #define _TEGRA114_COMMON_H_ #include "tegra-common.h" +/* Cortex-A15 uses a cache line size of 64 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* * NS16550 Configuration */ -- cgit v1.2.1