From debb7354d1ea4f694154818df5e5b523f5c1cc1d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 26 Apr 2006 17:58:56 -0500 Subject: Initial support for MPC8641 HPCN board. --- drivers/pci_auto.c | 2 +- drivers/tsec.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++----- drivers/tsec.h | 20 +++++++++++++++- 3 files changed, 83 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 15f74328f0..3c958d3b95 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -186,7 +186,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose, } else { /* We don't support prefetchable memory for now, so disable */ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); - pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000); + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1); } if (pci_io) { diff --git a/drivers/tsec.c b/drivers/tsec.c index 7ec565ca67..18778c270a 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -74,27 +75,33 @@ struct tsec_info_struct { static struct tsec_info_struct tsec_info[] = { #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1) {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX}, +#elif defined(CONFIG_MPC86XX_TSEC1) + {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, #else { 0, 0, 0}, #endif #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2) {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, +#elif defined(CONFIG_MPC86XX_TSEC2) + {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX}, #else { 0, 0, 0}, #endif #ifdef CONFIG_MPC85XX_FEC {FEC_PHY_ADDR, 0, FEC_PHYIDX}, #else -# if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) +#if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3) {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX}, -# else +#else { 0, 0, 0}, -# endif -# if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) +#endif +#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX}, -# else +#elif defined(CONFIG_MPC86XX_TSEC4) + {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, +#else { 0, 0, 0}, -# endif +#endif #endif }; @@ -467,6 +474,32 @@ uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv) return 0; } +/* Parse the vsc8244's status register for speed and duplex + * information */ +uint mii_parse_vsc8244(uint mii_reg, struct tsec_private *priv) +{ + uint speed; + + if(mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) + priv->duplexity = 1; + else + priv->duplexity = 0; + + speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; + switch(speed) { + case MIIM_VSC8244_AUXCONSTAT_GBIT: + priv->speed = 1000; + break; + case MIIM_VSC8244_AUXCONSTAT_100: + priv->speed = 100; + break; + default: + priv->speed = 10; + break; + } + + return 0; +} /* Parse the DM9161's status register for speed and duplex @@ -859,6 +892,29 @@ struct phy_info phy_info_cis8201 = { {miim_end,} }, }; +struct phy_info phy_info_VSC8244 = { + 0x3f1b, + "Vitesse VSC8244", + 6, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; struct phy_info phy_info_dm9161 = { @@ -1001,6 +1057,7 @@ struct phy_info *phy_info[] = { &phy_info_M88E1111S, &phy_info_dm9161, &phy_info_lxt971, + &phy_info_VSC8244, &phy_info_dp83865, NULL }; diff --git a/drivers/tsec.h b/drivers/tsec.h index b55b2992b2..31f18675fb 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -27,7 +27,7 @@ #define TSEC_SIZE 0x01000 /* FIXME: Should these be pushed back to 83xx and 85xx config files? */ -#if defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) #elif defined(CONFIG_MPC83XX) #define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET) @@ -133,6 +133,24 @@ #define MIIM_GBIT_CON 0x09 #define MIIM_GBIT_CON_ADVERT 0x0e00 +/* Entry for Vitesse VSC8244 regs starts here */ +/* Vitesse VSC8244 Auxiliary Control/Status Register */ +#define MIIM_VSC8244_AUX_CONSTAT 0x1c +#define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000 +#define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020 +#define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018 +#define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010 +#define MIIM_VSC8244_AUXCONSTAT_100 0x0008 +#define MIIM_CONTROL_INIT_LOOPBACK 0x4000 + +/* Vitesse VSC8244 Extended PHY Control Register 1 */ +#define MIIM_VSC8244_EPHY_CON 0x17 +#define MIIM_VSC8244_EPHYCON_INIT 0x0006 + +/* Vitesse VSC8244 Serial LED Control Register */ +#define MIIM_VSC8244_LED_CON 0x1b +#define MIIM_VSC8244_LEDCON_INIT 0xF011 + /* 88E1011 PHY Status Register */ #define MIIM_88E1011_PHY_STATUS 0x11 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000 -- cgit v1.2.1 From a2320a6bf8113a09544c42d160d10ac69d049a03 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 27 Apr 2006 08:22:39 -0500 Subject: Revert bad PCI prefetch limit change. --- drivers/pci_auto.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 3c958d3b95..15f74328f0 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -186,7 +186,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose, } else { /* We don't support prefetchable memory for now, so disable */ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); - pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1); + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000); } if (pci_io) { -- cgit v1.2.1 From bd22c2b97514fbfb0e03bd9c72b3445e4dbd57e2 Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong-R64188 Date: Tue, 27 Jun 2006 18:12:02 +0800 Subject: Fix bug for io_bar size during pci scan During the pci scan process, Some devices return bar_reponse with the highest bytes 0, such as the pci bridge in uli1575 return bar_response with 0xffffff, So the bar_size should be manually set under 64K. Signed-off-by: Jason Jin --- drivers/pci_auto.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 15f74328f0..9e921b2148 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -102,7 +102,8 @@ void pciauto_setup_device(struct pci_controller *hose, /* Check the BAR type and set our address mask */ if (bar_response & PCI_BASE_ADDRESS_SPACE) { - bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; + bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) + & 0xffff) + 1; bar_res = io; DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size); -- cgit v1.2.1 From fcfb9a57947fc203b99fe81ab0578f7286261f9f Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong-R64188 Date: Tue, 27 Jun 2006 18:12:23 +0800 Subject: Fix Tsec bug when no link When tftp a non-exist file from the tftp server, u-boot will check the link of all eth port. The original file will return wrong link state on the no link ports. signed-off-by: Jason Jin --- drivers/tsec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/tsec.c b/drivers/tsec.c index 18778c270a..a8a2ba2f52 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -372,7 +372,7 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private *priv) if (i > PHY_AUTONEGOTIATE_TIMEOUT) { puts (" TIMEOUT !\n"); priv->link = 0; - break; + return 0; } if ((i++ % 1000) == 0) { -- cgit v1.2.1 From bc09cf3c2bfb8d54c659cbb332f79d0950982fd0 Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong-R64188 Date: Tue, 27 Jun 2006 18:12:10 +0800 Subject: Fix RTL8139 in big endian signed-off-by: Jason Jin signed-off-by: Wei Zhang --- drivers/rtl8139.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c index a95f84e625..848d1d177a 100644 --- a/drivers/rtl8139.c +++ b/drivers/rtl8139.c @@ -196,6 +196,7 @@ static void rtl_disable(struct eth_device *dev); static struct pci_device_id supported[] = { {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139}, + {0x1186, 0x1300}, {} }; -- cgit v1.2.1 From da012ab661fd4ab169dd7b9b32201a4df62cf34a Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong Date: Wed, 28 Jun 2006 08:43:56 -0500 Subject: Change Id to symbolic name for RTL8139 Signed-off-by: Jason Jin --- drivers/rtl8139.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c index 848d1d177a..afe1a4fdaf 100644 --- a/drivers/rtl8139.c +++ b/drivers/rtl8139.c @@ -196,7 +196,7 @@ static void rtl_disable(struct eth_device *dev); static struct pci_device_id supported[] = { {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139}, - {0x1186, 0x1300}, + {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139}, {} }; -- cgit v1.2.1 From a4e11558b810ef2cddffdf7b9d86bc1130441960 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:44:23 -0500 Subject: * Made sure the code which disables prefetch for PCI devices sets the size of the prefetch region to 0 Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming --- drivers/pci_auto.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 15f74328f0..8fde3301e5 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -186,7 +186,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose, } else { /* We don't support prefetchable memory for now, so disable */ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); - pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000); + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0); } if (pci_io) { -- cgit v1.2.1 From 4782ac80b02f0d01afd309e2200dd3c7037f2ba4 Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong Date: Wed, 23 Aug 2006 19:10:44 +0800 Subject: Add AHCI support to u-boot Add AHCI support in u-boot, enable the sata disk controllers which following the AHCI protocol. Signed-off-by:Jason Jin --- drivers/Makefile | 2 +- drivers/ahci.c | 706 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 707 insertions(+), 1 deletion(-) create mode 100644 drivers/ahci.c (limited to 'drivers') diff --git a/drivers/Makefile b/drivers/Makefile index e6176ed86a..98c4ef95f8 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -44,7 +44,7 @@ OBJS = 3c589.o 5701rls.o ali512x.o \ serial.o serial_max3100.o \ serial_pl010.o serial_pl011.o serial_xuartlite.o \ sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ - status_led.o sym53c8xx.o \ + status_led.o sym53c8xx.o ahci.o \ ti_pci1410a.o tigon3.o tsec.o \ usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \ videomodes.o w83c553f.o \ diff --git a/drivers/ahci.c b/drivers/ahci.c new file mode 100644 index 0000000000..828498ddce --- /dev/null +++ b/drivers/ahci.c @@ -0,0 +1,706 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * Author: Jason Jin + * Zhang Wei + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference on libata and ahci drvier in kernel + * + */ +#include + +#ifdef CONFIG_SCSI_AHCI + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct ahci_probe_ent *probe_ent = NULL; +hd_driveid_t *ataid[AHCI_MAX_PORTS]; + +#define writel_with_flush(a,b) do{writel(a,b);readl(b);}while(0) + +static inline u32 ahci_port_base(u32 base, u32 port) +{ + return base + 0x100 + (port * 0x80); +} + + +static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, + unsigned int port_idx) +{ + base = ahci_port_base(base, port_idx); + + port->cmd_addr = base; + port->scr_addr = base + PORT_SCR; +} + + +#define msleep(a) udelay(a * 1000) +#define ssleep(a) msleep(a * 1000) +static int waiting_for_cmd_completed(volatile u8 *offset, int timeout_msec, u32 sign) +{ + int i; + u32 status; + for(i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) + msleep(1); + + return (i < timeout_msec)? 0 : -1; +} + + +static int ahci_host_init(struct ahci_probe_ent *probe_ent) +{ + pci_dev_t pdev = probe_ent->dev; + volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; + u32 tmp, cap_save; + u16 tmp16; + int i, j; + volatile u8* port_mmio; + unsigned short vendor; + + cap_save = readl(mmio + HOST_CAP); + cap_save &= ( (1<<28) | (1<<17) ); + cap_save |= (1 << 27); + + /* global controller reset */ + tmp = readl(mmio + HOST_CTL); + if ((tmp & HOST_RESET) == 0) + writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); + + /* reset must complete within 1 second, or + * the hardware should be considered fried. + */ + ssleep(1); + + tmp = readl(mmio + HOST_CTL); + if (tmp & HOST_RESET) { + debug("controller reset failed (0x%x)\n", tmp); + return -1; + } + + writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); + writel(cap_save, mmio + HOST_CAP); + writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); + + pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); + + if (vendor == PCI_VENDOR_ID_INTEL) { + u16 tmp16; + pci_read_config_word(pdev, 0x92, &tmp16); + tmp16 |= 0xf; + pci_write_config_word(pdev, 0x92, tmp16); + } + + probe_ent->cap = readl(mmio + HOST_CAP); + probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); + probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; + + debug("cap 0x%x port_map 0x%x n_ports %d\n", + probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); + + for (i = 0; i < probe_ent->n_ports; i++) { + probe_ent->port[i].port_mmio = ahci_port_base((u32)mmio, i); + port_mmio = (u8 *)probe_ent->port[i].port_mmio; + ahci_setup_port(&probe_ent->port[i], + (unsigned long) mmio, i); + + /* make sure port is not active */ + tmp = readl(port_mmio + PORT_CMD); + if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | + PORT_CMD_FIS_RX | PORT_CMD_START)) { + tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | + PORT_CMD_FIS_RX | PORT_CMD_START); + writel_with_flush(tmp, port_mmio + PORT_CMD); + + /* spec says 500 msecs for each bit, so + * this is slightly incorrect. + */ + msleep(500); + } + + writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); + + j = 0; + while (j < 100) { + msleep(10); + tmp = readl(port_mmio + PORT_SCR_STAT); + if ((tmp & 0xf) == 0x3) + break; + j++; + } + + tmp = readl(port_mmio + PORT_SCR_ERR); + debug("PORT_SCR_ERR 0x%x\n", tmp); + writel(tmp, port_mmio + PORT_SCR_ERR); + + /* ack any pending irq events for this port */ + tmp = readl(port_mmio + PORT_IRQ_STAT); + debug("PORT_IRQ_STAT 0x%x\n", tmp); + if (tmp) + writel(tmp, port_mmio + PORT_IRQ_STAT); + + writel(1 << i, mmio + HOST_IRQ_STAT); + + /* set irq mask (enables interrupts) */ + writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); + + /*register linkup ports*/ + tmp = readl(port_mmio + PORT_SCR_STAT); + debug("Port %d status: 0x%x\n",i,tmp); + if((tmp & 0xf) == 0x03) + probe_ent->link_port_map |= (0x01<< i); + } + + tmp = readl(mmio + HOST_CTL); + debug("HOST_CTL 0x%x\n", tmp); + writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); + tmp = readl(mmio + HOST_CTL); + debug("HOST_CTL 0x%x\n", tmp); + + pci_read_config_word(pdev, PCI_COMMAND, &tmp16); + tmp |= PCI_COMMAND_MASTER; + pci_write_config_word(pdev, PCI_COMMAND, tmp16); + + return 0; +} + + +static void ahci_print_info(struct ahci_probe_ent *probe_ent) +{ + pci_dev_t pdev = probe_ent->dev; + volatile u8* mmio = (volatile u8 *)probe_ent->mmio_base; + u32 vers, cap, impl, speed; + const char *speed_s; + u16 cc; + const char *scc_s; + + vers = readl(mmio + HOST_VERSION); + cap = probe_ent->cap; + impl = probe_ent->port_map; + + speed = (cap >> 20) & 0xf; + if (speed == 1) + speed_s = "1.5"; + else if (speed == 2) + speed_s = "3"; + else + speed_s = "?"; + + pci_read_config_word(pdev, 0x0a, &cc); + if (cc == 0x0101) + scc_s = "IDE"; + else if (cc == 0x0106) + scc_s = "SATA"; + else if (cc == 0x0104) + scc_s = "RAID"; + else + scc_s = "unknown"; + + printf( "AHCI %02x%02x.%02x%02x " + "%u slots %u ports %s Gbps 0x%x impl %s mode\n" + , + + (vers >> 24) & 0xff, + (vers >> 16) & 0xff, + (vers >> 8) & 0xff, + vers & 0xff, + + ((cap >> 8) & 0x1f) + 1, + (cap & 0x1f) + 1, + speed_s, + impl, + scc_s); + + printf("flags: " + "%s%s%s%s%s%s" + "%s%s%s%s%s%s%s\n" + , + + cap & (1 << 31) ? "64bit " : "", + cap & (1 << 30) ? "ncq " : "", + cap & (1 << 28) ? "ilck " : "", + cap & (1 << 27) ? "stag " : "", + cap & (1 << 26) ? "pm " : "", + cap & (1 << 25) ? "led " : "", + + cap & (1 << 24) ? "clo " : "", + cap & (1 << 19) ? "nz " : "", + cap & (1 << 18) ? "only " : "", + cap & (1 << 17) ? "pmp " : "", + cap & (1 << 15) ? "pio " : "", + cap & (1 << 14) ? "slum " : "", + cap & (1 << 13) ? "part " : "" + ); +} + + +static int ahci_init_one (pci_dev_t pdev) +{ + u32 iobase, vendor; + int rc; + + memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); + + probe_ent = malloc(sizeof(probe_ent)); + memset(probe_ent, 0, sizeof(probe_ent)); + probe_ent->dev = pdev; + + pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase); + iobase &= ~0xf; + + probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY + | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA + | ATA_FLAG_NO_ATAPI; + probe_ent->pio_mask = 0x1f; + probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6*/ + + probe_ent->mmio_base = iobase; + + /* Take from kernel: + * JMicron-specific fixup: + * make sure we're in AHCI mode + */ + pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); + if(vendor == 0x197b) + pci_write_config_byte(pdev, 0x41, 0xa1); + + /* initialize adapter */ + rc = ahci_host_init(probe_ent); + if (rc) + goto err_out; + + ahci_print_info(probe_ent); + + return 0; + +err_out: + return rc; +} + + +#define MAX_DATA_BYTE_COUNT (4*1024*1024) +static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) +{ + + struct ahci_ioports *pp = &(probe_ent->port[port]); + struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; + u32 sg_count; + int i; + + sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; + if(sg_count > AHCI_MAX_SG){ + printf("Error:Too much sg!\n"); + return -1; + } + + for(i = 0;i < sg_count; i++) + { + ahci_sg->addr = cpu_to_le32((u32)buf + i * MAX_DATA_BYTE_COUNT); + ahci_sg->addr_hi = 0; + ahci_sg->flags_size = cpu_to_le32( 0x3fffff & + (buf_len < MAX_DATA_BYTE_COUNT + ? (buf_len - 1) + : (MAX_DATA_BYTE_COUNT - 1))); + ahci_sg++; + buf_len -= MAX_DATA_BYTE_COUNT; + } + + return sg_count; +} + + +static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) +{ + pp->cmd_slot->opts = cpu_to_le32(opts); + pp->cmd_slot->status = 0; + pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); + pp->cmd_slot->tbl_addr_hi = 0; +} + + +static void ahci_set_feature(u8 port) +{ + + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; + u32 cmd_fis_len = 5; /* five dwords */ + u8 fis[20]; + + /*set feature*/ + memset(fis,0,20); + fis[0] = 0x27; + fis[1] = 1 << 7; + fis[2] = ATA_CMD_SETF; + fis[3] = SETFEATURES_XFER; + fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; + + memcpy((unsigned char *)pp->cmd_tbl,fis,20); + ahci_fill_cmd_slot(pp, cmd_fis_len); + writel(1, port_mmio + PORT_CMD_ISSUE); + readl(port_mmio + PORT_CMD_ISSUE); + + if(waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + printf("set feature error!\n"); + } +} + + +static int ahci_port_start(u8 port) +{ + + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; + u32 port_status; + u32 mem; + + debug("Enter start port: %d\n",port); + port_status = readl(port_mmio + PORT_SCR_STAT); + debug("Port %d status: %x\n",port,port_status); + if((port_status & 0xf) != 0x03){ + printf("No Link on this port!\n"); + return -1; + } + + mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); + if (!mem) { + free(pp); + printf("No mem for table!\n"); + return -ENOMEM; + } + + mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ + + memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); + /* + * First item in chunk of DMA memory: 32-slot command table, + * 32 bytes each in size + */ + pp->cmd_slot = (struct ahci_cmd_hdr *)mem; + debug("cmd_slot = 0x%x\n",pp->cmd_slot); + + mem += (AHCI_CMD_SLOT_SZ + 224); + /* + * Second item: Received-FIS area + */ + pp->rx_fis = mem; + + mem += AHCI_RX_FIS_SZ; + /* + * Third item: data area for storing a single command + * and its scatter-gather table + */ + pp->cmd_tbl = mem; + debug("cmd_tbl_dma = 0x%x\n",pp->cmd_tbl); + + mem += AHCI_CMD_TBL_HDR; + pp->cmd_tbl_sg = (struct ahci_sg *)mem; + + writel_with_flush((u32)pp->cmd_slot, port_mmio + PORT_LST_ADDR); + + writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); + + writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | + PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | + PORT_CMD_START, port_mmio + PORT_CMD); + + debug("Exit start port %d\n",port); + + return 0; +} + + +static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, int buf_len) +{ + + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; + u32 opts; + u32 port_status; + int sg_count; + + debug("Enter get_ahci_device_data: for port %d\n",port); + + if(port > probe_ent->n_ports){ + printf("Invaild port number %d\n", port); + return -1; + } + + port_status = readl(port_mmio + PORT_SCR_STAT); + if((port_status & 0xf) != 0x03){ + debug("No Link on port %d!\n",port); + return -1; + } + + memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); + + sg_count = ahci_fill_sg(port,buf,buf_len); + opts = (fis_len >> 2) | (sg_count << 16) ; + ahci_fill_cmd_slot(pp, opts); + + writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); + + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + printf("timeout exit!\n"); + return -1; + } + debug("get_ahci_device_data: %d byte transferred.\n", + pp->cmd_slot->status); + + return 0; +} + + +static char *ata_id_strcpy(u16 *target, u16 *src, int len) +{ + int i; + for(i = 0; i < len / 2; i++) + target[i] = le16_to_cpu(src[i]); + return (char *)target; +} + + +static void dump_ataid(hd_driveid_t *ataid) +{ + debug("(49)ataid->capability = 0x%x\n", ataid->capability); + debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); + debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); + debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); + debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); + debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); + debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); + debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); + debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); + debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); + debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); + debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); + debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); + debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); + debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); +} + +/* + * SCSI INQUIRY command operation. + */ +static int ata_scsiop_inquiry(ccb *pccb) +{ + u8 hdr[] = { + 0, + 0, + 0x5, /* claim SPC-3 version compatibility */ + 2, + 95 - 4, + }; + u8 fis[20]; + u8 *tmpid; + u8 port; + + /* Clean ccb data buffer */ + memset(pccb->pdata, 0, pccb->datalen); + + memcpy(pccb->pdata, hdr, sizeof(hdr)); + + if(pccb->datalen <= 35) + return 0; + + memset(fis, 0, 20); + /* Construct the FIS */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_IDENT; /* Command byte. */ + + /* Read id from sata */ + port = pccb->target; + if(!(tmpid = malloc(sizeof(hd_driveid_t)))) + return -ENOMEM; + + if(get_ahci_device_data(port, (u8 *)&fis, 20, + tmpid, sizeof(hd_driveid_t))){ + debug("scsi_ahci: SCSI inquiry command failure.\n"); + return -EIO; + } + + if(ataid[port]) + free(ataid[port]); + ataid[port] = (hd_driveid_t *)tmpid; + + memcpy(&pccb->pdata[8], "ATA ", 8); + ata_id_strcpy((u16 *)&pccb->pdata[16], (u16 *)ataid[port]->model, 16); + ata_id_strcpy((u16 *)&pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); + + dump_ataid(ataid[port]); + return 0; +} + + +/* + * SCSI READ10 command operation. + */ +static int ata_scsiop_read10(ccb *pccb) +{ + u64 lba = 0; + u32 len = 0; + u8 fis[20]; + + lba = (((u64)pccb->cmd[2]) << 24) | (((u64)pccb->cmd[3]) << 16) + | (((u64)pccb->cmd[4]) << 8) | ((u64)pccb->cmd[5]); + len = (((u32)pccb->cmd[7]) << 8) | ((u32)pccb->cmd[8]); + + /* For 10-byte and 16-byte SCSI R/W commands, transfer + * length 0 means transfer 0 block of data. + * However, for ATA R/W commands, sector count 0 means + * 256 or 65536 sectors, not 0 sectors as in SCSI. + * + * WARNING: one or two older ATA drives treat 0 as 0... + */ + if(!len) return 0; + memset(fis, 0, 20); + + /* Construct the FIS */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ + + /* LBA address, only support LBA28 in this driver*/ + fis[4] = pccb->cmd[5]; + fis[5] = pccb->cmd[4]; + fis[6] = pccb->cmd[3]; + fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0; + + /* Sector Count */ + fis[12] = pccb->cmd[8]; + fis[13] = pccb->cmd[7]; + + /* Read from ahci */ + if(get_ahci_device_data(pccb->target, (u8*)&fis, 20, + pccb->pdata, pccb->datalen)){ + debug("scsi_ahci: SCSI READ10 command failure.\n"); + return -EIO; + } + + return 0; +} + + +/* + * SCSI READ CAPACITY10 command operation. + */ +static int ata_scsiop_read_capacity10(ccb *pccb) +{ + u8 buf[8]; + + if(!ataid[pccb->target]) { + printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " + "\tNo ATA info!\n" + "\tPlease run SCSI commmand INQUIRY firstly!\n"); + return -EPERM; + } + + memset(buf, 0, 8); + + *(u32 *)buf = le32_to_cpu(ataid[pccb->target]->lba_capacity); + + buf[6] = 512 >> 8; + buf[7] = 512 & 0xff; + + memcpy(pccb->pdata, buf, 8); + + return 0; +} + + +/* + * SCSI TEST UNIT READY command operation. + */ +static int ata_scsiop_test_unit_ready(ccb *pccb) +{ + return (ataid[pccb->target]) ? 0 : -EPERM; +} + +int scsi_exec(ccb *pccb) +{ + int ret; + + switch(pccb->cmd[0]) { + case SCSI_READ10: + ret = ata_scsiop_read10(pccb); + break; + case SCSI_RD_CAPAC: + ret = ata_scsiop_read_capacity10(pccb); + break; + case SCSI_TST_U_RDY: + ret = ata_scsiop_test_unit_ready(pccb); + break; + case SCSI_INQUIRY: + ret = ata_scsiop_inquiry(pccb); + break; + default: + printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); + return FALSE; + } + + if(ret) { + debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0],ret); + return FALSE; + } + return TRUE; + +} + + +void scsi_low_level_init(int busdevfunc) +{ + int i; + u32 linkmap; + + ahci_init_one(busdevfunc); + + linkmap = probe_ent->link_port_map; + + for(i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++){ + if( ((linkmap >> i) & 0x01) ){ + if(ahci_port_start((u8)i)){ + printf("Can not start port %d\n",i); + continue; + } + ahci_set_feature((u8)i); + } + } +} + + +void scsi_bus_reset(void) +{ +/*Not implement*/ +} + + +void scsi_print_error(ccb *pccb) +{ +/*The ahci error info can be read in the ahci driver*/ +} +#endif -- cgit v1.2.1 From 4a7cc0f21918e6ecf07ed57075d67df2c4a1299c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 23 Aug 2006 11:04:43 -0500 Subject: Cleanup and lindent new AHCI driver. --- drivers/ahci.c | 280 ++++++++++++++++++++++++++++----------------------------- 1 file changed, 138 insertions(+), 142 deletions(-) (limited to 'drivers') diff --git a/drivers/ahci.c b/drivers/ahci.c index 828498ddce..8ceff00925 100644 --- a/drivers/ahci.c +++ b/drivers/ahci.c @@ -42,7 +42,8 @@ struct ahci_probe_ent *probe_ent = NULL; hd_driveid_t *ataid[AHCI_MAX_PORTS]; -#define writel_with_flush(a,b) do{writel(a,b);readl(b);}while(0) +#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) + static inline u32 ahci_port_base(u32 base, u32 port) { @@ -55,21 +56,25 @@ static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, { base = ahci_port_base(base, port_idx); - port->cmd_addr = base; - port->scr_addr = base + PORT_SCR; + port->cmd_addr = base; + port->scr_addr = base + PORT_SCR; } #define msleep(a) udelay(a * 1000) #define ssleep(a) msleep(a * 1000) -static int waiting_for_cmd_completed(volatile u8 *offset, int timeout_msec, u32 sign) + +static int waiting_for_cmd_completed(volatile u8 *offset, + int timeout_msec, + u32 sign) { int i; u32 status; - for(i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) + + for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) msleep(1); - return (i < timeout_msec)? 0 : -1; + return (i < timeout_msec) ? 0 : -1; } @@ -80,11 +85,11 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) u32 tmp, cap_save; u16 tmp16; int i, j; - volatile u8* port_mmio; + volatile u8 *port_mmio; unsigned short vendor; cap_save = readl(mmio + HOST_CAP); - cap_save &= ( (1<<28) | (1<<17) ); + cap_save &= ((1 << 28) | (1 << 17)); cap_save |= (1 << 27); /* global controller reset */ @@ -121,13 +126,12 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; debug("cap 0x%x port_map 0x%x n_ports %d\n", - probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); + probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); for (i = 0; i < probe_ent->n_ports; i++) { - probe_ent->port[i].port_mmio = ahci_port_base((u32)mmio, i); - port_mmio = (u8 *)probe_ent->port[i].port_mmio; - ahci_setup_port(&probe_ent->port[i], - (unsigned long) mmio, i); + probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); + port_mmio = (u8 *) probe_ent->port[i].port_mmio; + ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); /* make sure port is not active */ tmp = readl(port_mmio + PORT_CMD); @@ -169,11 +173,11 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) /* set irq mask (enables interrupts) */ writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); - /*register linkup ports*/ + /*register linkup ports */ tmp = readl(port_mmio + PORT_SCR_STAT); - debug("Port %d status: 0x%x\n",i,tmp); - if((tmp & 0xf) == 0x03) - probe_ent->link_port_map |= (0x01<< i); + debug("Port %d status: 0x%x\n", i, tmp); + if ((tmp & 0xf) == 0x03) + probe_ent->link_port_map |= (0x01 << i); } tmp = readl(mmio + HOST_CTL); @@ -193,7 +197,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) static void ahci_print_info(struct ahci_probe_ent *probe_ent) { pci_dev_t pdev = probe_ent->dev; - volatile u8* mmio = (volatile u8 *)probe_ent->mmio_base; + volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; u32 vers, cap, impl, speed; const char *speed_s; u16 cc; @@ -221,50 +225,38 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) else scc_s = "unknown"; - printf( "AHCI %02x%02x.%02x%02x " - "%u slots %u ports %s Gbps 0x%x impl %s mode\n" - , - - (vers >> 24) & 0xff, - (vers >> 16) & 0xff, - (vers >> 8) & 0xff, - vers & 0xff, - - ((cap >> 8) & 0x1f) + 1, - (cap & 0x1f) + 1, - speed_s, - impl, - scc_s); + printf("AHCI %02x%02x.%02x%02x " + "%u slots %u ports %s Gbps 0x%x impl %s mode\n", + (vers >> 24) & 0xff, + (vers >> 16) & 0xff, + (vers >> 8) & 0xff, + vers & 0xff, + ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); printf("flags: " - "%s%s%s%s%s%s" - "%s%s%s%s%s%s%s\n" - , - - cap & (1 << 31) ? "64bit " : "", - cap & (1 << 30) ? "ncq " : "", - cap & (1 << 28) ? "ilck " : "", - cap & (1 << 27) ? "stag " : "", - cap & (1 << 26) ? "pm " : "", - cap & (1 << 25) ? "led " : "", - - cap & (1 << 24) ? "clo " : "", - cap & (1 << 19) ? "nz " : "", - cap & (1 << 18) ? "only " : "", - cap & (1 << 17) ? "pmp " : "", - cap & (1 << 15) ? "pio " : "", - cap & (1 << 14) ? "slum " : "", - cap & (1 << 13) ? "part " : "" - ); + "%s%s%s%s%s%s" + "%s%s%s%s%s%s%s\n", + cap & (1 << 31) ? "64bit " : "", + cap & (1 << 30) ? "ncq " : "", + cap & (1 << 28) ? "ilck " : "", + cap & (1 << 27) ? "stag " : "", + cap & (1 << 26) ? "pm " : "", + cap & (1 << 25) ? "led " : "", + cap & (1 << 24) ? "clo " : "", + cap & (1 << 19) ? "nz " : "", + cap & (1 << 18) ? "only " : "", + cap & (1 << 17) ? "pmp " : "", + cap & (1 << 15) ? "pio " : "", + cap & (1 << 14) ? "slum " : "", + cap & (1 << 13) ? "part " : ""); } - -static int ahci_init_one (pci_dev_t pdev) +static int ahci_init_one(pci_dev_t pdev) { u32 iobase, vendor; int rc; - memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); + memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); probe_ent = malloc(sizeof(probe_ent)); memset(probe_ent, 0, sizeof(probe_ent)); @@ -273,20 +265,22 @@ static int ahci_init_one (pci_dev_t pdev) pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase); iobase &= ~0xf; - probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY - | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA - | ATA_FLAG_NO_ATAPI; - probe_ent->pio_mask = 0x1f; - probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6*/ + probe_ent->host_flags = ATA_FLAG_SATA + | ATA_FLAG_NO_LEGACY + | ATA_FLAG_MMIO + | ATA_FLAG_PIO_DMA + | ATA_FLAG_NO_ATAPI; + probe_ent->pio_mask = 0x1f; + probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ - probe_ent->mmio_base = iobase; + probe_ent->mmio_base = iobase; /* Take from kernel: * JMicron-specific fixup: * make sure we're in AHCI mode */ pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); - if(vendor == 0x197b) + if (vendor == 0x197b) pci_write_config_byte(pdev, 0x41, 0xa1); /* initialize adapter */ @@ -298,34 +292,34 @@ static int ahci_init_one (pci_dev_t pdev) return 0; -err_out: + err_out: return rc; } #define MAX_DATA_BYTE_COUNT (4*1024*1024) + static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) { - struct ahci_ioports *pp = &(probe_ent->port[port]); struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; u32 sg_count; int i; sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; - if(sg_count > AHCI_MAX_SG){ + if (sg_count > AHCI_MAX_SG) { printf("Error:Too much sg!\n"); return -1; } - for(i = 0;i < sg_count; i++) - { - ahci_sg->addr = cpu_to_le32((u32)buf + i * MAX_DATA_BYTE_COUNT); + for (i = 0; i < sg_count; i++) { + ahci_sg->addr = + cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); ahci_sg->addr_hi = 0; - ahci_sg->flags_size = cpu_to_le32( 0x3fffff & - (buf_len < MAX_DATA_BYTE_COUNT - ? (buf_len - 1) - : (MAX_DATA_BYTE_COUNT - 1))); + ahci_sg->flags_size = cpu_to_le32(0x3fffff & + (buf_len < MAX_DATA_BYTE_COUNT + ? (buf_len - 1) + : (MAX_DATA_BYTE_COUNT - 1))); ahci_sg++; buf_len -= MAX_DATA_BYTE_COUNT; } @@ -345,26 +339,25 @@ static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) static void ahci_set_feature(u8 port) { - struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; - u32 cmd_fis_len = 5; /* five dwords */ + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + u32 cmd_fis_len = 5; /* five dwords */ u8 fis[20]; - /*set feature*/ - memset(fis,0,20); + /*set feature */ + memset(fis, 0, 20); fis[0] = 0x27; fis[1] = 1 << 7; fis[2] = ATA_CMD_SETF; fis[3] = SETFEATURES_XFER; fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; - memcpy((unsigned char *)pp->cmd_tbl,fis,20); + memcpy((unsigned char *)pp->cmd_tbl, fis, 20); ahci_fill_cmd_slot(pp, cmd_fis_len); writel(1, port_mmio + PORT_CMD_ISSUE); readl(port_mmio + PORT_CMD_ISSUE); - if(waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { printf("set feature error!\n"); } } @@ -372,94 +365,94 @@ static void ahci_set_feature(u8 port) static int ahci_port_start(u8 port) { - struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; u32 port_status; u32 mem; - debug("Enter start port: %d\n",port); + debug("Enter start port: %d\n", port); port_status = readl(port_mmio + PORT_SCR_STAT); - debug("Port %d status: %x\n",port,port_status); - if((port_status & 0xf) != 0x03){ + debug("Port %d status: %x\n", port, port_status); + if ((port_status & 0xf) != 0x03) { printf("No Link on this port!\n"); return -1; } - mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); + mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); if (!mem) { free(pp); printf("No mem for table!\n"); return -ENOMEM; } - mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ + mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ + memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); - memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); /* * First item in chunk of DMA memory: 32-slot command table, * 32 bytes each in size */ pp->cmd_slot = (struct ahci_cmd_hdr *)mem; - debug("cmd_slot = 0x%x\n",pp->cmd_slot); - + debug("cmd_slot = 0x%x\n", pp->cmd_slot); mem += (AHCI_CMD_SLOT_SZ + 224); + /* * Second item: Received-FIS area */ pp->rx_fis = mem; - mem += AHCI_RX_FIS_SZ; + /* * Third item: data area for storing a single command * and its scatter-gather table */ pp->cmd_tbl = mem; - debug("cmd_tbl_dma = 0x%x\n",pp->cmd_tbl); + debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); mem += AHCI_CMD_TBL_HDR; pp->cmd_tbl_sg = (struct ahci_sg *)mem; - writel_with_flush((u32)pp->cmd_slot, port_mmio + PORT_LST_ADDR); + writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | - PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | - PORT_CMD_START, port_mmio + PORT_CMD); + PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | + PORT_CMD_START, port_mmio + PORT_CMD); - debug("Exit start port %d\n",port); + debug("Exit start port %d\n", port); return 0; } -static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, int buf_len) +static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, + int buf_len) { - struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; u32 opts; u32 port_status; int sg_count; - debug("Enter get_ahci_device_data: for port %d\n",port); + debug("Enter get_ahci_device_data: for port %d\n", port); - if(port > probe_ent->n_ports){ + if (port > probe_ent->n_ports) { printf("Invaild port number %d\n", port); return -1; } port_status = readl(port_mmio + PORT_SCR_STAT); - if((port_status & 0xf) != 0x03){ - debug("No Link on port %d!\n",port); + if ((port_status & 0xf) != 0x03) { + debug("No Link on port %d!\n", port); return -1; } memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); - sg_count = ahci_fill_sg(port,buf,buf_len); - opts = (fis_len >> 2) | (sg_count << 16) ; + sg_count = ahci_fill_sg(port, buf, buf_len); + opts = (fis_len >> 2) | (sg_count << 16); ahci_fill_cmd_slot(pp, opts); writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); @@ -469,7 +462,7 @@ static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, int buf_ return -1; } debug("get_ahci_device_data: %d byte transferred.\n", - pp->cmd_slot->status); + pp->cmd_slot->status); return 0; } @@ -478,7 +471,7 @@ static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, int buf_ static char *ata_id_strcpy(u16 *target, u16 *src, int len) { int i; - for(i = 0; i < len / 2; i++) + for (i = 0; i < len / 2; i++) target[i] = le16_to_cpu(src[i]); return (char *)target; } @@ -503,6 +496,7 @@ static void dump_ataid(hd_driveid_t *ataid) debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); } + /* * SCSI INQUIRY command operation. */ @@ -511,7 +505,7 @@ static int ata_scsiop_inquiry(ccb *pccb) u8 hdr[] = { 0, 0, - 0x5, /* claim SPC-3 version compatibility */ + 0x5, /* claim SPC-3 version compatibility */ 2, 95 - 4, }; @@ -524,33 +518,33 @@ static int ata_scsiop_inquiry(ccb *pccb) memcpy(pccb->pdata, hdr, sizeof(hdr)); - if(pccb->datalen <= 35) + if (pccb->datalen <= 35) return 0; memset(fis, 0, 20); /* Construct the FIS */ - fis[0] = 0x27; /* Host to device FIS. */ - fis[1] = 1 << 7; /* Command FIS. */ - fis[2] = ATA_CMD_IDENT; /* Command byte. */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_IDENT; /* Command byte. */ /* Read id from sata */ port = pccb->target; - if(!(tmpid = malloc(sizeof(hd_driveid_t)))) + if (!(tmpid = malloc(sizeof(hd_driveid_t)))) return -ENOMEM; - if(get_ahci_device_data(port, (u8 *)&fis, 20, - tmpid, sizeof(hd_driveid_t))){ + if (get_ahci_device_data(port, (u8 *) & fis, 20, + tmpid, sizeof(hd_driveid_t))) { debug("scsi_ahci: SCSI inquiry command failure.\n"); return -EIO; } - if(ataid[port]) + if (ataid[port]) free(ataid[port]); - ataid[port] = (hd_driveid_t *)tmpid; + ataid[port] = (hd_driveid_t *) tmpid; memcpy(&pccb->pdata[8], "ATA ", 8); - ata_id_strcpy((u16 *)&pccb->pdata[16], (u16 *)ataid[port]->model, 16); - ata_id_strcpy((u16 *)&pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); + ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16); + ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); dump_ataid(ataid[port]); return 0; @@ -560,15 +554,15 @@ static int ata_scsiop_inquiry(ccb *pccb) /* * SCSI READ10 command operation. */ -static int ata_scsiop_read10(ccb *pccb) +static int ata_scsiop_read10(ccb * pccb) { u64 lba = 0; u32 len = 0; u8 fis[20]; - lba = (((u64)pccb->cmd[2]) << 24) | (((u64)pccb->cmd[3]) << 16) - | (((u64)pccb->cmd[4]) << 8) | ((u64)pccb->cmd[5]); - len = (((u32)pccb->cmd[7]) << 8) | ((u32)pccb->cmd[8]); + lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16) + | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]); + len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]); /* For 10-byte and 16-byte SCSI R/W commands, transfer * length 0 means transfer 0 block of data. @@ -577,15 +571,16 @@ static int ata_scsiop_read10(ccb *pccb) * * WARNING: one or two older ATA drives treat 0 as 0... */ - if(!len) return 0; + if (!len) + return 0; memset(fis, 0, 20); /* Construct the FIS */ - fis[0] = 0x27; /* Host to device FIS. */ - fis[1] = 1 << 7; /* Command FIS. */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ - /* LBA address, only support LBA28 in this driver*/ + /* LBA address, only support LBA28 in this driver */ fis[4] = pccb->cmd[5]; fis[5] = pccb->cmd[4]; fis[6] = pccb->cmd[3]; @@ -596,8 +591,8 @@ static int ata_scsiop_read10(ccb *pccb) fis[13] = pccb->cmd[7]; /* Read from ahci */ - if(get_ahci_device_data(pccb->target, (u8*)&fis, 20, - pccb->pdata, pccb->datalen)){ + if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20, + pccb->pdata, pccb->datalen)) { debug("scsi_ahci: SCSI READ10 command failure.\n"); return -EIO; } @@ -613,16 +608,16 @@ static int ata_scsiop_read_capacity10(ccb *pccb) { u8 buf[8]; - if(!ataid[pccb->target]) { + if (!ataid[pccb->target]) { printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " - "\tNo ATA info!\n" - "\tPlease run SCSI commmand INQUIRY firstly!\n"); + "\tNo ATA info!\n" + "\tPlease run SCSI commmand INQUIRY firstly!\n"); return -EPERM; } memset(buf, 0, 8); - *(u32 *)buf = le32_to_cpu(ataid[pccb->target]->lba_capacity); + *(u32 *) buf = le32_to_cpu(ataid[pccb->target]->lba_capacity); buf[6] = 512 >> 8; buf[7] = 512 & 0xff; @@ -641,11 +636,12 @@ static int ata_scsiop_test_unit_ready(ccb *pccb) return (ataid[pccb->target]) ? 0 : -EPERM; } + int scsi_exec(ccb *pccb) { int ret; - switch(pccb->cmd[0]) { + switch (pccb->cmd[0]) { case SCSI_READ10: ret = ata_scsiop_read10(pccb); break; @@ -663,8 +659,8 @@ int scsi_exec(ccb *pccb) return FALSE; } - if(ret) { - debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0],ret); + if (ret) { + debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); return FALSE; } return TRUE; @@ -681,13 +677,13 @@ void scsi_low_level_init(int busdevfunc) linkmap = probe_ent->link_port_map; - for(i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++){ - if( ((linkmap >> i) & 0x01) ){ - if(ahci_port_start((u8)i)){ - printf("Can not start port %d\n",i); + for (i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++) { + if (((linkmap >> i) & 0x01)) { + if (ahci_port_start((u8) i)) { + printf("Can not start port %d\n", i); continue; } - ahci_set_feature((u8)i); + ahci_set_feature((u8) i); } } } @@ -695,12 +691,12 @@ void scsi_low_level_init(int busdevfunc) void scsi_bus_reset(void) { -/*Not implement*/ + /*Not implement*/ } -void scsi_print_error(ccb *pccb) +void scsi_print_error(ccb * pccb) { -/*The ahci error info can be read in the ahci driver*/ + /*The ahci error info can be read in the ahci driver*/ } #endif -- cgit v1.2.1 From 09f3e09e9ebcfa7919ca8931a4b5504fadd1f1d3 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 13 Sep 2006 10:34:18 -0500 Subject: Add support for eTSEC 3 & 4 on 8548 CDS * Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS. This will only work on rev 1.3 boards (but doesn't break older boards) * Cleaned up some comments to reflect the expanded role of tsec in other systems --- drivers/tsec.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++--------- drivers/tsec.h | 17 +++++++++++++++ 2 files changed, 76 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/tsec.c b/drivers/tsec.c index 7ec565ca67..bfc49c4629 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -44,9 +44,7 @@ struct tsec_info_struct { /* The tsec_info structure contains 3 values which the * driver uses to determine how to operate a given ethernet - * device. For now, the structure is initialized with the - * knowledge that all current implementations have 2 TSEC - * devices, and one FEC. The information needed is: + * device. The information needed is: * phyaddr - The address of the PHY which is attached to * the given device. * @@ -56,18 +54,16 @@ struct tsec_info_struct { * * phyregidx - This variable specifies which ethernet device * controls the MII Management registers which are connected - * to the PHY. For 8540/8560, only TSEC1 (index 0) has + * to the PHY. For now, only TSEC1 (index 0) has * access to the PHYs, so all of the entries have "0". * * The values specified in the table are taken from the board's * config file in include/configs/. When implementing a new * board with ethernet capability, it is necessary to define: - * TSEC1_PHY_ADDR - * TSEC1_PHYIDX - * TSEC2_PHY_ADDR - * TSEC2_PHYIDX + * TSECn_PHY_ADDR + * TSECn_PHYIDX * - * and for 8560: + * for n = 1,2,3, etc. And for FEC: * FEC_PHY_ADDR * FEC_PHYIDX */ @@ -91,7 +87,7 @@ static struct tsec_info_struct tsec_info[] = { { 0, 0, 0}, # endif # if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) - {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX}, + {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, # else { 0, 0, 0}, # endif @@ -805,6 +801,58 @@ struct phy_info phy_info_M88E1111S = { }, }; +static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) +{ + unsigned int temp; + uint mii_data = read_phy_reg(priv, mii_reg); + + + /* Setting MIIM_88E1145_PHY_EXT_CR */ + if (priv->flags & TSEC_REDUCED) + return mii_data | + MIIM_M88E1145_RGMII_RX_DELAY | + MIIM_M88E1145_RGMII_TX_DELAY; + else + return mii_data; +} + +static struct phy_info phy_info_M88E1145 = { + 0x01410cd, + "Marvell 88E1145", + 4, + (struct phy_cmd[]) { /* config */ + /* Errata E0, E1 */ + {29, 0x001b, NULL}, + {30, 0x418f, NULL}, + {29, 0x0016, NULL}, + {30, 0xa2da, NULL}, + + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL}, + {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL}, + /* Read the Status */ + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + + struct phy_info phy_info_cis8204 = { 0x3f11, "Cicada Cis8204", @@ -999,6 +1047,7 @@ struct phy_info *phy_info[] = { &phy_info_cis8204, &phy_info_M88E1011S, &phy_info_M88E1111S, + &phy_info_M88E1145, &phy_info_dm9161, &phy_info_lxt971, &phy_info_dp83865, diff --git a/drivers/tsec.h b/drivers/tsec.h index b55b2992b2..0bfca3a3df 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -142,6 +142,23 @@ #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 #define MIIM_88E1011_PHYSTAT_LINK 0x0400 +#define MIIM_88E1011_PHY_SCR 0x10 +#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 + +/* 88E1111 PHY LED Control Register */ +#define MIIM_88E1111_PHY_LED_CONTROL 24 +#define MIIM_88E1111_PHY_LED_DIRECT 0x4100 +#define MIIM_88E1111_PHY_LED_COMBINE 0x411C + +/* 88E1145 Extended PHY Specific Control Register */ +#define MIIM_88E1145_PHY_EXT_CR 20 +#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 +#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 + +#define MIIM_88E1145_PHY_PAGE 29 +#define MIIM_88E1145_PHY_CAL_OV 30 + + /* DM9161 Control register values */ #define MIIM_DM9161_CR_STOP 0x0400 #define MIIM_DM9161_CR_RSTAN 0x1200 -- cgit v1.2.1 From 89875e96ba3f023157bf50d5f8e33bf254964a76 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Oct 2006 17:03:43 -0500 Subject: Ran lindent and cleaned up whitespace issues. Format for 80-columns too. --- drivers/tsec.c | 896 +++++++++++++++++++++++++++++---------------------------- 1 file changed, 455 insertions(+), 441 deletions(-) (limited to 'drivers') diff --git a/drivers/tsec.c b/drivers/tsec.c index 0fb3ca229c..30dca11522 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -1,5 +1,4 @@ /* - * tsec.c * Freescale Three Speed Ethernet Controller driver * * This software may be used and distributed according to the @@ -28,13 +27,13 @@ DECLARE_GLOBAL_DATA_PTR; #define TX_BUF_CNT 2 -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ +static uint rxIdx; /* index of the current RX buffer */ +static uint txIdx; /* index of the current TX buffer */ typedef volatile struct rtxbd { txbd8_t txbd[TX_BUF_CNT]; rxbd8_t rxbd[PKTBUFSRX]; -} RTXBD; +} RTXBD; struct tsec_info_struct { unsigned int phyaddr; @@ -42,7 +41,6 @@ struct tsec_info_struct { unsigned int phyregidx; }; - /* The tsec_info structure contains 3 values which the * driver uses to determine how to operate a given ethernet * device. The information needed is: @@ -74,14 +72,14 @@ static struct tsec_info_struct tsec_info[] = { #elif defined(CONFIG_MPC86XX_TSEC1) {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, #else - { 0, 0, 0}, + {0, 0, 0}, #endif #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2) {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, #elif defined(CONFIG_MPC86XX_TSEC2) - {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX}, + {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX}, #else - { 0, 0, 0}, + {0, 0, 0}, #endif #ifdef CONFIG_MPC85XX_FEC {FEC_PHY_ADDR, 0, FEC_PHYIDX}, @@ -89,12 +87,12 @@ static struct tsec_info_struct tsec_info[] = { #if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3) {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX}, #else - { 0, 0, 0}, + {0, 0, 0}, #endif #if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4) {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, #else - { 0, 0, 0}, + {0, 0, 0}, #endif #endif }; @@ -111,68 +109,69 @@ static RTXBD rtx __attribute__ ((aligned(8))); #error "rtx must be 64-bit aligned" #endif -static int tsec_send(struct eth_device* dev, volatile void *packet, int length); -static int tsec_recv(struct eth_device* dev); -static int tsec_init(struct eth_device* dev, bd_t * bd); -static void tsec_halt(struct eth_device* dev); -static void init_registers(volatile tsec_t *regs); +static int tsec_send(struct eth_device *dev, + volatile void *packet, int length); +static int tsec_recv(struct eth_device *dev); +static int tsec_init(struct eth_device *dev, bd_t * bd); +static void tsec_halt(struct eth_device *dev); +static void init_registers(volatile tsec_t * regs); static void startup_tsec(struct eth_device *dev); static int init_phy(struct eth_device *dev); void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); uint read_phy_reg(struct tsec_private *priv, uint regnum); -struct phy_info * get_phy_info(struct eth_device *dev); +struct phy_info *get_phy_info(struct eth_device *dev); void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); static void adjust_link(struct eth_device *dev); static void relocate_cmds(void); static int tsec_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); + unsigned char reg, unsigned short value); static int tsec_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); + unsigned char reg, unsigned short *value); /* Initialize device structure. Returns success if PHY * initialization succeeded (i.e. if it recognizes the PHY) */ -int tsec_initialize(bd_t *bis, int index, char *devname) +int tsec_initialize(bd_t * bis, int index, char *devname) { - struct eth_device* dev; + struct eth_device *dev; int i; struct tsec_private *priv; - dev = (struct eth_device*) malloc(sizeof *dev); + dev = (struct eth_device *)malloc(sizeof *dev); - if(NULL == dev) + if (NULL == dev) return 0; memset(dev, 0, sizeof *dev); - priv = (struct tsec_private *) malloc(sizeof(*priv)); + priv = (struct tsec_private *)malloc(sizeof(*priv)); - if(NULL == priv) + if (NULL == priv) return 0; privlist[index] = priv; - priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index*TSEC_SIZE); + priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE); priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR + - tsec_info[index].phyregidx*TSEC_SIZE); + tsec_info[index].phyregidx * + TSEC_SIZE); priv->phyaddr = tsec_info[index].phyaddr; priv->flags = tsec_info[index].flags; sprintf(dev->name, devname); dev->iobase = 0; - dev->priv = priv; - dev->init = tsec_init; - dev->halt = tsec_halt; - dev->send = tsec_send; - dev->recv = tsec_recv; + dev->priv = priv; + dev->init = tsec_init; + dev->halt = tsec_halt; + dev->send = tsec_send; + dev->recv = tsec_recv; /* Tell u-boot to get the addr from the env */ - for(i=0;i<6;i++) + for (i = 0; i < 6; i++) dev->enetaddr[i] = 0; eth_register(dev); - /* Reset the MAC */ priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); @@ -186,12 +185,12 @@ int tsec_initialize(bd_t *bis, int index, char *devname) return init_phy(dev); } - /* Initializes data structures and registers for the controller, * and brings the interface up. Returns the link status, meaning * that it returns success if the link is up, failure otherwise. - * This allows u-boot to find the first active controller. */ -int tsec_init(struct eth_device* dev, bd_t * bd) + * This allows u-boot to find the first active controller. + */ +int tsec_init(struct eth_device *dev, bd_t * bd) { uint tempval; char tmpbuf[MAC_ADDR_LEN]; @@ -210,12 +209,12 @@ int tsec_init(struct eth_device* dev, bd_t * bd) /* Copy the station address into the address registers. * Backwards, because little endian MACS are dumb */ - for(i=0;ienetaddr[i]; } - regs->macstnaddr1 = *((uint *)(tmpbuf)); + regs->macstnaddr1 = *((uint *) (tmpbuf)); - tempval = *((uint *)(tmpbuf +4)); + tempval = *((uint *) (tmpbuf + 4)); regs->macstnaddr2 = tempval; @@ -234,7 +233,6 @@ int tsec_init(struct eth_device* dev, bd_t * bd) } - /* Write value to the device's PHY through the registers * specified in priv, modifying the register specified in regnum. * It will wait for the write to be done (or for a timeout to @@ -244,17 +242,16 @@ void write_phy_reg(struct tsec_private *priv, uint regnum, uint value) { volatile tsec_t *regbase = priv->phyregs; uint phyid = priv->phyaddr; - int timeout=1000000; + int timeout = 1000000; regbase->miimadd = (phyid << 8) | regnum; regbase->miimcon = value; asm("sync"); - timeout=1000000; - while((regbase->miimind & MIIMIND_BUSY) && timeout--); + timeout = 1000000; + while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; } - /* Reads register regnum on the device's PHY through the * registers specified in priv. It lowers and raises the read * command, and waits for the data to become valid (miimind @@ -280,7 +277,7 @@ uint read_phy_reg(struct tsec_private *priv, uint regnum) asm("sync"); /* Wait for the the indication that the read is done */ - while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))); + while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; /* Grab the value read from the PHY */ value = regbase->miimstat; @@ -288,7 +285,6 @@ uint read_phy_reg(struct tsec_private *priv, uint regnum) return value; } - /* Discover which PHY is attached to the device, and configure it * properly. If the PHY is not recognized, then return 0 * (failure). Otherwise, return 1 @@ -297,32 +293,29 @@ static int init_phy(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; struct phy_info *curphy; + volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR); /* Assign a Physical address to the TBI */ - - { - volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR); - regs->tbipa = TBIPA_VALUE; - regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE); - regs->tbipa = TBIPA_VALUE; - asm("sync"); - } + regs->tbipa = TBIPA_VALUE; + regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE); + regs->tbipa = TBIPA_VALUE; + asm("sync"); /* Reset MII (due to new addresses) */ priv->phyregs->miimcfg = MIIMCFG_RESET; asm("sync"); priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; asm("sync"); - while(priv->phyregs->miimind & MIIMIND_BUSY); + while (priv->phyregs->miimind & MIIMIND_BUSY) ; - if(0 == relocated) + if (0 == relocated) relocate_cmds(); /* Get the cmd structure corresponding to the attached * PHY */ curphy = get_phy_info(dev); - if(NULL == curphy) { + if (NULL == curphy) { printf("%s: No PHY found\n", dev->name); return 0; @@ -335,49 +328,53 @@ static int init_phy(struct eth_device *dev) return 1; } - -/* Returns which value to write to the control register. */ -/* For 10/100, the value is slightly different */ -uint mii_cr_init(uint mii_reg, struct tsec_private *priv) +/* + * Returns which value to write to the control register. + * For 10/100, the value is slightly different + */ +uint mii_cr_init(uint mii_reg, struct tsec_private * priv) { - if(priv->flags & TSEC_GIGABIT) + if (priv->flags & TSEC_GIGABIT) return MIIM_CONTROL_INIT; else return MIIM_CR_INIT; } - /* Parse the status register for link, and then do - * auto-negotiation */ -uint mii_parse_sr(uint mii_reg, struct tsec_private *priv) + * auto-negotiation + */ +uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) { /* - * Wait if PHY is capable of autonegotiation and autonegotiation is not complete + * Wait if PHY is capable of autonegotiation and autonegotiation + * is not complete. */ mii_reg = read_phy_reg(priv, MIIM_STATUS); - if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) { + if ((mii_reg & PHY_BMSR_AUTN_ABLE) + && !(mii_reg & PHY_BMSR_AUTN_COMP)) { int i = 0; - puts ("Waiting for PHY auto negotiation to complete"); - while (!((mii_reg & PHY_BMSR_AUTN_COMP) && (mii_reg & MIIM_STATUS_LINK))) { + puts("Waiting for PHY auto negotiation to complete"); + while (!((mii_reg & PHY_BMSR_AUTN_COMP) + && (mii_reg & MIIM_STATUS_LINK))) { /* * Timeout reached ? */ if (i > PHY_AUTONEGOTIATE_TIMEOUT) { - puts (" TIMEOUT !\n"); + puts(" TIMEOUT !\n"); priv->link = 0; return 0; } if ((i++ % 1000) == 0) { - putc ('.'); + putc('.'); } - udelay (1000); /* 1 ms */ + udelay(1000); /* 1 ms */ mii_reg = read_phy_reg(priv, MIIM_STATUS); } - puts (" done\n"); + puts(" done\n"); priv->link = 1; - udelay (500000); /* another 500 ms (results in faster booting) */ + udelay(500000); /* another 500 ms (results in faster booting) */ } else { priv->link = 1; } @@ -385,10 +382,10 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private *priv) return 0; } - /* Parse the 88E1011's status register for speed and duplex - * information */ -uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv) + * information + */ +uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) { uint speed; @@ -398,114 +395,116 @@ uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv) (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { int i = 0; - puts ("Waiting for PHY realtime link"); + puts("Waiting for PHY realtime link"); while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) && (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { /* * Timeout reached ? */ if (i > PHY_AUTONEGOTIATE_TIMEOUT) { - puts (" TIMEOUT !\n"); + puts(" TIMEOUT !\n"); priv->link = 0; break; } if ((i++ % 1000) == 0) { - putc ('.'); + putc('.'); } - udelay (1000); /* 1 ms */ + udelay(1000); /* 1 ms */ mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); } - puts (" done\n"); - udelay (500000); /* another 500 ms (results in faster booting) */ + puts(" done\n"); + udelay(500000); /* another 500 ms (results in faster booting) */ } - if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) + if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) priv->duplexity = 1; else priv->duplexity = 0; - speed = (mii_reg &MIIM_88E1011_PHYSTAT_SPEED); + speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); - switch(speed) { - case MIIM_88E1011_PHYSTAT_GBIT: - priv->speed = 1000; - break; - case MIIM_88E1011_PHYSTAT_100: - priv->speed = 100; - break; - default: - priv->speed = 10; + switch (speed) { + case MIIM_88E1011_PHYSTAT_GBIT: + priv->speed = 1000; + break; + case MIIM_88E1011_PHYSTAT_100: + priv->speed = 100; + break; + default: + priv->speed = 10; } return 0; } - /* Parse the cis8201's status register for speed and duplex - * information */ -uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv) + * information + */ +uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) { uint speed; - if(mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) + if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) priv->duplexity = 1; else priv->duplexity = 0; speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; - switch(speed) { - case MIIM_CIS8201_AUXCONSTAT_GBIT: - priv->speed = 1000; - break; - case MIIM_CIS8201_AUXCONSTAT_100: - priv->speed = 100; - break; - default: - priv->speed = 10; - break; + switch (speed) { + case MIIM_CIS8201_AUXCONSTAT_GBIT: + priv->speed = 1000; + break; + case MIIM_CIS8201_AUXCONSTAT_100: + priv->speed = 100; + break; + default: + priv->speed = 10; + break; } return 0; } + /* Parse the vsc8244's status register for speed and duplex - * information */ -uint mii_parse_vsc8244(uint mii_reg, struct tsec_private *priv) + * information + */ +uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) { - uint speed; - - if(mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) - priv->duplexity = 1; - else - priv->duplexity = 0; - - speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; - switch(speed) { - case MIIM_VSC8244_AUXCONSTAT_GBIT: - priv->speed = 1000; - break; - case MIIM_VSC8244_AUXCONSTAT_100: - priv->speed = 100; - break; - default: - priv->speed = 10; - break; - } - - return 0; -} + uint speed; + if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) + priv->duplexity = 1; + else + priv->duplexity = 0; + + speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; + switch (speed) { + case MIIM_VSC8244_AUXCONSTAT_GBIT: + priv->speed = 1000; + break; + case MIIM_VSC8244_AUXCONSTAT_100: + priv->speed = 100; + break; + default: + priv->speed = 10; + break; + } + + return 0; +} /* Parse the DM9161's status register for speed and duplex - * information */ -uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv) + * information + */ +uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) { - if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) + if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) priv->speed = 100; else priv->speed = 10; - if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) + if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) priv->duplexity = 1; else priv->duplexity = 0; @@ -513,27 +512,28 @@ uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv) return 0; } - -/* Hack to write all 4 PHYs with the LED values */ -uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv) +/* + * Hack to write all 4 PHYs with the LED values + */ +uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) { uint phyid; volatile tsec_t *regbase = priv->phyregs; - int timeout=1000000; + int timeout = 1000000; - for(phyid=0;phyid<4;phyid++) { + for (phyid = 0; phyid < 4; phyid++) { regbase->miimadd = (phyid << 8) | mii_reg; regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; asm("sync"); - timeout=1000000; - while((regbase->miimind & MIIMIND_BUSY) && timeout--); + timeout = 1000000; + while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; } return MIIM_CIS8204_SLEDCON_INIT; } -uint mii_cis8204_setmode(uint mii_reg, struct tsec_private *priv) +uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) { if (priv->flags & TSEC_REDUCED) return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; @@ -543,8 +543,9 @@ uint mii_cis8204_setmode(uint mii_reg, struct tsec_private *priv) /* Initialized required registers to appropriate values, zeroing * those we don't care about (unless zero is bad, in which case, - * choose a more appropriate value) */ -static void init_registers(volatile tsec_t *regs) + * choose a more appropriate value) + */ +static void init_registers(volatile tsec_t * regs) { /* Clear IEVENT */ regs->ievent = IEVENT_INIT_CLEAR; @@ -586,55 +587,55 @@ static void init_registers(volatile tsec_t *regs) } - /* Configure maccfg2 based on negotiated speed and duplex - * reported by PHY handling code */ + * reported by PHY handling code + */ static void adjust_link(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; volatile tsec_t *regs = priv->regs; - if(priv->link) { - if(priv->duplexity != 0) + if (priv->link) { + if (priv->duplexity != 0) regs->maccfg2 |= MACCFG2_FULL_DUPLEX; else regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); - switch(priv->speed) { - case 1000: - regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) - | MACCFG2_GMII); - break; - case 100: - case 10: - regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) - | MACCFG2_MII); - - /* If We're in reduced mode, we need - * to say whether we're 10 or 100 MB. - */ - if ((priv->speed == 100) - && (priv->flags & TSEC_REDUCED)) - regs->ecntrl |= ECNTRL_R100; - else - regs->ecntrl &= ~(ECNTRL_R100); - break; - default: - printf("%s: Speed was bad\n", dev->name); - break; + switch (priv->speed) { + case 1000: + regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) + | MACCFG2_GMII); + break; + case 100: + case 10: + regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) + | MACCFG2_MII); + + /* If We're in reduced mode, we need + * to say whether we're 10 or 100 MB. + */ + if ((priv->speed == 100) + && (priv->flags & TSEC_REDUCED)) + regs->ecntrl |= ECNTRL_R100; + else + regs->ecntrl &= ~(ECNTRL_R100); + break; + default: + printf("%s: Speed was bad\n", dev->name); + break; } printf("Speed: %d, %s duplex\n", priv->speed, - (priv->duplexity) ? "full" : "half"); + (priv->duplexity) ? "full" : "half"); } else { printf("%s: No link.\n", dev->name); } } - /* Set up the buffers and their descriptors, and bring up the - * interface */ + * interface + */ static void startup_tsec(struct eth_device *dev) { int i; @@ -649,17 +650,17 @@ static void startup_tsec(struct eth_device *dev) for (i = 0; i < PKTBUFSRX; i++) { rtx.rxbd[i].status = RXBD_EMPTY; rtx.rxbd[i].length = 0; - rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i]; + rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; } - rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP; + rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; /* Initialize the TX Buffer Descriptors */ - for(i=0; iphyinfo->startup); @@ -677,8 +678,9 @@ static void startup_tsec(struct eth_device *dev) /* This returns the status bits of the device. The return value * is never checked, and this is what the 8260 driver did, so we * do the same. Presumably, this would be zero if there were no - * errors */ -static int tsec_send(struct eth_device* dev, volatile void *packet, int length) + * errors + */ +static int tsec_send(struct eth_device *dev, volatile void *packet, int length) { int i; int result = 0; @@ -686,24 +688,25 @@ static int tsec_send(struct eth_device* dev, volatile void *packet, int length) volatile tsec_t *regs = priv->regs; /* Find an empty buffer descriptor */ - for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) { + for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { if (i >= TOUT_LOOP) { - debug ("%s: tsec: tx buffers full\n", dev->name); + debug("%s: tsec: tx buffers full\n", dev->name); return result; } } - rtx.txbd[txIdx].bufPtr = (uint)packet; + rtx.txbd[txIdx].bufPtr = (uint) packet; rtx.txbd[txIdx].length = length; - rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); + rtx.txbd[txIdx].status |= + (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); /* Tell the DMA to go */ regs->tstat = TSTAT_CLEAR_THALT; /* Wait for buffer to be transmitted */ - for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) { + for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { if (i >= TOUT_LOOP) { - debug ("%s: tsec: tx error\n", dev->name); + debug("%s: tsec: tx error\n", dev->name); return result; } } @@ -714,13 +717,13 @@ static int tsec_send(struct eth_device* dev, volatile void *packet, int length) return result; } -static int tsec_recv(struct eth_device* dev) +static int tsec_recv(struct eth_device *dev) { int length; struct tsec_private *priv = (struct tsec_private *)dev->priv; volatile tsec_t *regs = priv->regs; - while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { + while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { length = rtx.rxbd[rxIdx].length; @@ -729,18 +732,19 @@ static int tsec_recv(struct eth_device* dev) NetReceive(NetRxPackets[rxIdx], length - 4); } else { printf("Got error %x\n", - (rtx.rxbd[rxIdx].status & RXBD_STATS)); + (rtx.rxbd[rxIdx].status & RXBD_STATS)); } rtx.rxbd[rxIdx].length = 0; /* Set the wrap bit if this is the last element in the list */ - rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); + rtx.rxbd[rxIdx].status = + RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); rxIdx = (rxIdx + 1) % PKTBUFSRX; } - if(regs->ievent&IEVENT_BSY) { + if (regs->ievent & IEVENT_BSY) { regs->ievent = IEVENT_BSY; regs->rstat = RSTAT_CLEAR_RHALT; } @@ -749,9 +753,8 @@ static int tsec_recv(struct eth_device* dev) } - /* Stop the interface */ -static void tsec_halt(struct eth_device* dev) +static void tsec_halt(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; volatile tsec_t *regs = priv->regs; @@ -759,7 +762,7 @@ static void tsec_halt(struct eth_device* dev) regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); - while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))); + while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); @@ -767,69 +770,70 @@ static void tsec_halt(struct eth_device* dev) phy_run_commands(priv, priv->phyinfo->shutdown); } - struct phy_info phy_info_M88E1011S = { 0x01410c6, "Marvell 88E1011S", 4, - (struct phy_cmd[]) { /* config */ - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {0x1d, 0x1f, NULL}, - {0x1e, 0x200c, NULL}, - {0x1d, 0x5, NULL}, - {0x1e, 0x0, NULL}, - {0x1e, 0x100, NULL}, - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]){ /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1d, 0x1f, NULL}, + {0x1e, 0x200c, NULL}, + {0x1d, 0x5, NULL}, + {0x1e, 0x0, NULL}, + {0x1e, 0x100, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, + &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; struct phy_info phy_info_M88E1111S = { 0x01410cc, "Marvell 88E1111S", 4, - (struct phy_cmd[]) { /* config */ - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {0x1d, 0x1f, NULL}, - {0x1e, 0x200c, NULL}, - {0x1d, 0x5, NULL}, - {0x1e, 0x0, NULL}, - {0x1e, 0x100, NULL}, - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]){ /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1d, 0x1f, NULL}, + {0x1e, 0x200c, NULL}, + {0x1d, 0x5, NULL}, + {0x1e, 0x0, NULL}, + {0x1e, 0x100, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, + &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) @@ -837,12 +841,10 @@ static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) unsigned int temp; uint mii_data = read_phy_reg(priv, mii_reg); - /* Setting MIIM_88E1145_PHY_EXT_CR */ if (priv->flags & TSEC_REDUCED) return mii_data | - MIIM_M88E1145_RGMII_RX_DELAY | - MIIM_M88E1145_RGMII_TX_DELAY; + MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; else return mii_data; } @@ -851,64 +853,70 @@ static struct phy_info phy_info_M88E1145 = { 0x01410cd, "Marvell 88E1145", 4, - (struct phy_cmd[]) { /* config */ - /* Errata E0, E1 */ - {29, 0x001b, NULL}, - {30, 0x418f, NULL}, - {29, 0x0016, NULL}, - {30, 0xa2da, NULL}, - - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL}, - {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL}, - /* Read the Status */ - {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]){ /* config */ + /* Errata E0, E1 */ + {29, 0x001b, NULL}, + {30, 0x418f, NULL}, + {29, 0x0016, NULL}, + {30, 0xa2da, NULL}, + + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, + NULL}, + {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + {MIIM_88E1111_PHY_LED_CONTROL, + MIIM_88E1111_PHY_LED_DIRECT, NULL}, + /* Read the Status */ + {MIIM_88E1011_PHY_STATUS, miim_read, + &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; - struct phy_info phy_info_cis8204 = { 0x3f11, "Cicada Cis8204", 6, - (struct phy_cmd[]) { /* config */ - /* Override PHY config settings */ - {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled}, - {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, &mii_cis8204_setmode}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]){ /* config */ + /* Override PHY config settings */ + {MIIM_CIS8201_AUX_CONSTAT, + MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, + &mii_cis8204_fixled}, + {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, + &mii_cis8204_setmode}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_CIS8201_AUX_CONSTAT, miim_read, + &mii_parse_cis8201}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; /* Cicada 8201 */ @@ -916,81 +924,86 @@ struct phy_info phy_info_cis8201 = { 0xfc41, "CIS8201", 4, - (struct phy_cmd[]) { /* config */ - /* Override PHY config settings */ - {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, - /* Set up the interface mode */ - {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]){ /* config */ + /* Override PHY config settings */ + {MIIM_CIS8201_AUX_CONSTAT, + MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, + /* Set up the interface mode */ + {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, + NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_CIS8201_AUX_CONSTAT, miim_read, + &mii_parse_cis8201}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; struct phy_info phy_info_VSC8244 = { - 0x3f1b, - "Vitesse VSC8244", - 6, - (struct phy_cmd[]) { /* config */ - /* Override PHY config settings */ - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + 0x3f1b, + "Vitesse VSC8244", + 6, + (struct phy_cmd[]){ /* config */ + /* Override PHY config settings */ + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_VSC8244_AUX_CONSTAT, miim_read, + &mii_parse_vsc8244}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; - struct phy_info phy_info_dm9161 = { 0x0181b88, "Davicom DM9161E", 4, - (struct phy_cmd[]) { /* config */ - {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, - /* Do not bypass the scrambler/descrambler */ - {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, - /* Clear 10BTCSR to default */ - {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL}, - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CR_INIT, NULL}, - /* Restart Auto Negotiation */ - {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]){ /* config */ + {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, + /* Do not bypass the scrambler/descrambler */ + {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, + /* Clear 10BTCSR to default */ + {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, + NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CR_INIT, NULL}, + /* Restart Auto Negotiation */ + {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_DM9161_SCSR, miim_read, + &mii_parse_dm9161_scsr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) @@ -1028,24 +1041,25 @@ static struct phy_info phy_info_lxt971 = { 0x0001378e, "LXT971", 4, - (struct phy_cmd []) { /* config */ - { MIIM_CR, MIIM_CR_INIT, mii_cr_init }, /* autonegotiate */ - { miim_end, } - }, - (struct phy_cmd []) { /* startup - enable interrupts */ - /* { 0x12, 0x00f2, NULL }, */ - { MIIM_STATUS, miim_read, NULL }, - { MIIM_STATUS, miim_read, &mii_parse_sr }, - { MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2 }, - { miim_end, } - }, - (struct phy_cmd []) { /* shutdown - disable interrupts */ - { miim_end, } - }, + (struct phy_cmd[]){ /* config */ + {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ + {miim_end,} + }, + (struct phy_cmd[]){ /* startup - enable interrupts */ + /* { 0x12, 0x00f2, NULL }, */ + {MIIM_STATUS, miim_read, NULL}, + {MIIM_STATUS, miim_read, &mii_parse_sr}, + {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown - disable interrupts */ + {miim_end,} + }, }; /* Parse the DP83865's link and auto-neg status register for speed and duplex - * information */ + * information + */ uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) { switch (mii_reg & MIIM_DP83865_SPD_MASK) { @@ -1076,22 +1090,23 @@ struct phy_info phy_info_dp83865 = { 0x20005c7, "NatSemi DP83865", 4, - (struct phy_cmd[]) { /* config */ - {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the link and auto-neg status */ - {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]){ /* config */ + {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the link and auto-neg status */ + {MIIM_DP83865_LANR, miim_read, + &mii_parse_dp83865_lanr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; struct phy_info *phy_info[] = { @@ -1109,11 +1124,11 @@ struct phy_info *phy_info[] = { NULL }; - /* Grab the identifier of the device's PHY, and search through * all of the known PHYs to see if one matches. If so, return - * it, if not, return NULL */ -struct phy_info * get_phy_info(struct eth_device *dev) + * it, if not, return NULL + */ +struct phy_info *get_phy_info(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; uint phy_reg, phy_ID; @@ -1130,13 +1145,12 @@ struct phy_info * get_phy_info(struct eth_device *dev) /* loop through all the known PHY types, and find one that */ /* matches the ID we read from the PHY. */ - for(i=0; phy_info[i]; i++) { - if(phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) + for (i = 0; phy_info[i]; i++) { + if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) theInfo = phy_info[i]; } - if(theInfo == NULL) - { + if (theInfo == NULL) { printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID); return NULL; } else { @@ -1146,9 +1160,9 @@ struct phy_info * get_phy_info(struct eth_device *dev) return theInfo; } - /* Execute the given series of commands on the given device's - * PHY, running functions as necessary*/ + * PHY, running functions as necessary + */ void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) { int i; @@ -1159,18 +1173,18 @@ void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) phyregs->miimcfg = MIIMCFG_INIT_VALUE; - while(phyregs->miimind & MIIMIND_BUSY); + while (phyregs->miimind & MIIMIND_BUSY) ; - for(i=0;cmd->mii_reg != miim_end;i++) { - if(cmd->mii_data == miim_read) { + for (i = 0; cmd->mii_reg != miim_end; i++) { + if (cmd->mii_data == miim_read) { result = read_phy_reg(priv, cmd->mii_reg); - if(cmd->funct != NULL) - (*(cmd->funct))(result, priv); + if (cmd->funct != NULL) + (*(cmd->funct)) (result, priv); } else { - if(cmd->funct != NULL) - result = (*(cmd->funct))(cmd->mii_reg, priv); + if (cmd->funct != NULL) + result = (*(cmd->funct)) (cmd->mii_reg, priv); else result = cmd->mii_data; @@ -1181,37 +1195,38 @@ void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) } } - /* Relocate the function pointers in the phy cmd lists */ static void relocate_cmds(void) { struct phy_cmd **cmdlistptr; struct phy_cmd *cmd; - int i,j,k; + int i, j, k; - for(i=0; phy_info[i]; i++) { + for (i = 0; phy_info[i]; i++) { /* First thing's first: relocate the pointers to the * PHY command structures (the structs were done) */ - phy_info[i] = (struct phy_info *) ((uint)phy_info[i] - + gd->reloc_off); + phy_info[i] = (struct phy_info *)((uint) phy_info[i] + + gd->reloc_off); phy_info[i]->name += gd->reloc_off; phy_info[i]->config = - (struct phy_cmd *)((uint)phy_info[i]->config - + gd->reloc_off); + (struct phy_cmd *)((uint) phy_info[i]->config + + gd->reloc_off); phy_info[i]->startup = - (struct phy_cmd *)((uint)phy_info[i]->startup - + gd->reloc_off); + (struct phy_cmd *)((uint) phy_info[i]->startup + + gd->reloc_off); phy_info[i]->shutdown = - (struct phy_cmd *)((uint)phy_info[i]->shutdown - + gd->reloc_off); + (struct phy_cmd *)((uint) phy_info[i]->shutdown + + gd->reloc_off); cmdlistptr = &phy_info[i]->config; - j=0; - for(;cmdlistptr <= &phy_info[i]->shutdown;cmdlistptr++) { - k=0; - for(cmd=*cmdlistptr;cmd->mii_reg != miim_end;cmd++) { + j = 0; + for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) { + k = 0; + for (cmd = *cmdlistptr; + cmd->mii_reg != miim_end; + cmd++) { /* Only relocate non-NULL pointers */ - if(cmd->funct) + if (cmd->funct) cmd->funct += gd->reloc_off; k++; @@ -1223,16 +1238,15 @@ static void relocate_cmds(void) relocated = 1; } - #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \ && !defined(BITBANGMII) -struct tsec_private * get_priv_for_phy(unsigned char phyaddr) +struct tsec_private *get_priv_for_phy(unsigned char phyaddr) { int i; - for(i=0;iphyaddr == phyaddr) + for (i = 0; i < MAXCONTROLLERS; i++) { + if (privlist[i]->phyaddr == phyaddr) return privlist[i]; } @@ -1246,12 +1260,12 @@ struct tsec_private * get_priv_for_phy(unsigned char phyaddr) * 0 on success */ static int tsec_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) + unsigned char reg, unsigned short *value) { unsigned short ret; struct tsec_private *priv = get_priv_for_phy(addr); - if(NULL == priv) { + if (NULL == priv) { printf("Can't read PHY at address %d\n", addr); return -1; } @@ -1269,11 +1283,11 @@ static int tsec_miiphy_read(char *devname, unsigned char addr, * 0 on success */ static int tsec_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value) + unsigned char reg, unsigned short value) { struct tsec_private *priv = get_priv_for_phy(addr); - if(NULL == priv) { + if (NULL == priv) { printf("Can't write PHY at address %d\n", addr); return -1; } -- cgit v1.2.1 From 0ee90cb77e01d6e8ccd37e1bd96678597875c391 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 12 Oct 2006 10:42:36 -0500 Subject: Remove unneeded include files and local variable. Signed-off-by: Jon Loeliger --- drivers/tsec.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers') diff --git a/drivers/tsec.c b/drivers/tsec.c index 30dca11522..770517b87e 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -12,8 +12,6 @@ */ #include -#include -#include #include #include #include @@ -838,7 +836,6 @@ struct phy_info phy_info_M88E1111S = { static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) { - unsigned int temp; uint mii_data = read_phy_reg(priv, mii_reg); /* Setting MIIM_88E1145_PHY_EXT_CR */ -- cgit v1.2.1 From 7237c033b02fe295880435f1eb80819a0c987532 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 19 Oct 2006 11:02:16 -0500 Subject: Moved i2c driver out of cpu/mpc86xx/i2c.c into drivers/fsl_i2c.c in an effort to begin to unify the umpteen FSL I2C drivers that are all otherwise very similar. Signed-off-by: Jon Loeliger --- drivers/Makefile | 3 +- drivers/fsl_i2c.c | 247 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 249 insertions(+), 1 deletion(-) create mode 100644 drivers/fsl_i2c.c (limited to 'drivers') diff --git a/drivers/Makefile b/drivers/Makefile index 0f84969a99..b191018c72 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -50,7 +50,8 @@ COBJS = 3c589.o 5701rls.o ali512x.o \ videomodes.o w83c553f.o \ ks8695eth.o \ pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ - rpx_pcmcia.o + rpx_pcmcia.o \ + fsl_i2c.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/fsl_i2c.c b/drivers/fsl_i2c.c new file mode 100644 index 0000000000..72b2556b28 --- /dev/null +++ b/drivers/fsl_i2c.c @@ -0,0 +1,247 @@ +/* + * Copyright 2006 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +#ifdef CONFIG_HARD_I2C + +#include +#include + +#define I2C_TIMEOUT (CFG_HZ / 4) + +#define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET)) + + +void +i2c_init(int speed, int slaveadd) +{ + /* stop I2C controller */ + writeb(0x0 , &I2C->cr); + + /* set clock */ + writeb(0x3f, &I2C->fdr); + + /* set default filter */ + writeb(0x10, &I2C->dfsrr); + + /* write slave address */ + writeb(slaveadd, &I2C->adr); + + /* clear status register */ + writeb(0x0, &I2C->sr); + + /* start I2C controller */ + writeb(I2C_CR_MEN, &I2C->cr); +} + +static __inline__ int +i2c_wait4bus(void) +{ + ulong timeval = get_timer (0); + + while (readb(&I2C->sr) & I2C_SR_MBB) { + if (get_timer(timeval) > I2C_TIMEOUT) { + return -1; + } + } + + return 0; +} + +static __inline__ int +i2c_wait(int write) +{ + u32 csr; + ulong timeval = get_timer(0); + + do { + csr = readb(&I2C->sr); + if (!(csr & I2C_SR_MIF)) + continue; + + writeb(0x0, &I2C->sr); + + if (csr & I2C_SR_MAL) { + debug("i2c_wait: MAL\n"); + return -1; + } + + if (!(csr & I2C_SR_MCF)) { + debug("i2c_wait: unfinished\n"); + return -1; + } + + if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) { + debug("i2c_wait: No RXACK\n"); + return -1; + } + + return 0; + } while (get_timer (timeval) < I2C_TIMEOUT); + + debug("i2c_wait: timed out\n"); + return -1; +} + +static __inline__ int +i2c_write_addr (u8 dev, u8 dir, int rsta) +{ + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX + | (rsta ? I2C_CR_RSTA : 0), + &I2C->cr); + + writeb((dev << 1) | dir, &I2C->dr); + + if (i2c_wait(I2C_WRITE) < 0) + return 0; + + return 1; +} + +static __inline__ int +__i2c_write(u8 *data, int length) +{ + int i; + + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, + &I2C->cr); + + for (i = 0; i < length; i++) { + writeb(data[i], &I2C->dr); + + if (i2c_wait(I2C_WRITE) < 0) + break; + } + + return i; +} + +static __inline__ int +__i2c_read(u8 *data, int length) +{ + int i; + + writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), + &I2C->cr); + + /* dummy read */ + readb(&I2C->dr); + + for (i = 0; i < length; i++) { + if (i2c_wait(I2C_READ) < 0) + break; + + /* Generate ack on last next to last byte */ + if (i == length - 2) + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, + &I2C->cr); + + /* Generate stop on last byte */ + if (i == length - 1) + writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr); + + data[i] = readb(&I2C->dr); + } + + return i; +} + +int +i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8*)&addr; + + if (i2c_wait4bus () < 0) + goto exit; + + if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write(&a[4 - alen], alen) != alen) + goto exit; + + if (i2c_write_addr(dev, I2C_READ, 1) == 0) + goto exit; + + i = __i2c_read(data, length); + + exit: + writeb(I2C_CR_MEN, &I2C->cr); + + return !(i == length); +} + +int +i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8*)&addr; + + if (i2c_wait4bus() < 0) + goto exit; + + if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write(&a[4 - alen], alen) != alen) + goto exit; + + i = __i2c_write(data, length); + + exit: + writeb(I2C_CR_MEN, &I2C->cr); + + return !(i == length); +} + +int +i2c_probe(uchar chip) +{ + int tmp; + + /* + * Try to read the first location of the chip. The underlying + * driver doesn't appear to support sending just the chip address + * and looking for an back. + */ + udelay(10000); + + return i2c_read(chip, 0, 1, (uchar *)&tmp, 1); +} + +uchar +i2c_reg_read(uchar i2c_addr, uchar reg) +{ + uchar buf[1]; + + i2c_read(i2c_addr, reg, 1, buf, 1); + + return buf[0]; +} + +void +i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) +{ + i2c_write(i2c_addr, reg, 1, &val, 1); +} + +#endif /* CONFIG_HARD_I2C */ -- cgit v1.2.1 From 4d45f69e362b05892c9e92a7907e5820995612aa Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 19 Oct 2006 12:02:24 -0500 Subject: Rewrite a series of goto statements as a sequences of conditional expressions instead. Use consistent return code 0/-1 for good/bad indicators. Include one fewer file if the driver isn't used at all. Signed-off-by: Jon Loeliger --- drivers/fsl_i2c.c | 52 +++++++++++++++++++++------------------------------- 1 file changed, 21 insertions(+), 31 deletions(-) (limited to 'drivers') diff --git a/drivers/fsl_i2c.c b/drivers/fsl_i2c.c index 72b2556b28..af191915e3 100644 --- a/drivers/fsl_i2c.c +++ b/drivers/fsl_i2c.c @@ -16,18 +16,16 @@ * MA 02111-1307 USA */ - #include -#include #ifdef CONFIG_HARD_I2C +#include #include #include #define I2C_TIMEOUT (CFG_HZ / 4) - -#define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET)) +#define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET)) void @@ -170,24 +168,19 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) int i = 0; u8 *a = (u8*)&addr; - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write(&a[4 - alen], alen) != alen) - goto exit; - - if (i2c_write_addr(dev, I2C_READ, 1) == 0) - goto exit; - - i = __i2c_read(data, length); + if (i2c_wait4bus() >= 0 + && i2c_write_addr(dev, I2C_WRITE, 0) != 0 + && __i2c_write(&a[4 - alen], alen) == alen + && i2c_write_addr(dev, I2C_READ, 1) != 0) { + i = __i2c_read(data, length); + } - exit: writeb(I2C_CR_MEN, &I2C->cr); - return !(i == length); + if (i == length) + return 0; + + return -1; } int @@ -196,21 +189,18 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) int i = 0; u8 *a = (u8*)&addr; - if (i2c_wait4bus() < 0) - goto exit; - - if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write(&a[4 - alen], alen) != alen) - goto exit; - - i = __i2c_write(data, length); + if (i2c_wait4bus() >= 0 + && i2c_write_addr(dev, I2C_WRITE, 0) != 0 + && __i2c_write(&a[4 - alen], alen) == alen) { + i = __i2c_write(data, length); + } - exit: writeb(I2C_CR_MEN, &I2C->cr); - return !(i == length); + if (i == length) + return 0; + + return -1; } int -- cgit v1.2.1 From 2047672684cf85cb6f96a1fbc993180aaaf19a99 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 20 Oct 2006 15:50:15 -0500 Subject: Converted all 85xx boards to use a common FSL I2C driver. Introduced COFIG_FSL_I2C to select the common FSL I2C driver. And removed hard i2c path from a few u-boot.lds scipts too. Minor whitespace cleanups along the way. Signed-off-by: Jon Loeliger --- drivers/fsl_i2c.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/fsl_i2c.c b/drivers/fsl_i2c.c index af191915e3..65c27439e3 100644 --- a/drivers/fsl_i2c.c +++ b/drivers/fsl_i2c.c @@ -18,11 +18,14 @@ #include +#ifdef CONFIG_FSL_I2C #ifdef CONFIG_HARD_I2C #include +#include /* Functional interface */ + #include -#include +#include /* HW definitions */ #define I2C_TIMEOUT (CFG_HZ / 4) #define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET)) @@ -32,7 +35,7 @@ void i2c_init(int speed, int slaveadd) { /* stop I2C controller */ - writeb(0x0 , &I2C->cr); + writeb(0x0, &I2C->cr); /* set clock */ writeb(0x3f, &I2C->fdr); @@ -53,7 +56,7 @@ i2c_init(int speed, int slaveadd) static __inline__ int i2c_wait4bus(void) { - ulong timeval = get_timer (0); + ulong timeval = get_timer(0); while (readb(&I2C->sr) & I2C_SR_MBB) { if (get_timer(timeval) > I2C_TIMEOUT) { @@ -235,3 +238,4 @@ i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) } #endif /* CONFIG_HARD_I2C */ +#endif /* CONFIG_FSL_I2C */ -- cgit v1.2.1