From 2cb4fade0ef00ebf485db05d6aab4acd8897ecf9 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Mon, 21 Nov 2011 19:25:46 +0530 Subject: mvsata: fix ide_preinit for missing disks Consider that ide_preinit() succeed if at least one port is successfully initialized. This allows to iniatialize IDE support on a board with two SATA ports but a single hard disk available. Signed-off-by: Simon Guinot --- drivers/block/mvsata_ide.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index 1be395fb45..a88d0f7f83 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -150,23 +150,25 @@ static int mvsata_ide_initialize_port(struct mvsata_port_registers *port) int ide_preinit(void) { + int ret = MVSATA_STATUS_TIMEOUT; int status; + /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE0_OFFSET) status = mvsata_ide_initialize_port( (struct mvsata_port_registers *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET)); - if (status) - return status; + if (status == MVSATA_STATUS_OK) + ret = MVSATA_STATUS_OK; #endif /* Enable ATA port 1 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE1_OFFSET) status = mvsata_ide_initialize_port( (struct mvsata_port_registers *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET)); - if (status) - return status; + if (status == MVSATA_STATUS_OK) + ret = MVSATA_STATUS_OK; #endif - /* return success if all ports initializations succeeded */ - return MVSATA_STATUS_OK; + /* Return success if at least one port initialization succeeded */ + return ret; } -- cgit v1.2.1 From 28cb465f78027c2e7eb6678a61bf5c71e6b2cdeb Mon Sep 17 00:00:00 2001 From: Ajay Bhargav Date: Mon, 31 Oct 2011 01:19:37 +0000 Subject: net: Armada100: Fix compilation warnings This patch fix compilation warnings for Armada100 FEC driver Ref: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Ajay Bhargav Acked-by: Anatolij Gustschin --- drivers/net/armada100_fec.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c index fbf97632c6..1a54362e0b 100644 --- a/drivers/net/armada100_fec.c +++ b/drivers/net/armada100_fec.c @@ -440,6 +440,7 @@ static int armdfec_init(struct eth_device *dev, bd_t *bd) struct armdfec_device *darmdfec = to_darmdfec(dev); struct armdfec_reg *regs = darmdfec->regs; int phy_adr; + u32 temp; armdfec_init_rx_desc_ring(darmdfec); @@ -479,9 +480,12 @@ static int armdfec_init(struct eth_device *dev, bd_t *bd) update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr); /* Update TX and RX queue descriptor register */ - writel((u32)darmdfec->p_txdesc, ®s->txcdp[TXQ]); - writel((u32)darmdfec->p_rxdesc, ®s->rxfdp[RXQ]); - writel((u32)darmdfec->p_rxdesc_curr, ®s->rxcdp[RXQ]); + temp = (u32)®s->txcdp[TXQ]; + writel((u32)darmdfec->p_txdesc, temp); + temp = (u32)®s->rxfdp[RXQ]; + writel((u32)darmdfec->p_rxdesc, temp); + temp = (u32)®s->rxcdp[RXQ]; + writel((u32)darmdfec->p_rxdesc_curr, temp); /* Enable Interrupts */ writel(ALL_INTS, ®s->im); @@ -614,6 +618,7 @@ static int armdfec_recv(struct eth_device *dev) struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr; u32 cmd_sts; u32 timeout = 0; + u32 temp; /* wait untill rx packet available or timeout */ do { @@ -667,7 +672,8 @@ static int armdfec_recv(struct eth_device *dev) p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; p_rxdesc_curr->byte_cnt = 0; - writel((u32)p_rxdesc_curr->nxtdesc_p, (u32)&darmdfec->p_rxdesc_curr); + temp = (u32)&darmdfec->p_rxdesc_curr; + writel((u32)p_rxdesc_curr->nxtdesc_p, temp); return 0; } -- cgit v1.2.1 From 82645f816fe25b8ff1cda8cf509dfb4f3059c975 Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Mon, 31 Oct 2011 06:34:44 +0000 Subject: nand: Add common functions to linux/mtd/nand.h Functions often used in SPL are now part of linux/mtd/nand.h. Static modifiers are removed from these functions in drivers/mtd/nand/nand_base.c. Signed-off-by: Simon Schwarz Cc: scottwood@freescale.com Cc: s-paulraj@ti.com Cc: albert.u.boot@aribaud.net Acked-by: Scott Wood --- drivers/mtd/nand/nand_base.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 6aac6a2bf4..27f6c776b0 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -133,7 +133,7 @@ static void nand_release_device (struct mtd_info *mtd) * * Default read function for 8bit buswith */ -static uint8_t nand_read_byte(struct mtd_info *mtd) +uint8_t nand_read_byte(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; return readb(chip->IO_ADDR_R); @@ -196,7 +196,7 @@ static void nand_select_chip(struct mtd_info *mtd, int chipnr) * * Default write function for 8bit buswith */ -static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) { int i; struct nand_chip *chip = mtd->priv; @@ -249,7 +249,7 @@ static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) * * Default write function for 16bit buswith */ -static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) +void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) { int i; struct nand_chip *chip = mtd->priv; -- cgit v1.2.1 From 56c91bc3b6be0551113df0eb1f0c8b1a597b9da1 Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Mon, 31 Oct 2011 06:34:45 +0000 Subject: Fix regression in SMDK6400 s3c64xx.c implemented its own nand_read_byte, nand_write_buf and nand_read_buf functions. This provoked a regression when these functions were made public by patch 55f429bb39614a16b1bacc9a8bea9ac01a60bfc8. This deletes these duplicated functions from s3c64xx.c and adds the generic implementations in nand_base.c to the spl Makefile. It also adds -ffcuntion-sections and -gc-sections to the compilation flags of the SPL to avoid errors originating from unused functions in nand_base.c. Description of the regression: http://article.gmane.org/gmane.comp.boot-loaders.u-boot/108873 Signed-off-by: Simon Schwarz Cc: scottwood@freescale.com Cc: s-paulraj@ti.com Cc: albert.u.boot@aribaud.net --- drivers/mtd/nand/s3c64xx.c | 28 ++-------------------------- 1 file changed, 2 insertions(+), 26 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/s3c64xx.c b/drivers/mtd/nand/s3c64xx.c index 084e475649..87f0341066 100644 --- a/drivers/mtd/nand/s3c64xx.c +++ b/drivers/mtd/nand/s3c64xx.c @@ -28,6 +28,8 @@ #include #include +#include + #include #include @@ -60,32 +62,6 @@ static void print_oob(const char *header, struct mtd_info *mtd) } #endif /* S3C_NAND_DEBUG */ -#ifdef CONFIG_NAND_SPL -static u_char nand_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - return readb(this->IO_ADDR_R); -} - -static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) -{ - int i; - struct nand_chip *this = mtd->priv; - - for (i = 0; i < len; i++) - writeb(buf[i], this->IO_ADDR_W); -} - -static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - int i; - struct nand_chip *this = mtd->priv; - - for (i = 0; i < len; i++) - buf[i] = readb(this->IO_ADDR_R); -} -#endif - static void s3c_nand_select_chip(struct mtd_info *mtd, int chip) { int ctrl = readl(NFCONT); -- cgit v1.2.1 From abc20aba1834c321a638b367c18dcce1bb4e232d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 26 Nov 2011 07:20:07 +0100 Subject: PXA: Rename CONFIG_PXA2[57]X to CONFIG_CPU_PXA2[57]X Signed-off-by: Marek Vasut --- drivers/mmc/pxa_mmc.c | 7 ++++--- drivers/mmc/pxa_mmc_gen.c | 4 ++-- drivers/net/lan91c96.h | 4 ++-- drivers/net/smc91111.h | 6 +++--- drivers/serial/serial_pxa.c | 4 ++-- drivers/serial/usbtty.h | 2 +- drivers/usb/gadget/Makefile | 2 +- 7 files changed, 15 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/pxa_mmc.c b/drivers/mmc/pxa_mmc.c index 3c2905c3c6..2b58a98ac3 100644 --- a/drivers/mmc/pxa_mmc.c +++ b/drivers/mmc/pxa_mmc.c @@ -129,7 +129,7 @@ mmc_block_read(uchar * dst, uint32_t src, int len) writel(~MMC_I_MASK_RXFIFO_RD_REQ, MMC_I_MASK); while (len) { if (readl(MMC_I_REG) & MMC_I_REG_RXFIFO_RD_REQ) { -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) int i; for (i = min(len, 32); i; i--) { *dst++ = readb(MMC_RXFIFO); @@ -560,7 +560,8 @@ mmc_legacy_init(int verbose) /* Reset device interface type */ mmc_dev.if_type = IF_TYPE_UNKNOWN; -#if defined (CONFIG_LUBBOCK) || (defined (CONFIG_GUMSTIX) && !defined(CONFIG_PXA27X)) +#if defined(CONFIG_LUBBOCK) || \ + (defined(CONFIG_GUMSTIX) && !defined(CONFIG_CPU_PXA27X)) set_GPIO_mode(GPIO6_MMCCLK_MD); set_GPIO_mode(GPIO8_MMCCS0_MD); #endif @@ -633,7 +634,7 @@ mmc_legacy_init(int verbose) writel(0, MMC_CLKRT); /* 20 MHz */ resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1); -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) if (IF_TYPE_SD == mmc_dev.if_type) { resp = mmc_cmd(MMC_CMD_APP_CMD, rca, 0, MMC_CMDAT_R1); resp = mmc_cmd(SD_CMD_APP_SET_BUS_WIDTH, 0, 2, MMC_CMDAT_R1); diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c index 28e37b4fe1..4a7c67a6bd 100644 --- a/drivers/mmc/pxa_mmc_gen.c +++ b/drivers/mmc/pxa_mmc_gen.c @@ -30,12 +30,12 @@ #include /* PXAMMC Generic default config for various CPUs */ -#if defined(CONFIG_PXA250) +#if defined(CONFIG_CPU_PXA25X) #define PXAMMC_FIFO_SIZE 1 #define PXAMMC_MIN_SPEED 312500 #define PXAMMC_MAX_SPEED 20000000 #define PXAMMC_HOST_CAPS (0) -#elif defined(CONFIG_PXA27X) +#elif defined(CONFIG_CPU_PXA27X) #define PXAMMC_CRC_SKIP #define PXAMMC_FIFO_SIZE 32 #define PXAMMC_MIN_SPEED 304000 diff --git a/drivers/net/lan91c96.h b/drivers/net/lan91c96.h index 6fbb0e3cbf..bef15225a3 100644 --- a/drivers/net/lan91c96.h +++ b/drivers/net/lan91c96.h @@ -68,7 +68,7 @@ typedef unsigned long int dword; #define SMC_IO_EXTENT 16 -#ifdef CONFIG_PXA250 +#ifdef CONFIG_CPU_PXA25X #ifdef CONFIG_LUBBOCK #define SMC_IO_SHIFT 2 @@ -146,7 +146,7 @@ typedef unsigned long int dword; }; \ }) -#else /* if not CONFIG_PXA250 */ +#else /* if not CONFIG_CPU_PXA25X */ /* * We have only 16 Bit PCMCIA access on Socket 0 diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index 895c749788..d70c66f58e 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -78,7 +78,7 @@ struct smc91111_priv{ #define SMC_IO_EXTENT 16 -#ifdef CONFIG_PXA250 +#ifdef CONFIG_CPU_PXA25X #ifdef CONFIG_XSENGINE #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1)))) @@ -180,7 +180,7 @@ struct smc91111_priv{ }; \ }) -#elif defined(CONFIG_LEON) /* if not CONFIG_PXA250 */ +#elif defined(CONFIG_LEON) /* if not CONFIG_CPU_PXA25X */ #define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); }) @@ -249,7 +249,7 @@ struct smc91111_priv{ }; \ }while(0) -#else /* if not CONFIG_PXA250 and not CONFIG_LEON */ +#else /* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */ #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ /* diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c index 84bb17c110..a9976d709a 100644 --- a/drivers/serial/serial_pxa.c +++ b/drivers/serial/serial_pxa.c @@ -49,7 +49,7 @@ DECLARE_GLOBAL_DATA_PTR; #define BTUART_INDEX 0 #define FFUART_INDEX 1 #define STUART_INDEX 2 -#elif CONFIG_PXA250 +#elif CONFIG_CPU_PXA25X #define UART_CLK_BASE (1 << 4) /* HWUART */ #define UART_CLK_REG CKEN #define HWUART_INDEX 0 @@ -68,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR; * Only PXA250 has HWUART, to avoid poluting the code with more macros, * artificially introduce this. */ -#ifndef CONFIG_PXA250 +#ifndef CONFIG_CPU_PXA25X #define HWUART_INDEX 0xff #endif diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index 14961c1969..e449cd717d 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -31,7 +31,7 @@ #include #elif defined(CONFIG_MUSB_UDC) #include -#elif defined(CONFIG_PXA27X) +#elif defined(CONFIG_CPU_PXA27X) #include #elif defined(CONFIG_SPEAR3XX) || defined(CONFIG_SPEAR600) #include diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 7d5b504c7c..5e7271352c 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -37,7 +37,7 @@ COBJS-y += ep0.o COBJS-$(CONFIG_OMAP1510) += omap1510_udc.o COBJS-$(CONFIG_OMAP1610) += omap1510_udc.o COBJS-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o -COBJS-$(CONFIG_PXA27X) += pxa27x_udc.o +COBJS-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o COBJS-$(CONFIG_SPEARUDC) += spr_udc.o endif endif -- cgit v1.2.1 From 7c587d320d110e41008bc7b658655d22485d05a6 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:29 +0000 Subject: davinci_emac: move arch-independent defines to separate header DaVinci EMAC is found not only on DaVinci SoCs but on some OMAP3 SoCs also. This patch moves common defines from arch-davinci/emac_defs.h to drivers/net/davinci_emac.h DaVinci specific PHY drivers hacked to include the new header. We might want to switch to phylib in future. Signed-off-by: Ilya Yanok --- drivers/net/davinci_emac.c | 1 + drivers/net/davinci_emac.h | 314 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 315 insertions(+) create mode 100644 drivers/net/davinci_emac.h (limited to 'drivers') diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 36c33af662..43c4373e0e 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -43,6 +43,7 @@ #include #include #include +#include "davinci_emac.h" unsigned int emac_dbg = 0; #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) diff --git a/drivers/net/davinci_emac.h b/drivers/net/davinci_emac.h new file mode 100644 index 0000000000..a42c93aa60 --- /dev/null +++ b/drivers/net/davinci_emac.h @@ -0,0 +1,314 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on: mach-davinci/emac_defs.h + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _DAVINCI_EMAC_H_ +#define _DAVINCI_EMAC_H_ +/* Ethernet Min/Max packet size */ +#define EMAC_MIN_ETHERNET_PKT_SIZE 60 +#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 +/* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ +#define EMAC_PKT_ALIGN 18 + +/* Number of RX packet buffers + * NOTE: Only 1 buffer supported as of now + */ +#define EMAC_MAX_RX_BUFFERS 10 + + +/*********************************************** + ******** Internally used macros *************** + ***********************************************/ + +#define EMAC_CH_TX 1 +#define EMAC_CH_RX 0 + +/* Each descriptor occupies 4 words, lets start RX desc's at 0 and + * reserve space for 64 descriptors max + */ +#define EMAC_RX_DESC_BASE 0x0 +#define EMAC_TX_DESC_BASE 0x1000 + +/* EMAC Teardown value */ +#define EMAC_TEARDOWN_VALUE 0xfffffffc + +/* MII Status Register */ +#define MII_STATUS_REG 1 + +/* Number of statistics registers */ +#define EMAC_NUM_STATS 36 + + +/* EMAC Descriptor */ +typedef volatile struct _emac_desc +{ + u_int32_t next; /* Pointer to next descriptor + in chain */ + u_int8_t *buffer; /* Pointer to data buffer */ + u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ + u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ +} emac_desc; + +/* CPPI bit positions */ +#define EMAC_CPPI_SOP_BIT (0x80000000) +#define EMAC_CPPI_EOP_BIT (0x40000000) +#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) +#define EMAC_CPPI_EOQ_BIT (0x10000000) +#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) +#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) + +#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) + +#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) +#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) +#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) +#define EMAC_MACCONTROL_GIGFORCE (1 << 17) +#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) + +#define EMAC_MAC_ADDR_MATCH (1 << 19) +#define EMAC_MAC_ADDR_IS_VALID (1 << 20) + +#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) +#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) + + +#define MDIO_CONTROL_IDLE (0x80000000) +#define MDIO_CONTROL_ENABLE (0x40000000) +#define MDIO_CONTROL_FAULT_ENABLE (0x40000) +#define MDIO_CONTROL_FAULT (0x80000) +#define MDIO_USERACCESS0_GO (0x80000000) +#define MDIO_USERACCESS0_WRITE_READ (0x0) +#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) +#define MDIO_USERACCESS0_ACK (0x20000000) + +/* Ethernet MAC Registers Structure */ +typedef struct { + dv_reg TXIDVER; + dv_reg TXCONTROL; + dv_reg TXTEARDOWN; + u_int8_t RSVD0[4]; + dv_reg RXIDVER; + dv_reg RXCONTROL; + dv_reg RXTEARDOWN; + u_int8_t RSVD1[100]; + dv_reg TXINTSTATRAW; + dv_reg TXINTSTATMASKED; + dv_reg TXINTMASKSET; + dv_reg TXINTMASKCLEAR; + dv_reg MACINVECTOR; + u_int8_t RSVD2[12]; + dv_reg RXINTSTATRAW; + dv_reg RXINTSTATMASKED; + dv_reg RXINTMASKSET; + dv_reg RXINTMASKCLEAR; + dv_reg MACINTSTATRAW; + dv_reg MACINTSTATMASKED; + dv_reg MACINTMASKSET; + dv_reg MACINTMASKCLEAR; + u_int8_t RSVD3[64]; + dv_reg RXMBPENABLE; + dv_reg RXUNICASTSET; + dv_reg RXUNICASTCLEAR; + dv_reg RXMAXLEN; + dv_reg RXBUFFEROFFSET; + dv_reg RXFILTERLOWTHRESH; + u_int8_t RSVD4[8]; + dv_reg RX0FLOWTHRESH; + dv_reg RX1FLOWTHRESH; + dv_reg RX2FLOWTHRESH; + dv_reg RX3FLOWTHRESH; + dv_reg RX4FLOWTHRESH; + dv_reg RX5FLOWTHRESH; + dv_reg RX6FLOWTHRESH; + dv_reg RX7FLOWTHRESH; + dv_reg RX0FREEBUFFER; + dv_reg RX1FREEBUFFER; + dv_reg RX2FREEBUFFER; + dv_reg RX3FREEBUFFER; + dv_reg RX4FREEBUFFER; + dv_reg RX5FREEBUFFER; + dv_reg RX6FREEBUFFER; + dv_reg RX7FREEBUFFER; + dv_reg MACCONTROL; + dv_reg MACSTATUS; + dv_reg EMCONTROL; + dv_reg FIFOCONTROL; + dv_reg MACCONFIG; + dv_reg SOFTRESET; + u_int8_t RSVD5[88]; + dv_reg MACSRCADDRLO; + dv_reg MACSRCADDRHI; + dv_reg MACHASH1; + dv_reg MACHASH2; + dv_reg BOFFTEST; + dv_reg TPACETEST; + dv_reg RXPAUSE; + dv_reg TXPAUSE; + u_int8_t RSVD6[16]; + dv_reg RXGOODFRAMES; + dv_reg RXBCASTFRAMES; + dv_reg RXMCASTFRAMES; + dv_reg RXPAUSEFRAMES; + dv_reg RXCRCERRORS; + dv_reg RXALIGNCODEERRORS; + dv_reg RXOVERSIZED; + dv_reg RXJABBER; + dv_reg RXUNDERSIZED; + dv_reg RXFRAGMENTS; + dv_reg RXFILTERED; + dv_reg RXQOSFILTERED; + dv_reg RXOCTETS; + dv_reg TXGOODFRAMES; + dv_reg TXBCASTFRAMES; + dv_reg TXMCASTFRAMES; + dv_reg TXPAUSEFRAMES; + dv_reg TXDEFERRED; + dv_reg TXCOLLISION; + dv_reg TXSINGLECOLL; + dv_reg TXMULTICOLL; + dv_reg TXEXCESSIVECOLL; + dv_reg TXLATECOLL; + dv_reg TXUNDERRUN; + dv_reg TXCARRIERSENSE; + dv_reg TXOCTETS; + dv_reg FRAME64; + dv_reg FRAME65T127; + dv_reg FRAME128T255; + dv_reg FRAME256T511; + dv_reg FRAME512T1023; + dv_reg FRAME1024TUP; + dv_reg NETOCTETS; + dv_reg RXSOFOVERRUNS; + dv_reg RXMOFOVERRUNS; + dv_reg RXDMAOVERRUNS; + u_int8_t RSVD7[624]; + dv_reg MACADDRLO; + dv_reg MACADDRHI; + dv_reg MACINDEX; + u_int8_t RSVD8[244]; + dv_reg TX0HDP; + dv_reg TX1HDP; + dv_reg TX2HDP; + dv_reg TX3HDP; + dv_reg TX4HDP; + dv_reg TX5HDP; + dv_reg TX6HDP; + dv_reg TX7HDP; + dv_reg RX0HDP; + dv_reg RX1HDP; + dv_reg RX2HDP; + dv_reg RX3HDP; + dv_reg RX4HDP; + dv_reg RX5HDP; + dv_reg RX6HDP; + dv_reg RX7HDP; + dv_reg TX0CP; + dv_reg TX1CP; + dv_reg TX2CP; + dv_reg TX3CP; + dv_reg TX4CP; + dv_reg TX5CP; + dv_reg TX6CP; + dv_reg TX7CP; + dv_reg RX0CP; + dv_reg RX1CP; + dv_reg RX2CP; + dv_reg RX3CP; + dv_reg RX4CP; + dv_reg RX5CP; + dv_reg RX6CP; + dv_reg RX7CP; +} emac_regs; + +/* EMAC Wrapper Registers Structure */ +typedef struct { +#ifdef DAVINCI_EMAC_VERSION2 + dv_reg idver; + dv_reg softrst; + dv_reg emctrl; + dv_reg c0rxthreshen; + dv_reg c0rxen; + dv_reg c0txen; + dv_reg c0miscen; + dv_reg c1rxthreshen; + dv_reg c1rxen; + dv_reg c1txen; + dv_reg c1miscen; + dv_reg c2rxthreshen; + dv_reg c2rxen; + dv_reg c2txen; + dv_reg c2miscen; + dv_reg c0rxthreshstat; + dv_reg c0rxstat; + dv_reg c0txstat; + dv_reg c0miscstat; + dv_reg c1rxthreshstat; + dv_reg c1rxstat; + dv_reg c1txstat; + dv_reg c1miscstat; + dv_reg c2rxthreshstat; + dv_reg c2rxstat; + dv_reg c2txstat; + dv_reg c2miscstat; + dv_reg c0rximax; + dv_reg c0tximax; + dv_reg c1rximax; + dv_reg c1tximax; + dv_reg c2rximax; + dv_reg c2tximax; +#else + u_int8_t RSVD0[4100]; + dv_reg EWCTL; + dv_reg EWINTTCNT; +#endif +} ewrap_regs; + +/* EMAC MDIO Registers Structure */ +typedef struct { + dv_reg VERSION; + dv_reg CONTROL; + dv_reg ALIVE; + dv_reg LINK; + dv_reg LINKINTRAW; + dv_reg LINKINTMASKED; + u_int8_t RSVD0[8]; + dv_reg USERINTRAW; + dv_reg USERINTMASKED; + dv_reg USERINTMASKSET; + dv_reg USERINTMASKCLEAR; + u_int8_t RSVD1[80]; + dv_reg USERACCESS0; + dv_reg USERPHYSEL0; + dv_reg USERACCESS1; + dv_reg USERPHYSEL1; +} mdio_regs; + +int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); +int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); + +typedef struct { + char name[64]; + int (*init)(int phy_addr); + int (*is_phy_connected)(int phy_addr); + int (*get_link_speed)(int phy_addr); + int (*auto_negotiate)(int phy_addr); +} phy_t; + +#endif /* _DAVINCI_EMAC_H_ */ -- cgit v1.2.1 From 82b772178d0f3d7f3cb246138197028795edf004 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:30 +0000 Subject: davinci_emac: use internal addresses in buffer descriptors On AM35xx CPPI RAM had different addresses when accessed from the CPU and from the EMAC. We need to account this to deal with the buffer descriptors correctly. Signed-off-by: Ilya Yanok --- drivers/net/davinci_emac.c | 39 ++++++++++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 43c4373e0e..2ac6874b35 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -48,6 +48,27 @@ unsigned int emac_dbg = 0; #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) +#ifdef EMAC_HW_RAM_ADDR +static inline unsigned long BD_TO_HW(unsigned long x) +{ + if (x == 0) + return 0; + + return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR; +} + +static inline unsigned long HW_TO_BD(unsigned long x) +{ + if (x == 0) + return 0; + + return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR; +} +#else +#define BD_TO_HW(x) (x) +#define HW_TO_BD(x) (x) +#endif + #ifdef DAVINCI_EMAC_GIG_ENABLE #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr) #else @@ -448,7 +469,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) /* Create RX queue and set receive process in place */ emac_rx_active_head = emac_rx_desc; for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { - rx_desc->next = (u_int32_t)(rx_desc + 1); + rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1)); rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; @@ -501,7 +522,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) emac_gigabit_enable(active_phy_addr[index]); /* Start receive process */ - writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP); + writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP); debug_emac("- emac_open\n"); @@ -619,7 +640,7 @@ static int davinci_eth_send_packet (struct eth_device *dev, EMAC_CPPI_OWNERSHIP_BIT | EMAC_CPPI_EOP_BIT); /* Send the packet */ - writel((unsigned long)emac_tx_desc, &adap_emac->TX0HDP); + writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP); /* Wait for packet to complete or link down */ while (1) { @@ -663,14 +684,14 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) } /* Ack received packet descriptor */ - writel((unsigned long)rx_curr_desc, &adap_emac->RX0CP); + writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP); curr_desc = rx_curr_desc; emac_rx_active_head = - (volatile emac_desc *) rx_curr_desc->next; + (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next)); if (status & EMAC_CPPI_EOQ_BIT) { if (emac_rx_active_head) { - writel((unsigned long)emac_rx_active_head, + writel(BD_TO_HW((ulong)emac_rx_active_head), &adap_emac->RX0HDP); } else { emac_rx_queue_active = 0; @@ -688,7 +709,7 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) emac_rx_active_head = curr_desc; emac_rx_active_tail = curr_desc; if (emac_rx_queue_active != 0) { - writel((unsigned long)emac_rx_active_head, + writel(BD_TO_HW((ulong)emac_rx_active_head), &adap_emac->RX0HDP); printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); emac_rx_queue_active = 1; @@ -696,10 +717,10 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) } else { tail_desc = emac_rx_active_tail; emac_rx_active_tail = curr_desc; - tail_desc->next = (unsigned int) curr_desc; + tail_desc->next = BD_TO_HW((ulong) curr_desc); status = tail_desc->pkt_flag_len; if (status & EMAC_CPPI_EOQ_BIT) { - writel((unsigned long)curr_desc, + writel(BD_TO_HW((ulong)curr_desc), &adap_emac->RX0HDP); status &= ~EMAC_CPPI_EOQ_BIT; tail_desc->pkt_flag_len = status; -- cgit v1.2.1 From 918588cfd380cdd93c796f9217283737b45887c6 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:31 +0000 Subject: davinci_emac: conditionally compile specific PHY support Signed-off-by: Ilya Yanok --- drivers/net/davinci_emac.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 2ac6874b35..4f9ed2fccd 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -803,6 +803,7 @@ int davinci_emac_initialize(void) phy_id |= tmp & 0x0000ffff; switch (phy_id) { +#ifdef PHY_KSZ8873 case PHY_KSZ8873: sprintf(phy[i].name, "KSZ8873 @ 0x%02x", active_phy_addr[i]); @@ -811,6 +812,8 @@ int davinci_emac_initialize(void) phy[i].get_link_speed = ksz8873_get_link_speed; phy[i].auto_negotiate = ksz8873_auto_negotiate; break; +#endif +#ifdef PHY_LXT972 case PHY_LXT972: sprintf(phy[i].name, "LXT972 @ 0x%02x", active_phy_addr[i]); @@ -819,6 +822,8 @@ int davinci_emac_initialize(void) phy[i].get_link_speed = lxt972_get_link_speed; phy[i].auto_negotiate = lxt972_auto_negotiate; break; +#endif +#ifdef PHY_DP83848 case PHY_DP83848: sprintf(phy[i].name, "DP83848 @ 0x%02x", active_phy_addr[i]); @@ -827,6 +832,8 @@ int davinci_emac_initialize(void) phy[i].get_link_speed = dp83848_get_link_speed; phy[i].auto_negotiate = dp83848_auto_negotiate; break; +#endif +#ifdef PHY_ET1011C case PHY_ET1011C: sprintf(phy[i].name, "ET1011C @ 0x%02x", active_phy_addr[i]); @@ -835,6 +842,7 @@ int davinci_emac_initialize(void) phy[i].get_link_speed = et1011c_get_link_speed; phy[i].auto_negotiate = gen_auto_negotiate; break; +#endif default: sprintf(phy[i].name, "GENERIC @ 0x%02x", active_phy_addr[i]); -- cgit v1.2.1 From 2aa8720257beadde8f798bd30096ca4c9007c8e0 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:33 +0000 Subject: davinci_emac: fix for running with dcache enabled DaVinci EMAC is present on TI AM35xx SoCs (ARMv7) which run with D-Cache enabled by default. So we have to take care and flush/invalidate the cache before/after the DMA operations. Please note that the receive buffer alignment to 32 byte boundary comes from the old driver version I don't know if it is really needed or alignment to cache line size is enough. Signed-off-by: Ilya Yanok --- drivers/net/davinci_emac.c | 41 +++++++++++++++++++++++++++++++++++++++-- drivers/net/davinci_emac.h | 5 +++-- 2 files changed, 42 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 4f9ed2fccd..4760390591 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include #include "davinci_emac.h" @@ -105,7 +106,8 @@ static volatile emac_desc *emac_rx_active_tail = 0; static int emac_rx_queue_active = 0; /* Receive packet buffers */ -static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; +static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE] + __aligned(ARCH_DMA_MINALIGN); #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3 @@ -119,6 +121,26 @@ static u_int8_t num_phy; phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; +static inline void davinci_flush_rx_descs(void) +{ + /* flush the whole RX descs area */ + flush_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, + EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); +} + +static inline void davinci_invalidate_rx_descs(void) +{ + /* invalidate the whole RX descs area */ + invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, + EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); +} + +static inline void davinci_flush_desc(emac_desc *desc) +{ + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + sizeof(*desc)); +} + static int davinci_eth_set_mac_addr(struct eth_device *dev) { unsigned long mac_hi; @@ -470,7 +492,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) emac_rx_active_head = emac_rx_desc; for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1)); - rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; + rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE]; rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; rx_desc++; @@ -482,6 +504,8 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) emac_rx_active_tail = rx_desc; emac_rx_queue_active = 1; + davinci_flush_rx_descs(); + /* Enable TX/RX */ writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); writel(0, &adap_emac->RXBUFFEROFFSET); @@ -639,6 +663,11 @@ static int davinci_eth_send_packet (struct eth_device *dev, EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT | EMAC_CPPI_EOP_BIT); + + flush_dcache_range((unsigned long)packet, + (unsigned long)packet + length); + davinci_flush_desc(emac_tx_desc); + /* Send the packet */ writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP); @@ -671,6 +700,8 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) volatile emac_desc *tail_desc; int status, ret = -1; + davinci_invalidate_rx_descs(); + rx_curr_desc = emac_rx_active_head; status = rx_curr_desc->pkt_flag_len; if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { @@ -678,6 +709,9 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) /* Error in packet - discard it and requeue desc */ printf ("WARN: emac_rcv_pkt: Error in packet\n"); } else { + unsigned long tmp = (unsigned long)rx_curr_desc->buffer; + + invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE); NetReceive (rx_curr_desc->buffer, (rx_curr_desc->buff_off_len & 0xffff)); ret = rx_curr_desc->buff_off_len & 0xffff; @@ -703,6 +737,7 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; rx_curr_desc->next = 0; + davinci_flush_desc(rx_curr_desc); if (emac_rx_active_head == 0) { printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); @@ -720,11 +755,13 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) tail_desc->next = BD_TO_HW((ulong) curr_desc); status = tail_desc->pkt_flag_len; if (status & EMAC_CPPI_EOQ_BIT) { + davinci_flush_desc(tail_desc); writel(BD_TO_HW((ulong)curr_desc), &adap_emac->RX0HDP); status &= ~EMAC_CPPI_EOQ_BIT; tail_desc->pkt_flag_len = status; } + davinci_flush_desc(tail_desc); } return (ret); } diff --git a/drivers/net/davinci_emac.h b/drivers/net/davinci_emac.h index a42c93aa60..37c841ca84 100644 --- a/drivers/net/davinci_emac.h +++ b/drivers/net/davinci_emac.h @@ -24,8 +24,9 @@ /* Ethernet Min/Max packet size */ #define EMAC_MIN_ETHERNET_PKT_SIZE 60 #define EMAC_MAX_ETHERNET_PKT_SIZE 1518 -/* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ -#define EMAC_PKT_ALIGN 18 +/* Buffer size (should be aligned on 32 byte and cache line) */ +#define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\ + ARCH_DMA_MINALIGN) /* Number of RX packet buffers * NOTE: Only 1 buffer supported as of now -- cgit v1.2.1 From 80deda5d8e02c7e58dd4e037d754d72a8e1a99ae Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:34 +0000 Subject: davinci_emac: hardcode 100Mbps for AM35xx and RMII For some reason code setting the speed based on the PHY feedback causes troubles on AM3517 so hardcode 100Mbps for now. Signed-off-by: Ilya Yanok --- drivers/net/davinci_emac.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 4760390591..d6c4e63d61 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -520,7 +520,8 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) writel(1, &adap_emac->RXUNICASTSET); /* Enable MII interface and Full duplex mode */ -#ifdef CONFIG_SOC_DA8XX +#if defined(CONFIG_SOC_DA8XX) || \ + (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII)) writel((EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE | EMAC_MACCONTROL_RMIISPEED_100), -- cgit v1.2.1 From 1df308e5be76ec42ade8fb21f623f36ba09217bd Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:37 +0000 Subject: nand_spl_simple: add support for software ECC This patch adds support for software ECC to the nand_spl_simple driver. To enable this one have to define CONFIG_SPL_NAND_SOFTECC. Tested on OMAP3. Signed-off-by: Ilya Yanok Acked-by: Scott Wood --- drivers/mtd/nand/nand_ecc.c | 2 +- drivers/mtd/nand/nand_spl_simple.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c index 52bc916afb..81f0e0812b 100644 --- a/drivers/mtd/nand/nand_ecc.c +++ b/drivers/mtd/nand/nand_ecc.c @@ -50,7 +50,7 @@ * only nand_correct_data() is needed */ -#ifndef CONFIG_NAND_SPL +#if !defined(CONFIG_NAND_SPL) || defined(CONFIG_SPL_NAND_SOFTECC) /* * Pre-calculated 256-way 1 byte column parity */ diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c index e5003e646e..ed821f244d 100644 --- a/drivers/mtd/nand/nand_spl_simple.c +++ b/drivers/mtd/nand/nand_spl_simple.c @@ -21,6 +21,7 @@ #include #include #include +#include static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; static nand_info_t mtd; @@ -204,7 +205,8 @@ static int nand_read_page(int block, int page, void *dst) oob_data = ecc_calc + 0x200; for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - this->ecc.hwctl(&mtd, NAND_ECC_READ); + if (this->ecc.mode != NAND_ECC_SOFT) + this->ecc.hwctl(&mtd, NAND_ECC_READ); this->read_buf(&mtd, p, eccsize); this->ecc.calculate(&mtd, p, &ecc_calc[i]); } @@ -274,6 +276,13 @@ void nand_init(void) (void __iomem *)CONFIG_SYS_NAND_BASE; board_nand_init(&nand_chip); +#ifdef CONFIG_SPL_NAND_SOFTECC + if (nand_chip.ecc.mode == NAND_ECC_SOFT) { + nand_chip.ecc.calculate = nand_calculate_ecc; + nand_chip.ecc.correct = nand_correct_data; + } +#endif + if (nand_chip.select_chip) nand_chip.select_chip(&mtd, 0); } -- cgit v1.2.1 From ff62fb4c6a01866310b0b5f43ea097e9e5220a27 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:38 +0000 Subject: omap_gpmc: use SOFTECC in SPL if it's enabled Use software ECC for the SPL build if support for software ECC in SPL is enabled. Signed-off-by: Ilya Yanok Acked-by: Scott Wood --- drivers/mtd/nand/omap_gpmc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 5bbec48be2..1dfe074e1e 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -348,7 +348,7 @@ int board_nand_init(struct nand_chip *nand) nand->chip_delay = 100; /* Default ECC mode */ -#ifndef CONFIG_SPL_BUILD +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC) nand->ecc.mode = NAND_ECC_SOFT; #else nand->ecc.mode = NAND_ECC_HW; @@ -359,7 +359,9 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.correct = omap_correct_data; nand->ecc.calculate = omap_calculate_ecc; omap_hwecc_init(nand); +#endif +#ifdef CONFIG_SPL_BUILD if (nand->options & NAND_BUSWIDTH_16) nand->read_buf = nand_read_buf16; else -- cgit v1.2.1 From b5ce18a235b9b7064575a817576a8aa2c64f30ac Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 29 Nov 2011 02:33:43 +0000 Subject: arm, davinci: move davinci_rtc struct to hardware.h move struct davinci_rtc to arch/arm/include/asm/arch-davinci/hardware.h and add RTC_KICK0R_WE, RTC_KICK1R_WE defines, so they are global useable. Signed-off-by: Heiko Schocher Cc: Sandeep Paulraj --- drivers/rtc/davinci.c | 26 -------------------------- 1 file changed, 26 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c index 8436cbf8e9..5cafff4d21 100644 --- a/drivers/rtc/davinci.c +++ b/drivers/rtc/davinci.c @@ -27,32 +27,6 @@ #include #if defined(CONFIG_CMD_DATE) -struct davinci_rtc { - u_int32_t second; - u_int32_t minutes; - u_int32_t hours; - u_int32_t day; - u_int32_t month; /* 0x10 */ - u_int32_t year; - u_int32_t dotw; - u_int32_t resv1; - u_int32_t alarmsecond; /* 0x20 */ - u_int32_t alarmminute; - u_int32_t alarmhour; - u_int32_t alarmday; - u_int32_t alarmmonth; /* 0x30 */ - u_int32_t alarmyear; - u_int32_t resv2[2]; - u_int32_t ctrl; /* 0x40 */ - u_int32_t status; - u_int32_t irq; -}; - -#define RTC_STATE_BUSY 0x01 -#define RTC_STATE_RUN 0x02 - -#define davinci_rtc_base ((struct davinci_rtc *)DAVINCI_RTC_BASE) - int rtc_get(struct rtc_time *tmp) { struct davinci_rtc *rtc = davinci_rtc_base; -- cgit v1.2.1 From b609009801b8a00644926f49b7d0d0cc0d3d8797 Mon Sep 17 00:00:00 2001 From: Prabhakar Lad Date: Thu, 17 Nov 2011 02:53:23 +0000 Subject: ARM: davici_emac: Fix condition for number of phy detects Fix the condition for number of phys in davinci_eth_phy_detect() function. CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT indicates number of phys. From this commit id dc02badab480563b0bf9d3908046ea9d6b22ae63 davinci emac initilazed one less than the number of phy count. Signed-off-by: Prabhakar Lad Acked-by: Heiko Schocher --- drivers/net/davinci_emac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index d6c4e63d61..fbd0f1b7b5 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -220,7 +220,7 @@ static int davinci_eth_phy_detect(void) for (i = 0, j = 0; i < 32; i++) if (phy_act_state & (1 << i)) { count++; - if (count < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) { + if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) { active_phy_addr[j++] = i; } else { printf("%s: to many PHYs detected.\n", -- cgit v1.2.1 From 12dab4ce85a7dc2cb2e4d813696ed47ed44fb24e Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 18 Nov 2011 01:17:44 +0000 Subject: apbh_dma: return error value on timeout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When a timeout occurs, the return value is prepared but never returned. Fix that. Signed-off-by: Uwe Kleine-König Signed-off-by: Wolfram Sang Cc: Marek Vasut Acked-by: Stefano Babic --- drivers/dma/apbh_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index 69a10428ef..4000974483 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -606,7 +606,7 @@ int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan) mxs_dma_reset(chan); } - return 0; + return ret; } /* -- cgit v1.2.1 From aa72e43bb77353f8f33f4f5c7484a48084495e50 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 23 Nov 2011 10:59:13 +0000 Subject: MXS: Add static annotations to dma driver Some functions were internal to the apbh dma driver, so annotate them static. Some of the functions weren't used at all so drop them. This makes the U-Boot binary smaller by about 1500 bytes. Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Wolfgang Denk Acked-by: Stefano Babic --- drivers/dma/apbh_dma.c | 209 ++++++++++++------------------------------------- 1 file changed, 50 insertions(+), 159 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index 4000974483..e85f5fe6d2 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -52,6 +52,47 @@ int mxs_dma_validate_chan(int channel) return 0; } +/* + * Return the address of the command within a descriptor. + */ +static unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc) +{ + return desc->address + offsetof(struct mxs_dma_desc, cmd); +} + +/* + * Read a DMA channel's hardware semaphore. + * + * As used by the MXS platform's DMA software, the DMA channel's hardware + * semaphore reflects the number of DMA commands the hardware will process, but + * has not yet finished. This is a volatile value read directly from hardware, + * so it must be be viewed as immediately stale. + * + * If the channel is not marked busy, or has finished processing all its + * commands, this value should be zero. + * + * See mxs_dma_append() for details on how DMA command blocks must be configured + * to maintain the expected behavior of the semaphore's value. + */ +static int mxs_dma_read_semaphore(int channel) +{ + struct mx28_apbh_regs *apbh_regs = + (struct mx28_apbh_regs *)MXS_APBH_BASE; + uint32_t tmp; + int ret; + + ret = mxs_dma_validate_chan(channel); + if (ret) + return ret; + + tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema); + + tmp &= APBH_CHn_SEMA_PHORE_MASK; + tmp >>= APBH_CHn_SEMA_PHORE_OFFSET; + + return tmp; +} + /* * Enable a DMA channel. * @@ -61,7 +102,7 @@ int mxs_dma_validate_chan(int channel) * This function marks the DMA channel as "busy," whether or not there are any * descriptors to process. */ -int mxs_dma_enable(int channel) +static int mxs_dma_enable(int channel) { struct mx28_apbh_regs *apbh_regs = (struct mx28_apbh_regs *)MXS_APBH_BASE; @@ -132,7 +173,7 @@ int mxs_dma_enable(int channel) * state. It is unwise to call this function if there is ANY chance the hardware * is still processing a command. */ -int mxs_dma_disable(int channel) +static int mxs_dma_disable(int channel) { struct mxs_dma_chan *pchan; struct mx28_apbh_regs *apbh_regs = @@ -162,7 +203,7 @@ int mxs_dma_disable(int channel) /* * Resets the DMA channel hardware. */ -int mxs_dma_reset(int channel) +static int mxs_dma_reset(int channel) { struct mx28_apbh_regs *apbh_regs = (struct mx28_apbh_regs *)MXS_APBH_BASE; @@ -178,91 +219,12 @@ int mxs_dma_reset(int channel) return 0; } -/* - * Freeze a DMA channel. - * - * This function causes the channel to continuously fail arbitration for bus - * access, which halts all forward progress without losing any state. A call to - * mxs_dma_unfreeze() will cause the channel to continue its current operation - * with no ill effect. - */ -int mxs_dma_freeze(int channel) -{ - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - int ret; - - ret = mxs_dma_validate_chan(channel); - if (ret) - return ret; - - writel(1 << (channel + APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET), - &apbh_regs->hw_apbh_channel_ctrl_set); - - return 0; -} - -/* - * Unfreeze a DMA channel. - * - * This function reverses the effect of mxs_dma_freeze(), enabling the DMA - * channel to continue from where it was frozen. - */ -int mxs_dma_unfreeze(int channel) -{ - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - int ret; - - ret = mxs_dma_validate_chan(channel); - if (ret) - return ret; - - writel(1 << (channel + APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET), - &apbh_regs->hw_apbh_channel_ctrl_clr); - - return 0; -} - -/* - * Read a DMA channel's hardware semaphore. - * - * As used by the MXS platform's DMA software, the DMA channel's hardware - * semaphore reflects the number of DMA commands the hardware will process, but - * has not yet finished. This is a volatile value read directly from hardware, - * so it must be be viewed as immediately stale. - * - * If the channel is not marked busy, or has finished processing all its - * commands, this value should be zero. - * - * See mxs_dma_append() for details on how DMA command blocks must be configured - * to maintain the expected behavior of the semaphore's value. - */ -int mxs_dma_read_semaphore(int channel) -{ - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - uint32_t tmp; - int ret; - - ret = mxs_dma_validate_chan(channel); - if (ret) - return ret; - - tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema); - - tmp &= APBH_CHn_SEMA_PHORE_MASK; - tmp >>= APBH_CHn_SEMA_PHORE_OFFSET; - - return tmp; -} - /* * Enable or disable DMA interrupt. * * This function enables the given DMA channel to interrupt the CPU. */ -int mxs_dma_enable_irq(int channel, int enable) +static int mxs_dma_enable_irq(int channel, int enable) { struct mx28_apbh_regs *apbh_regs = (struct mx28_apbh_regs *)MXS_APBH_BASE; @@ -282,33 +244,13 @@ int mxs_dma_enable_irq(int channel, int enable) return 0; } -/* - * Check if a DMA interrupt is pending. - */ -int mxs_dma_irq_is_pending(int channel) -{ - struct mx28_apbh_regs *apbh_regs = - (struct mx28_apbh_regs *)MXS_APBH_BASE; - uint32_t tmp; - int ret; - - ret = mxs_dma_validate_chan(channel); - if (ret) - return ret; - - tmp = readl(&apbh_regs->hw_apbh_ctrl1); - tmp |= readl(&apbh_regs->hw_apbh_ctrl2); - - return (tmp >> channel) & 1; -} - /* * Clear DMA interrupt. * * The software that is using the DMA channel must register to receive its * interrupts and, when they arrive, must call this function to clear them. */ -int mxs_dma_ack_irq(int channel) +static int mxs_dma_ack_irq(int channel) { struct mx28_apbh_regs *apbh_regs = (struct mx28_apbh_regs *)MXS_APBH_BASE; @@ -327,7 +269,7 @@ int mxs_dma_ack_irq(int channel) /* * Request to reserve a DMA channel */ -int mxs_dma_request(int channel) +static int mxs_dma_request(int channel) { struct mxs_dma_chan *pchan; @@ -359,7 +301,7 @@ int mxs_dma_request(int channel) * The channel will NOT be released if it's marked "busy" (see * mxs_dma_enable()). */ -int mxs_dma_release(int channel) +static int mxs_dma_release(int channel) { struct mxs_dma_chan *pchan; int ret; @@ -410,32 +352,6 @@ void mxs_dma_desc_free(struct mxs_dma_desc *pdesc) free(pdesc); } -/* - * Return the address of the command within a descriptor. - */ -unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc) -{ - return desc->address + offsetof(struct mxs_dma_desc, cmd); -} - -/* - * Check if descriptor is on a channel's active list. - * - * This function returns the state of a descriptor's "ready" flag. This flag is - * usually set only if the descriptor appears on a channel's active list. The - * descriptor may or may not have already been processed by the hardware. - * - * The "ready" flag is set when the descriptor is submitted to a channel by a - * call to mxs_dma_append() or mxs_dma_append_list(). The "ready" flag is - * cleared when a processed descriptor is moved off the active list by a call - * to mxs_dma_finish(). The "ready" flag is NOT cleared if the descriptor is - * aborted by a call to mxs_dma_disable(). - */ -int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc) -{ - return pdesc->flags & MXS_DMA_DESC_READY; -} - /* * Add a DMA descriptor to a channel. * @@ -508,31 +424,6 @@ int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc) return ret; } -/* - * Retrieve processed DMA descriptors. - * - * This function moves all the descriptors from the DMA channel's "done" list to - * the head of the given list. - */ -int mxs_dma_get_finished(int channel, struct list_head *head) -{ - struct mxs_dma_chan *pchan; - int ret; - - ret = mxs_dma_validate_chan(channel); - if (ret) - return ret; - - if (head == NULL) - return 0; - - pchan = mxs_dma_channels + channel; - - list_splice(&pchan->done, head); - - return 0; -} - /* * Clean up processed DMA descriptors. * @@ -544,7 +435,7 @@ int mxs_dma_get_finished(int channel, struct list_head *head) * This function marks the DMA channel as "not busy" if no unprocessed * descriptors remain on the "active" list. */ -int mxs_dma_finish(int channel, struct list_head *head) +static int mxs_dma_finish(int channel, struct list_head *head) { int sem; struct mxs_dma_chan *pchan; @@ -590,7 +481,7 @@ int mxs_dma_finish(int channel, struct list_head *head) /* * Wait for DMA channel to complete */ -int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan) +static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan) { struct mx28_apbh_regs *apbh_regs = (struct mx28_apbh_regs *)MXS_APBH_BASE; -- cgit v1.2.1 From 5a42cd33d5600e90245fe4fa979d888753b081de Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20Deli=C3=ABn?= Date: Tue, 22 Nov 2011 04:14:22 +0000 Subject: M28: Fix OB1 bug in GPIO driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch fixes a small off-by-one bug in the GPIO driver for the mxs platform that allowed the selection gpio pins of one bank more than the SoC actually has. Signed-off-by: Robert Deliën Acked-by: Marek Vasut Acked-by: Marek Vasut --- drivers/gpio/mxs_gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index b7e959128e..539738be9b 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -120,7 +120,7 @@ int gpio_direction_output(int gp, int value) int gpio_request(int gp, const char *label) { - if (PAD_BANK(gp) > PINCTRL_BANKS) + if (PAD_BANK(gp) >= PINCTRL_BANKS) return -EINVAL; return 0; -- cgit v1.2.1 From 40f6fffee5917930597bfcc07de1cd879d4994f6 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 22 Nov 2011 15:22:39 +0100 Subject: MX: serial_mxc: cleanup removing nasty #ifdef The serial driver for iMX SOCs is continuosly changed if a new SOC or not yet used port is used. CONFIG_SYS__ defines were used only to find the base address for the selected UART. Instead of that, move the base address to the board configuration file and drop all #ifdef from driver. Signed-off-by: Stefano Babic CC: Marek Vasut CC: Wolfgang Denk CC: Fabio Estevam CC: Helmut Raiger CC: John Rigby CC: Matthias Weisser CC: Jason Liu Acked-by: Jason Liu --- drivers/serial/serial_mxc.c | 37 ++++--------------------------------- 1 file changed, 4 insertions(+), 33 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index dcb4bd16d8..af00b9c0ec 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -24,41 +24,12 @@ #define __REG(x) (*((volatile u32 *)(x))) -#if defined(CONFIG_SYS_MX31_UART1) || defined(CONFIG_SYS_MX25_UART1) -#define UART_PHYS 0x43f90000 -#elif defined(CONFIG_SYS_MX31_UART2) || defined(CONFIG_SYS_MX25_UART2) -#define UART_PHYS 0x43f94000 -#elif defined(CONFIG_SYS_MX31_UART3) || defined(CONFIG_SYS_MX25_UART3) -#define UART_PHYS 0x5000c000 -#elif defined(CONFIG_SYS_MX31_UART4) || defined(CONFIG_SYS_MX25_UART4) -#define UART_PHYS 0x43fb0000 -#elif defined(CONFIG_SYS_MX31_UART5) || defined(CONFIG_SYS_MX25_UART5) -#define UART_PHYS 0x43fb4000 -#elif defined(CONFIG_SYS_MX27_UART1) -#define UART_PHYS 0x1000a000 -#elif defined(CONFIG_SYS_MX27_UART2) -#define UART_PHYS 0x1000b000 -#elif defined(CONFIG_SYS_MX27_UART3) -#define UART_PHYS 0x1000c000 -#elif defined(CONFIG_SYS_MX27_UART4) -#define UART_PHYS 0x1000d000 -#elif defined(CONFIG_SYS_MX27_UART5) -#define UART_PHYS 0x1001b000 -#elif defined(CONFIG_SYS_MX27_UART6) -#define UART_PHYS 0x1001c000 -#elif defined(CONFIG_SYS_MX35_UART1) || defined(CONFIG_SYS_MX51_UART1) || \ - defined(CONFIG_SYS_MX53_UART1) -#define UART_PHYS UART1_BASE_ADDR -#elif defined(CONFIG_SYS_MX35_UART2) || defined(CONFIG_SYS_MX51_UART2) || \ - defined(CONFIG_SYS_MX53_UART2) -#define UART_PHYS UART2_BASE_ADDR -#elif defined(CONFIG_SYS_MX35_UART3) || defined(CONFIG_SYS_MX51_UART3) || \ - defined(CONFIG_SYS_MX53_UART3) -#define UART_PHYS UART3_BASE_ADDR -#else -#error "define CONFIG_SYS_MXxx_UARTx to use the MXC UART driver" +#ifndef CONFIG_MXC_UART_BASE +#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver" #endif +#define UART_PHYS CONFIG_MXC_UART_BASE + #ifdef CONFIG_SERIAL_MULTI #warning "MXC driver does not support MULTI serials." #endif -- cgit v1.2.1