From 9035edbae9dd3c10751d78bf80a1b2bc225cda4f Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Mon, 20 Jul 2015 20:49:25 +0300 Subject: gpio: sh-pfc: fix gpio input read Fix gpio_read: gpio input (INDT) and gpio output (OUTDT) registers have different offset. gpio_read must be performed from INDT. Signed-off-by: Vladimir Barinov Signed-off-by: Nobuhiro Iwamatsu --- drivers/gpio/sh_pfc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/sh_pfc.c b/drivers/gpio/sh_pfc.c index 7a5af20a2a..a0eac137c2 100644 --- a/drivers/gpio/sh_pfc.c +++ b/drivers/gpio/sh_pfc.c @@ -75,7 +75,8 @@ static int gpio_read_bit(struct pinmux_data_reg *dr, debug("read_bit: addr = %lx, pos = %ld, " "r_width = %ld\n", dr->reg, pos, dr->reg_width); - return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1; + return + (gpio_read_raw_reg(dr->mapped_reg + 0x4, dr->reg_width) >> pos) & 1; } static void gpio_write_bit(struct pinmux_data_reg *dr, -- cgit v1.2.1 From 53be7bf2a536c3b0c260993e51bb0803938d21f5 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Mon, 20 Jul 2015 20:49:39 +0300 Subject: serial: serial-sh: SCIFA interface for R-Car Gen2 SoCs Add SCIFA console interface for R-Car Gen2 SoCs. SCIFA has different registers offsets and sizes then SCI. Hence it needs to put it's macro definitions separately. Signed-off-by: Vladimir Barinov Signed-off-by: Nobuhiro Iwamatsu --- drivers/serial/serial_sh.h | 43 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 34 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 941e6eda4c..cbc2929435 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -226,7 +226,11 @@ struct uart_port { # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) -# define SCIF_ORER 0x0001 +# if defined(CONFIG_SCIF_A) +# define SCIF_ORER 0x0200 +# else +# define SCIF_ORER 0x0001 +# endif # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30) /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ #else @@ -306,7 +310,11 @@ struct uart_port { #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) -# define SCIF_RFDC_MASK 0x003f +# if defined(CONFIG_SCIF_A) +# define SCIF_RFDC_MASK 0x007f +# else +# define SCIF_RFDC_MASK 0x001f +# endif #else # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) # define SCIF_RFDC_MASK 0x001f @@ -557,6 +565,25 @@ SCIF_FNS(SCFCR, 0x18, 16) SCIF_FNS(SCFDR, 0x1c, 16) SCIF_FNS(SCLSR, 0x24, 16) SCIF_FNS(DL, 0x00, 0) /* dummy */ +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) +/* SCIFA and SCIF register offsets and size */ +SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0) +SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0) +SCIx_FNS(SCSCR, 0, 0, 0x08, 16, 0, 0, 0x08, 16, 0, 0) +SCIx_FNS(SCxTDR, 0, 0, 0x20, 8, 0, 0, 0x0C, 8, 0, 0) +SCIx_FNS(SCxSR, 0, 0, 0x14, 16, 0, 0, 0x10, 16, 0, 0) +SCIx_FNS(SCxRDR, 0, 0, 0x24, 8, 0, 0, 0x14, 8, 0, 0) +SCIF_FNS(SCFCR, 0, 0, 0x18, 16) +SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) +SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) +SCIF_FNS(DL, 0, 0, 0x30, 16) +SCIF_FNS(CKS, 0, 0, 0x34, 16) +#if defined(CONFIG_SCIF_A) +SCIF_FNS(SCLSR, 0, 0, 0x14, 16) +#else +SCIF_FNS(SCLSR, 0, 0, 0x24, 16) +#endif #else /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ /* name off sz off sz off sz off sz off sz*/ @@ -594,14 +621,8 @@ SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) #endif SCIF_FNS(SCLSR, 0, 0, 0x24, 16) #endif -#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ - defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) -SCIF_FNS(DL, 0, 0, 0x30, 16) -SCIF_FNS(CKS, 0, 0, 0x34, 16) -#else SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */ #endif -#endif #define sci_in(port, reg) sci_##reg##_in(port) #define sci_out(port, reg, value) sci_##reg##_out(port, value) @@ -743,7 +764,11 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk) #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ -#define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ + #if defined(CONFIG_SCIF_A) + #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */ + #else + #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ + #endif #else /* Generic SH */ #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif -- cgit v1.2.1 From cc19722f040fe326b1622dd1e2699179def7e45d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 4 Sep 2015 14:43:00 +0200 Subject: sunxi_nand_spl: Add config parameter for 4KiB page sized NAND devices This patch adds support for NAND chips with 4KiB page size and 24/1024 ECC strength. Like the Micron MT29F32G08CBACAWP which is used on the ICnova-A20 SoM. Signed-off-by: Stefan Roese Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- drivers/mtd/nand/sunxi_nand_spl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index bf9b1b1450..5985534e5f 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -321,6 +321,7 @@ static int nand_read_buffer(uint32_t offs, unsigned int size, void *dest, { 8192, 40, 1024, 5 }, { 16384, 56, 1024, 5 }, { 8192, 24, 1024, 5 }, + { 4096, 24, 1024, 5 }, }; static int nand_config = -1; int i; -- cgit v1.2.1 From c12e0d9317cf9a86622a32c7060b62f3b0f151f2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 26 Aug 2015 15:41:33 +0800 Subject: driver: misc: correct Kconfig entry Should use FSL_SEC_MON, not CONFIG_FSL_SEC_MON as Kconfig entry. Signed-off-by: Peng Fan Cc: Simon Glass Cc: Masahiro Yamada Cc: Fabio Estevam Cc: York Sun Cc: Stefan Roese Cc: Tom Rini Acked-by: Simon Glass --- drivers/misc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index f29a169774..8b38a84de6 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -59,7 +59,7 @@ config CROS_EC_SPI provides a faster and more robust interface than I2C but the bugs are less interesting. -config CONFIG_FSL_SEC_MON +config FSL_SEC_MON bool "Enable FSL SEC_MON Driver" help Freescale Security Monitor block is responsible for monitoring -- cgit v1.2.1 From 0abdd9d01ac6ca58d8c5765bdaf4283949fdcd76 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:14 -0600 Subject: arm: Remove nhk8815 boards and nomadik arch These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass --- drivers/mtd/nand/Makefile | 1 - drivers/mtd/nand/nomadik.c | 206 --------------------------------------------- 2 files changed, 207 deletions(-) delete mode 100644 drivers/mtd/nand/nomadik.c (limited to 'drivers') diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 71c1a519e9..b4e5376176 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -60,7 +60,6 @@ obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_NAND_MXC) += mxc_nand.o obj-$(CONFIG_NAND_MXS) += mxs_nand.o obj-$(CONFIG_NAND_NDFC) += ndfc.o -obj-$(CONFIG_NAND_NOMADIK) += nomadik.o obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o obj-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o obj-$(CONFIG_NAND_SPEAR) += spr_nand.o diff --git a/drivers/mtd/nand/nomadik.c b/drivers/mtd/nand/nomadik.c deleted file mode 100644 index a7cee5138d..0000000000 --- a/drivers/mtd/nand/nomadik.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * (C) Copyright 2007 STMicroelectronics, - * (C) Copyright 2009 Alessandro Rubini - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -static inline int parity(int b) /* b is really a byte; returns 0 or ~0 */ -{ - __asm__ __volatile__( - "eor %0, %0, %0, lsr #4\n\t" - "eor %0, %0, %0, lsr #2\n\t" - "eor %0, %0, %0, lsr #1\n\t" - "ands %0, %0, #1\n\t" - "subne %0, %0, #2\t" - : "=r" (b) : "0" (b)); - return b; -} - -/* - * This is the ECC routine used in hardware, according to the manual. - * HW claims to make the calculation but not the correction; so we must - * recalculate the bytes for a comparison. - */ -static int ecc512(const unsigned char *data, unsigned char *ecc) -{ - int gpar = 0; - int i, val, par; - int pbits = 0; /* P8, P16, ... P2048 */ - int pprime = 0; /* P8', P16', ... P2048' */ - int lowbits; /* P1, P2, P4 and primes */ - - for (i = 0; i < 512; i++) { - par = parity((val = data[i])); - gpar ^= val; - pbits ^= (i & par); - } - /* - * Ok, now gpar is global parity (xor of all bytes) - * pbits are all the parity bits (non-prime ones) - */ - par = parity(gpar); - pprime = pbits ^ par; - /* Put low bits in the right position for ecc[2] (bits 7..2) */ - lowbits = 0 - | (parity(gpar & 0xf0) & 0x80) /* P4 */ - | (parity(gpar & 0x0f) & 0x40) /* P4' */ - | (parity(gpar & 0xcc) & 0x20) /* P2 */ - | (parity(gpar & 0x33) & 0x10) /* P2' */ - | (parity(gpar & 0xaa) & 0x08) /* P1 */ - | (parity(gpar & 0x55) & 0x04); /* P1' */ - - ecc[2] = ~(lowbits | ((pbits & 0x100) >> 7) | ((pprime & 0x100) >> 8)); - /* now intermix bits for ecc[1] (P1024..P128') and ecc[0] (P64..P8') */ - ecc[1] = ~( (pbits & 0x80) >> 0 | ((pprime & 0x80) >> 1) - | ((pbits & 0x40) >> 1) | ((pprime & 0x40) >> 2) - | ((pbits & 0x20) >> 2) | ((pprime & 0x20) >> 3) - | ((pbits & 0x10) >> 3) | ((pprime & 0x10) >> 4)); - - ecc[0] = ~( (pbits & 0x8) << 4 | ((pprime & 0x8) << 3) - | ((pbits & 0x4) << 3) | ((pprime & 0x4) << 2) - | ((pbits & 0x2) << 2) | ((pprime & 0x2) << 1) - | ((pbits & 0x1) << 1) | ((pprime & 0x1) << 0)); - return 0; -} - -/* This is the method in the chip->ecc field */ -static int nomadik_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat, - uint8_t *ecc_code) -{ - return ecc512(dat, ecc_code); -} - -static int nomadik_ecc_correct(struct mtd_info *mtd, uint8_t *dat, - uint8_t *r_ecc, uint8_t *c_ecc) -{ - struct nand_chip *chip = mtd->priv; - uint32_t r, c, d, diff; /*read, calculated, xor of them */ - - if (!memcmp(r_ecc, c_ecc, chip->ecc.bytes)) - return 0; - - /* Reorder the bytes into ascending-order 24 bits -- see manual */ - r = r_ecc[2] << 22 | r_ecc[1] << 14 | r_ecc[0] << 6 | r_ecc[2] >> 2; - c = c_ecc[2] << 22 | c_ecc[1] << 14 | c_ecc[0] << 6 | c_ecc[2] >> 2; - diff = (r ^ c) & ((1<<24)-1); /* use 24 bits only */ - - /* If 12 bits are different, one per pair, it's correctable */ - if (((diff | (diff>>1)) & 0x555555) == 0x555555) { - int bit = ((diff & 2) >> 1) - | ((diff & 0x8) >> 2) | ((diff & 0x20) >> 3); - int byte; - - d = diff >> 6; /* remove bit-order info */ - byte = ((d & 2) >> 1) - | ((d & 0x8) >> 2) | ((d & 0x20) >> 3) - | ((d & 0x80) >> 4) | ((d & 0x200) >> 5) - | ((d & 0x800) >> 6) | ((d & 0x2000) >> 7) - | ((d & 0x8000) >> 8) | ((d & 0x20000) >> 9); - /* correct the single bit */ - dat[byte] ^= 1<priv; - u32 pcr0 = readl(REG_FSMC_PCR0); - - if (ctrl & NAND_CTRL_CHANGE) { - ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); - - if (ctrl & NAND_CLE) - IO_ADDR_W |= MASK_CLE; - if (ctrl & NAND_ALE) - IO_ADDR_W |= MASK_ALE; - - if (ctrl & NAND_NCE) - writel(pcr0 | 0x4, REG_FSMC_PCR0); - else - writel(pcr0 & ~0x4, REG_FSMC_PCR0); - - this->IO_ADDR_W = (void *) IO_ADDR_W; - this->IO_ADDR_R = (void *) IO_ADDR_W; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -/* Returns 1 when ready; upper layers timeout at 20ms with timer routines */ -static int nomadik_nand_ready(struct mtd_info *mtd) -{ - return 1; /* The ready bit is handled in hardware */ -} - -/* Copy a buffer 32bits at a time: faster than defualt method which is 8bit */ -static void nomadik_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) -{ - int i; - struct nand_chip *chip = mtd->priv; - u32 *p = (u32 *) buf; - - len >>= 2; - writel(0, REG_FSMC_ECCR0); - for (i = 0; i < len; i++) - p[i] = readl(chip->IO_ADDR_R); -} - -int board_nand_init(struct nand_chip *chip) -{ - /* Set up the FSMC_PCR0 for nand access*/ - writel(0x0000004a, REG_FSMC_PCR0); - /* Set up FSMC_PMEM0, FSMC_PATT0 with timing data for access */ - writel(0x00020401, REG_FSMC_PMEM0); - writel(0x00020404, REG_FSMC_PATT0); - - chip->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING; - chip->cmd_ctrl = nomadik_nand_hwcontrol; - chip->dev_ready = nomadik_nand_ready; - /* The chip allows 32bit reads, so avoid the default 8bit copy */ - chip->read_buf = nomadik_nand_read_buf; - - /* ECC: follow the hardware-defined rulse, but do it in sw */ - chip->ecc.mode = NAND_ECC_HW; - chip->ecc.bytes = 3; - chip->ecc.size = 512; - chip->ecc.strength = 1; - chip->ecc.layout = &nomadik_ecc_layout; - chip->ecc.calculate = nomadik_ecc_calculate; - chip->ecc.hwctl = nomadik_ecc_hwctl; - chip->ecc.correct = nomadik_ecc_correct; - - return 0; -} -- cgit v1.2.1 From 1c87dd76c490041fce01e3dbfe29d993eadd693b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 19:19:34 -0600 Subject: arm: Remove xaeniax board This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass --- drivers/net/smc91111.c | 51 +------------------------------------------------- drivers/net/smc91111.h | 22 ---------------------- 2 files changed, 1 insertion(+), 72 deletions(-) (limited to 'drivers') diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c index ade14cd475..f31216ffa6 100644 --- a/drivers/net/smc91111.c +++ b/drivers/net/smc91111.c @@ -499,15 +499,8 @@ again: } /* we have a packet address, so tell the card to use it */ -#ifndef CONFIG_XAENIAX SMC_outb (dev, packet_no, PN_REG); -#else - /* On Xaeniax board, we can't use SMC_outb here because that way - * the Allocate MMU command will end up written to the command register - * as well, which will lead to a problem. - */ - SMC_outl (dev, packet_no << 16, 0); -#endif + /* do not write new ptr value if Write data fifo not empty */ while ( saved_ptr & PTR_NOTEMPTY ) printf ("Write data fifo not empty!\n"); @@ -542,39 +535,19 @@ again: */ #ifdef USE_32_BIT SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2); -#ifndef CONFIG_XAENIAX if (length & 0x2) SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))), SMC91111_DATA_REG); -#else - /* On XANEIAX, we can only use 32-bit writes, so we need to handle - * unaligned tail part specially. The standard code doesn't work. - */ - if ((length & 3) == 3) { - u16 * ptr = (u16*) &buf[length-3]; - SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16), - SMC91111_DATA_REG); - } else if ((length & 2) == 2) { - u16 * ptr = (u16*) &buf[length-2]; - SMC_outl(dev, *ptr, SMC91111_DATA_REG); - } else if (length & 1) { - SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG); - } else { - SMC_outl(dev, 0, SMC91111_DATA_REG); - } -#endif #else SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1); #endif /* USE_32_BIT */ -#ifndef CONFIG_XAENIAX /* Send the last byte, if there is one. */ if ((length & 1) == 0) { SMC_outw (dev, 0, SMC91111_DATA_REG); } else { SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG); } -#endif /* and let the chipset deal with it */ SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG); @@ -588,9 +561,6 @@ again: /* release packet */ /* no need to release, MMU does that now */ -#ifdef CONFIG_XAENIAX - SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); -#endif /* wait for MMU getting ready (low) */ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { @@ -610,9 +580,6 @@ again: /* release packet */ /* no need to release, MMU does that now */ -#ifdef CONFIG_XAENIAX - SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); -#endif /* wait for MMU getting ready (low) */ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { @@ -625,15 +592,7 @@ again: } /* restore previously saved registers */ -#ifndef CONFIG_XAENIAX SMC_outb( dev, saved_pnr, PN_REG ); -#else - /* On Xaeniax board, we can't use SMC_outb here because that way - * the Allocate MMU command will end up written to the command register - * as well, which will lead to a problem. - */ - SMC_outl(dev, saved_pnr << 16, 0); -#endif SMC_outw( dev, saved_ptr, PTR_REG ); return length; @@ -802,15 +761,7 @@ static int smc_rcv(struct eth_device *dev) udelay(1); /* Wait until not busy */ /* restore saved registers */ -#ifndef CONFIG_XAENIAX SMC_outb( dev, saved_pnr, PN_REG ); -#else - /* On Xaeniax board, we can't use SMC_outb here because that way - * the Allocate MMU command will end up written to the command register - * as well, which will lead to a problem. - */ - SMC_outl( dev, saved_pnr << 16, 0); -#endif SMC_outw( dev, saved_ptr, PTR_REG ); if (!is_error) { diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index e19c491cbc..5197f36039 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -77,19 +77,6 @@ struct smc91111_priv{ if (__p & 2) __v >>= 8; \ else __v &= 0xff; \ __v; }) -#elif defined(CONFIG_XAENIAX) -#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) -#define SMC_inw(a,z) ({ \ - unsigned int __p = (unsigned int)((a)->iobase + (z)); \ - unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \ - if (__p & 3) __v >>= 16; \ - else __v &= 0xffff; \ - __v; }) -#define SMC_inb(a,p) ({ \ - unsigned int ___v = SMC_inw((a),(p) & ~1); \ - if ((p) & 1) ___v >>= 8; \ - else ___v &= 0xff; \ - ___v; }) #else #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) @@ -104,15 +91,6 @@ struct smc91111_priv{ #ifdef CONFIG_XSENGINE #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d) -#elif defined (CONFIG_XAENIAX) -#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) -#define SMC_outw(a,d,p) ({ \ - dword __dwo = SMC_inl((a),(p) & ~3); \ - dword __dwn = (word)(d); \ - __dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \ - __dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \ - SMC_outl((a), __dwo, (p) & ~3); \ -}) #else #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) -- cgit v1.2.1 From 1a103c6caa0b27fcd3798267b980444f5459860f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 2 Sep 2015 14:29:12 +0200 Subject: mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600 This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can be used by boards equipped with a NAND chip that requires 4-bit ECC strength. The SPEAr600 HW ECC only supports 1-bit ECC strength. To enable SW BCH4, you need to specify this in your config header: #define CONFIG_NAND_ECC_BCH #define CONFIG_BCH And use the command "nandecc bch4" to select this ECC scheme upon runtime. Tested on SPEAr600 x600 board. Signed-off-by: Stefan Roese Cc: Scott Wood Acked-by: Viresh Kumar --- drivers/mtd/nand/fsmc_nand.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'drivers') diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c index 567eff0914..0976a67ff8 100644 --- a/drivers/mtd/nand/fsmc_nand.c +++ b/drivers/mtd/nand/fsmc_nand.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -390,6 +391,45 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, return 0; } +#ifndef CONFIG_SPL_BUILD +/* + * fsmc_nand_switch_ecc - switch the ECC operation between different engines + * + * @eccstrength - the number of bits that could be corrected + * (1 - HW, 4 - SW BCH4) + */ +int __maybe_unused fsmc_nand_switch_ecc(uint32_t eccstrength) +{ + struct nand_chip *nand; + struct mtd_info *mtd; + int err; + + mtd = &nand_info[nand_curr_device]; + nand = mtd->priv; + + /* Setup the ecc configurations again */ + if (eccstrength == 1) { + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.bytes = 3; + nand->ecc.strength = 1; + nand->ecc.layout = &fsmc_ecc1_layout; + nand->ecc.correct = nand_correct_data; + } else { + nand->ecc.mode = NAND_ECC_SOFT_BCH; + nand->ecc.calculate = nand_bch_calculate_ecc; + nand->ecc.correct = nand_bch_correct_data; + nand->ecc.bytes = 7; + nand->ecc.strength = 4; + nand->ecc.layout = NULL; + } + + /* Update NAND handling after ECC mode switch */ + err = nand_scan_tail(mtd); + + return err; +} +#endif /* CONFIG_SPL_BUILD */ + int fsmc_nand_init(struct nand_chip *nand) { static int chip_nr; -- cgit v1.2.1 From 6e295186c7fc8bf5be22a05f6ca9602f2bb507f2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 2 Sep 2015 17:24:57 -0600 Subject: Move malloc_cache_aligned() to its own header At present malloc.h is included everywhere since it recently was added to common.h in this commit: 4519668 mtd/nand/ubi: assortment of alignment fixes This seems wasteful and unnecessary. We have been trying to trim down common.h and put separate functions into separate header files and that change goes in the opposite direction. Move malloc_cache_aligned() to a new header so that this can be avoided. The header would perhaps be better named as alignmem.h but it needs to be included after common.h and people might be confused by this. With the name memalign.h it fits nicely after malloc() in most cases. Signed-off-by: Simon Glass Acked-by: Marcel Ziswiler --- drivers/mtd/nand/nand_util.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 21b4a618ce..71285b6669 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include -- cgit v1.2.1 From cf92e05c0135bc2b1a1b25a3218e31e6d79bad59 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 2 Sep 2015 17:24:58 -0600 Subject: Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h header Now that we have a new header file for cache-aligned allocation, we should move the stack-based allocation macro there also. Signed-off-by: Simon Glass --- drivers/block/ahci.c | 1 + drivers/mmc/dw_mmc.c | 1 + drivers/mmc/mmc.c | 1 + drivers/mmc/rpmb.c | 1 + drivers/mtd/nand/tegra_nand.c | 1 + drivers/net/e1000.c | 1 + drivers/net/fec_mxc.c | 1 + drivers/net/rtl8169.c | 1 + drivers/spi/mxs_spi.c | 1 + drivers/usb/eth/asix.c | 1 + drivers/usb/eth/asix88179.c | 1 + drivers/usb/eth/mcs7830.c | 1 + drivers/usb/eth/smsc95xx.c | 1 + drivers/usb/gadget/ether.c | 1 + drivers/usb/gadget/f_thor.c | 1 + drivers/usb/host/dwc2.c | 1 + drivers/usb/host/ehci-hcd.c | 1 + drivers/usb/host/ohci-hcd.c | 1 + drivers/usb/host/usb-uclass.c | 1 + drivers/video/bcm2835.c | 1 + 20 files changed, 20 insertions(+) (limited to 'drivers') diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 0d19dd25a3..82c68439f8 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 1117fedefe..a84c1e16d8 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 371c1ec212..2a58702848 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include "mmc_private.h" diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c index 9d0b8bc0c8..1c6888fc48 100644 --- a/drivers/mmc/rpmb.c +++ b/drivers/mmc/rpmb.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include "mmc_private.h" diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c index debad4f791..a77db7b65d 100644 --- a/drivers/mtd/nand/tegra_nand.c +++ b/drivers/mtd/nand/tegra_nand.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 7b830ff8c0..2ba03ed73e 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -32,6 +32,7 @@ tested on both gig copper and gig fiber boards #include #include #include +#include #include #include "e1000.h" diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index bff5fd1119..79f6737e8e 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 7b6e20f30f..ebd46b27e5 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #ifndef CONFIG_DM_ETH #include diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 2b9f395a97..627644b56b 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c index 8a43e7c27d..ad083cf8ae 100644 --- a/drivers/usb/eth/asix.c +++ b/drivers/usb/eth/asix.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "usb_ether.h" diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c index 94dfe85eff..cf4085d765 100644 --- a/drivers/usb/eth/asix88179.c +++ b/drivers/usb/eth/asix88179.c @@ -12,6 +12,7 @@ #include #include "usb_ether.h" #include +#include #include /* ASIX AX88179 based USB 3.0 Ethernet Devices */ diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c index c1b708600e..bbdad8b79a 100644 --- a/drivers/usb/eth/mcs7830.c +++ b/drivers/usb/eth/mcs7830.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include "usb_ether.h" diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c index 1dcd088b8d..dc8fa8891b 100644 --- a/drivers/usb/eth/smsc95xx.c +++ b/drivers/usb/eth/smsc95xx.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index 53f4672291..c5e35ee350 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "gadget_chips.h" diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index 06139ee04d..ff1481ba37 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index 85236aeb2a..541c0f9687 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 88b670b7f8..135ef72622 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 0ffd838db2..9bde2b252c 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -41,6 +41,7 @@ #endif #include +#include #include #include "ohci.h" diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index b17a7d762e..c66ebb6678 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c index 61d054dd89..7867fe3895 100644 --- a/drivers/video/bcm2835.c +++ b/drivers/video/bcm2835.c @@ -6,6 +6,7 @@ #include #include +#include #include #include -- cgit v1.2.1 From 44bfb43f9afab9b2944bb98bc0d514303f029ff9 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 4 Sep 2015 22:03:42 -0600 Subject: usb: gadget: don't leak configs when unbinding By the time g_dnl_unbind() is run, cdev->config has been set to NULL, so the free() there does nothing, and the config struct is leaked. Equally, struct usb_gadget contains a linked list of config structs, so the code should iterate over them all and free each one, rather than freeing one particular config struct. composite_unbind() already iterates over the list of config structs, and unlinks each from the linked list. Fix this loop to free() each struct as it's unlinked and otherwise forgotten. Signed-off-by: Stephen Warren Acked-by: Lukasz Majewski Tested-by: Lukasz Majewski --- drivers/usb/gadget/composite.c | 1 + drivers/usb/gadget/g_dnl.c | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index d96296cd73..a13b21d0a0 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -948,6 +948,7 @@ static void composite_unbind(struct usb_gadget *gadget) debug("unbind config '%s'/%p\n", c->label, c); c->unbind(c); } + free(c); } if (composite->unbind) composite->unbind(cdev); diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index ad89a0d2e6..2fa6da4091 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -93,8 +93,6 @@ static int g_dnl_unbind(struct usb_composite_dev *cdev) { struct usb_gadget *gadget = cdev->gadget; - free(cdev->config); - cdev->config = NULL; debug("%s: calling usb_gadget_disconnect for " "controller '%s'\n", __func__, gadget->name); usb_gadget_disconnect(gadget); -- cgit v1.2.1 From 806bd245b1ab392245e6adc56522c3473edbc805 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 4 Sep 2015 22:03:46 -0600 Subject: dfu: don't keep freeing/reallocating DFU currently allocates buffer memory at the start of each data transfer operation and frees it at the end. Especially since memalign() is used to allocate the buffer, and various other allocations happen during the transfer, this can expose the code to heap fragmentation, which prevents the allocation from succeeding on subsequent transfers. Fix the code to allocate the buffer once when DFU mode is initialized, and free the buffer once when DFU mode is exited, to reduce the exposure to heap fragmentation. The failure mode is: // Internally to memalign(), this allocates a lot more than s to guarantee // that alignment can occur, then returns chunks of memory at the start/ // end of the allocated buffer to the heap. p = memalign(a, s); // Various other malloc()s occur here, some of which allocate the RAM // immediately before/after "p". // // DFU transfer is complete, so buffer is released. free(p); // By chance, no other malloc()/free() here, in DFU at least. // // A new DFU transfer starts, so the buffer is allocated again. // In theory this should succeed since we just free()d a buffer of the // same size. However, this fails because memalign() internally attempts // to allocate much more than "s", yet free(p) above only free()d a // little more than "s". p = memalign(a, s); Signed-off-by: Stephen Warren Acked-by: Lukasz Majewski Tested-by: Lukasz Majewski --- drivers/dfu/dfu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 6cf240de22..6842aef420 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -164,7 +164,6 @@ static int dfu_write_buffer_drain(struct dfu_entity *dfu) void dfu_write_transaction_cleanup(struct dfu_entity *dfu) { /* clear everything */ - dfu_free_buf(); dfu->crc = 0; dfu->offset = 0; dfu->i_blk_seq_num = 0; @@ -385,7 +384,6 @@ int dfu_read(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) dfu_hash_algo->name, dfu->crc); puts("\nUPLOAD ... done\nCtrl+C to exit ...\n"); - dfu_free_buf(); dfu->i_blk_seq_num = 0; dfu->crc = 0; dfu->offset = 0; @@ -433,6 +431,7 @@ static int dfu_fill_entity(struct dfu_entity *dfu, char *s, int alt, __func__, interface); return -1; } + dfu_get_buf(dfu); return 0; } @@ -441,6 +440,7 @@ void dfu_free_entities(void) { struct dfu_entity *dfu, *p, *t = NULL; + dfu_free_buf(); list_for_each_entry_safe_reverse(dfu, p, &dfu_list, list) { list_del(&dfu->list); if (dfu->free_entity) -- cgit v1.2.1 From 411c5e57e8cf7dd83627a24b5cde73a0e662b1b0 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 4 Sep 2015 22:03:47 -0600 Subject: dfu: mmc: buffer file reads too When writing to files in a filesystem on MMC, dfu_mmc.c buffers up the entire file content until the end of the transaction, at which point the file is written in one go. This allows writing files larger than the USB transfer size (CONFIG_SYS_DFU_DATA_BUF_SIZE); the maximum written file size is CONFIG_SYS_DFU_MAX_FILE_SIZE (the size of the temporary buffer). The current file reading code does not do any buffering, and so limits the maximum read file size to the USB transfer size. Enhance the code to do the same kind of buffering as the write path, so the same file size limits apply. Remove the size checking code from dfu_read() since all read paths now support larger files than the USB transfer buffer. Signed-off-by: Stephen Warren Acked-by: Lukasz Majewski Tested-by: Lukasz Majewski --- drivers/dfu/dfu.c | 11 ----------- drivers/dfu/dfu_mmc.c | 27 ++++++++++++++++++++++++++- 2 files changed, 26 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 6842aef420..8f5915e49c 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -338,17 +338,6 @@ int dfu_read(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) dfu->r_left = dfu->get_medium_size(dfu); if (dfu->r_left < 0) return dfu->r_left; - switch (dfu->layout) { - case DFU_RAW_ADDR: - case DFU_RAM_ADDR: - break; - default: - if (dfu->r_left > dfu_buf_size) { - printf("%s: File too big for buffer\n", - __func__); - return -EOVERFLOW; - } - } debug("%s: %s %ld [B]\n", __func__, dfu->name, dfu->r_left); diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 2a780f7b5d..5a9fb4a6e2 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -18,6 +18,7 @@ static unsigned char *dfu_file_buf; static long dfu_file_buf_len; +static long dfu_file_buf_filled; static int mmc_access_part(struct dfu_entity *dfu, struct mmc *mmc, int part) { @@ -230,9 +231,12 @@ long dfu_get_medium_size_mmc(struct dfu_entity *dfu) return dfu->data.mmc.lba_size * dfu->data.mmc.lba_blk_size; case DFU_FS_FAT: case DFU_FS_EXT4: + dfu_file_buf_filled = -1; ret = mmc_file_op(DFU_OP_SIZE, dfu, NULL, &len); if (ret < 0) return ret; + if (len > CONFIG_SYS_DFU_MAX_FILE_SIZE) + return -1; return len; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, @@ -241,6 +245,27 @@ long dfu_get_medium_size_mmc(struct dfu_entity *dfu) } } +static int mmc_file_unbuffer(struct dfu_entity *dfu, u64 offset, void *buf, + long *len) +{ + int ret; + long file_len; + + if (dfu_file_buf_filled == -1) { + ret = mmc_file_op(DFU_OP_READ, dfu, dfu_file_buf, &file_len); + if (ret < 0) + return ret; + dfu_file_buf_filled = file_len; + } + if (offset + *len > dfu_file_buf_filled) + return -EINVAL; + + /* Add to the current buffer. */ + memcpy(buf, dfu_file_buf + offset, *len); + + return 0; +} + int dfu_read_medium_mmc(struct dfu_entity *dfu, u64 offset, void *buf, long *len) { @@ -252,7 +277,7 @@ int dfu_read_medium_mmc(struct dfu_entity *dfu, u64 offset, void *buf, break; case DFU_FS_FAT: case DFU_FS_EXT4: - ret = mmc_file_op(DFU_OP_READ, dfu, buf, len); + ret = mmc_file_unbuffer(dfu, offset, buf, len); break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, -- cgit v1.2.1 From 92a3188d7d836779915e3a6f9251fa07b9c753e4 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 7 Sep 2015 13:43:52 +0200 Subject: bitops: introduce BIT() definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann Acked-by: Stefan Roese Acked-by: Anatolij Gustschin --- drivers/ddr/marvell/a38x/ddr3_init.h | 2 -- drivers/mtd/nand/jz4740_nand.c | 1 - drivers/spi/davinci_spi.c | 2 -- drivers/spi/ep93xx_spi.c | 2 -- drivers/video/anx9804.c | 2 -- 5 files changed, 9 deletions(-) (limited to 'drivers') diff --git a/drivers/ddr/marvell/a38x/ddr3_init.h b/drivers/ddr/marvell/a38x/ddr3_init.h index e2ff040b00..cb3fb24416 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.h +++ b/drivers/ddr/marvell/a38x/ddr3_init.h @@ -32,8 +32,6 @@ */ #define MV_DEBUG_INIT -#define BIT(x) (1 << (x)) - #ifdef MV_DEBUG_INIT #define DEBUG_INIT_S(s) puts(s) #define DEBUG_INIT_D(d, l) printf("%x", d) diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c index 7a62cc3361..abcedc2102 100644 --- a/drivers/mtd/nand/jz4740_nand.c +++ b/drivers/mtd/nand/jz4740_nand.c @@ -16,7 +16,6 @@ #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000) #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000) -#define BIT(x) (1 << (x)) #define JZ_NAND_ECC_CTRL_ENCODING BIT(3) #define JZ_NAND_ECC_CTRL_RS BIT(2) #define JZ_NAND_ECC_CTRL_RESET BIT(1) diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 0a036ccb00..0bd4f88926 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -15,8 +15,6 @@ #include #include -#define BIT(x) (1 << (x)) - /* SPIGCR0 */ #define SPIGCR0_SPIENA_MASK 0x1 #define SPIGCR0_SPIRST_MASK 0x0 diff --git a/drivers/spi/ep93xx_spi.c b/drivers/spi/ep93xx_spi.c index 235557ea3c..cb682ddda4 100644 --- a/drivers/spi/ep93xx_spi.c +++ b/drivers/spi/ep93xx_spi.c @@ -16,8 +16,6 @@ #include - -#define BIT(x) (1<<(x)) #define SSPBASE SPI_BASE #define SSPCR0 0x0000 diff --git a/drivers/video/anx9804.c b/drivers/video/anx9804.c index 83d60d672d..37ad69a039 100755 --- a/drivers/video/anx9804.c +++ b/drivers/video/anx9804.c @@ -14,8 +14,6 @@ #include #include "anx9804.h" -#define BIT(x) (1 << (x)) - /* Registers at i2c address 0x38 */ #define ANX9804_HDCP_CONTROL_0_REG 0x01 -- cgit v1.2.1 From 89983478bdc99996bbc26bd63fd00358d3082cbe Mon Sep 17 00:00:00 2001 From: Sylvain Lemieux Date: Wed, 9 Sep 2015 11:35:58 -0400 Subject: gpio: lpc32xx: fix issues with port3 gpio The current simplify lpc32xx gpio driver implementation assume a maximum of 32 GPIO per port; there are a total of 22 GPI, 24 GPO and 6 GPIO to managed on port 3. Update the driver to fix the following: 1) When requesting GPI_xx and GPO_xx on port 3 (xx is the same number) the second call to "gpio_request" will return -EBUSY. 2) The status of GPO_xx pin report the status of the corresponding GPI_xx pin when using the "gpio status" command. 3) The gpio driver may setup the direction register for the wrong gpio when calling "gpio_direction_input" (GPI_xx) or "gpio_direction_output" (GPO_xx) on port 3; the call to the direction is require to use the "gpio status" command. The following change were done in the driver: 1) port3 GPI are cache in a separate 32 bits in the array. 2) port3 direction register written only for GPIO pins. 3) port3 GPO & GPIO (as output) are read using "p3_outp_state". 4) LPC32XX_GPI_P3_GRP updated to match the change. Signed-off-by: Sylvain Lemieux --- drivers/gpio/lpc32xx_gpio.c | 41 +++++++++++++++++++++++++++++++++++------ 1 file changed, 35 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c index 8a9826e6eb..9674ee75f0 100644 --- a/drivers/gpio/lpc32xx_gpio.c +++ b/drivers/gpio/lpc32xx_gpio.c @@ -22,7 +22,7 @@ * read on another one. * * In order to keep this code simple, GPIOS are considered here as - * homogeneous and linear, from 0 to 127. + * homogeneous and linear, from 0 to 159. * * ** WARNING #1 ** * @@ -35,7 +35,7 @@ * Please read NOTE in description of lpc32xx_gpio_get_function(). */ -#define LPC32XX_GPIOS 128 +#define LPC32XX_GPIOS 160 struct lpc32xx_gpio_priv { struct gpio_regs *regs; @@ -45,11 +45,18 @@ struct lpc32xx_gpio_priv { /** * We have 4 GPIO ports of 32 bits each + * + * Port mapping offset (32 bits each): + * - Port 0: 0 + * - Port 1: 32 + * - Port 2: 64 + * - Port 3: GPO / GPIO (output): 96 + * - Port 3: GPI: 128 */ -#define MAX_GPIO 128 +#define MAX_GPIO 160 -#define GPIO_TO_PORT(gpio) ((gpio / 32) & 3) +#define GPIO_TO_PORT(gpio) ((gpio / 32) & 7) #define GPIO_TO_RANK(gpio) (gpio % 32) #define GPIO_TO_MASK(gpio) (1 << (gpio % 32)) @@ -75,9 +82,16 @@ static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset) break; case 2: /* ports 2 and 3 share a common direction */ - case 3: writel(mask, ®s->p2_p3_dir_clr); break; + case 3: + /* Setup direction only for GPIO_xx. */ + if ((mask >= 25) && (mask <= 30)) + writel(mask, ®s->p2_p3_dir_clr); + break; + case 4: + /* GPI_xx; nothing to do. */ + break; default: return -1; } @@ -111,6 +125,11 @@ static int lpc32xx_gpio_get_value(struct udevice *dev, unsigned offset) value = readl(®s->p2_inp_state); break; case 3: + /* Read GPO_xx and GPIO_xx (as output) using p3_outp_state. */ + value = readl(®s->p3_outp_state); + break; + case 4: + /* Read GPI_xx and GPIO_xx (as input) using p3_inp_state. */ value = readl(®s->p3_inp_state); break; default: @@ -149,6 +168,8 @@ static int gpio_set(struct udevice *dev, unsigned gpio) case 3: writel(mask, ®s->p3_outp_set); break; + case 4: + /* GPI_xx; invalid. */ default: return -1; } @@ -181,6 +202,8 @@ static int gpio_clr(struct udevice *dev, unsigned gpio) case 3: writel(mask, ®s->p3_outp_clr); break; + case 4: + /* GPI_xx; invalid. */ default: return -1; } @@ -223,9 +246,15 @@ static int lpc32xx_gpio_direction_output(struct udevice *dev, unsigned offset, break; case 2: /* ports 2 and 3 share a common direction */ - case 3: writel(mask, ®s->p2_p3_dir_set); break; + case 3: + /* Setup direction only for GPIO_xx. */ + if ((mask >= 25) && (mask <= 30)) + writel(mask, ®s->p2_p3_dir_set); + break; + case 4: + /* GPI_xx; invalid. */ default: return -1; } -- cgit v1.2.1 From 70eaeb03c1fc173b1a7c11ad627d8cc8bbfe3e6c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 28 Aug 2015 09:20:30 +0800 Subject: usb: gadget: ci_udc: implement usb_ep_ops dequeue callback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement endpoint dequeue callback function. Without this function, uboot will hang when executing fastboot comamnd. See following flow: "fastboot_tx_write_str->fastboot_tx_write->usb_ep_dequeue->ep->ops->dequeue" without implement ci_udc dequeue function, ep->ops->dequeue is NULL, then uboot will hang. Tested on mx6qsabresd board with fastboot enabled. Signed-off-by: Peng Fan Tested-by: Fabio Estevam Cc: "Łukasz Majewski" Cc: Marek Vasut --- drivers/usb/gadget/ci_udc.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 3e8eb8799f..c0d23a444b 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -87,6 +87,7 @@ static int ci_ep_enable(struct usb_ep *ep, static int ci_ep_disable(struct usb_ep *ep); static int ci_ep_queue(struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags); +static int ci_ep_dequeue(struct usb_ep *ep, struct usb_request *req); static struct usb_request * ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req); @@ -99,6 +100,7 @@ static struct usb_ep_ops ci_ep_ops = { .enable = ci_ep_enable, .disable = ci_ep_disable, .queue = ci_ep_queue, + .dequeue = ci_ep_dequeue, .alloc_request = ci_ep_alloc_request, .free_request = ci_ep_free_request, }; @@ -525,6 +527,30 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep) writel(bit, &udc->epprime); } +static int ci_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) +{ + struct ci_ep *ci_ep = container_of(_ep, struct ci_ep, ep); + struct ci_req *ci_req; + + list_for_each_entry(ci_req, &ci_ep->queue, queue) { + if (&ci_req->req == _req) + break; + } + + if (&ci_req->req != _req) + return -EINVAL; + + list_del_init(&ci_req->queue); + + if (ci_req->req.status == -EINPROGRESS) { + ci_req->req.status = -ECONNRESET; + if (ci_req->req.complete) + ci_req->req.complete(_ep, _req); + } + + return 0; +} + static int ci_ep_queue(struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags) { -- cgit v1.2.1 From b337b3b2a53f112a217f4bd31307b02f830bb787 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 11 Sep 2015 17:10:02 -0600 Subject: usb: ci_udc: fix emissions of ZLPs Commit 6a132416359e "ci_udc: Update the ci_udc driver to support bulk transfers" caused the value of "len" to change without updating subsquent users of that variable in ci_ep_submit_next_request(). This caused the code that detects when to emit ZLPs (Zero Length Packets) never to trigger, which in turn caused host timeouts when a ZLP was required, which in turn broke tests/dfu/, even despite the assertion in that commit's description that "These changes are tested for both the DFU and lthor." Fix this by modifying the added dtd iteration code not to modify "len", but rather to keep state in a separate variable. Rename the variables while we're at it so they describe their purpose better. Fixes: 6a132416359e ("ci_udc: Update the ci_udc driver to support bulk transfers") Cc: Siva Durga Prasad Paladugu Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index c0d23a444b..1ba5054965 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -426,7 +426,7 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep) int bit, num, len, in; struct ci_req *ci_req; u8 *buf; - uint32_t length, actlen; + uint32_t len_left, len_this_dtd; struct ept_queue_item *dtd, *qtd; ci_ep->req_primed = true; @@ -444,25 +444,23 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep) ci_req->dtd_count = 0; buf = ci_req->hw_buf; - actlen = 0; + len_left = len; dtd = item; do { - length = min(ci_req->req.length - actlen, - (unsigned)EP_MAX_LENGTH_TRANSFER); + len_this_dtd = min(len_left, (unsigned)EP_MAX_LENGTH_TRANSFER); - dtd->info = INFO_BYTES(length) | INFO_ACTIVE; + dtd->info = INFO_BYTES(len_this_dtd) | INFO_ACTIVE; dtd->page0 = (unsigned long)buf; dtd->page1 = ((unsigned long)buf & 0xfffff000) + 0x1000; dtd->page2 = ((unsigned long)buf & 0xfffff000) + 0x2000; dtd->page3 = ((unsigned long)buf & 0xfffff000) + 0x3000; dtd->page4 = ((unsigned long)buf & 0xfffff000) + 0x4000; - len -= length; - actlen += length; - buf += length; + len_left -= len_this_dtd; + buf += len_this_dtd; - if (len) { + if (len_left) { qtd = (struct ept_queue_item *) memalign(ILIST_ALIGN, ILIST_ENT_SZ); dtd->next = (unsigned long)qtd; @@ -471,7 +469,7 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep) } ci_req->dtd_count++; - } while (len); + } while (len_left); item = dtd; /* -- cgit v1.2.1 From 1368f99346b1a6c566095bcb1df662cdbdb129b3 Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Wed, 2 Sep 2015 13:54:13 -0500 Subject: thermal: imx_thermal: rework driver to be reused Rework imx_thermal driver to be used across i.MX processor that support thermal sensor Signed-off-by: Adrian Alonso Signed-off-by: Peng Fan --- drivers/thermal/Makefile | 2 +- drivers/thermal/imx_thermal.c | 18 +++++++++++------- 2 files changed, 12 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 6d4cacdcf7..d768f5ef80 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -6,4 +6,4 @@ # obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o -obj-$(CONFIG_IMX6_THERMAL) += imx_thermal.o +obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 3c6c9679f9..d90874e5ec 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -41,7 +41,7 @@ struct thermal_data { int maxc; }; -static int read_cpu_temperature(struct udevice *dev) +static int read_cpu_temperature_mx6(struct udevice *dev) { int temperature; unsigned int reg, n_meas; @@ -129,13 +129,15 @@ int imx_thermal_get_temp(struct udevice *dev, int *temp) struct thermal_data *priv = dev_get_priv(dev); int cpu_tmp = 0; - cpu_tmp = read_cpu_temperature(dev); + if (is_soc_type(MXC_SOC_MX6)) + cpu_tmp = read_cpu_temperature_mx6(dev); while (cpu_tmp >= priv->critical) { printf("CPU Temperature (%dC) too close to max (%dC)", cpu_tmp, priv->maxc); puts(" waiting...\n"); udelay(5000000); - cpu_tmp = read_cpu_temperature(dev); + if (is_soc_type(MXC_SOC_MX6)) + cpu_tmp = read_cpu_temperature_mx6(dev); } *temp = cpu_tmp; @@ -157,10 +159,12 @@ static int imx_thermal_probe(struct udevice *dev) /* Read Temperature calibration data fuse */ fuse_read(pdata->fuse_bank, pdata->fuse_word, &fuse); - /* Check for valid fuse */ - if (fuse == 0 || fuse == ~0) { - printf("CPU: Thermal invalid data, fuse: 0x%x\n", fuse); - return -EPERM; + if (is_soc_type(MXC_SOC_MX6)) { + /* Check for valid fuse */ + if (fuse == 0 || fuse == ~0) { + printf("CPU: Thermal invalid data, fuse: 0x%x\n", fuse); + return -EPERM; + } } /* set critical cooling temp */ -- cgit v1.2.1 From d1aa6f2d58f7f27a890d26d0a1f1fc14aa81f127 Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Wed, 2 Sep 2015 13:54:22 -0500 Subject: thermal: imx: add imx7d soc thermal support Add imx7 SoC thermal driver support Signed-off-by: Adrian Alonso --- drivers/thermal/imx_thermal.c | 90 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 84 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index d90874e5ec..ca35be837b 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -25,6 +25,9 @@ #define FACTOR1 15976 #define FACTOR2 4297157 #define MEASURE_FREQ 327 +#define TEMPERATURE_MIN -40 +#define TEMPERATURE_HOT 85 +#define TEMPERATURE_MAX 125 #define TEMPSENSE0_TEMP_CNT_SHIFT 8 #define TEMPSENSE0_TEMP_CNT_MASK (0xfff << TEMPSENSE0_TEMP_CNT_SHIFT) @@ -41,7 +44,8 @@ struct thermal_data { int maxc; }; -static int read_cpu_temperature_mx6(struct udevice *dev) +#if defined(CONFIG_MX6) +static int read_cpu_temperature(struct udevice *dev) { int temperature; unsigned int reg, n_meas; @@ -123,21 +127,87 @@ static int read_cpu_temperature_mx6(struct udevice *dev) return temperature; } +#elif defined(CONFIG_MX7) +static int read_cpu_temperature(struct udevice *dev) +{ + unsigned int reg, tmp, start; + unsigned int raw_25c, te1; + int temperature; + unsigned int *priv = dev_get_priv(dev); + u32 fuse = *priv; + struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) + ANATOP_BASE_ADDR; + /* + * fuse data layout: + * [31:21] sensor value @ 25C + * [20:18] hot temperature value + * [17:9] sensor value of room + * [8:0] sensor value of hot + */ + + raw_25c = fuse >> 21; + if (raw_25c == 0) + raw_25c = 25; + + te1 = (fuse >> 9) & 0x1ff; + + /* + * now we only use single measure, every time we read + * the temperature, we will power on/down anadig thermal + * module + */ + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK, &ccm_anatop->tempsense1_clr); + writel(PMU_REF_REFTOP_SELFBIASOFF_MASK, &ccm_anatop->ref_set); + + /* write measure freq */ + reg = readl(&ccm_anatop->tempsense1); + reg &= ~TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK; + reg |= TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(MEASURE_FREQ); + writel(reg, &ccm_anatop->tempsense1); + + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_clr); + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set); + + start = get_timer(0); + /* Wait max 100ms */ + do { + /* + * Since we can not rely on finish bit, use 1ms delay to get + * temperature. From RM, 17us is enough to get data, but + * to gurantee to get the data, delay 100ms here. + */ + reg = readl(&ccm_anatop->tempsense1); + tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) + >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; + } while (get_timer(0) < (start + 100)); + + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); + + /* power down anatop thermal sensor */ + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK, &ccm_anatop->tempsense1_set); + writel(PMU_REF_REFTOP_SELFBIASOFF_MASK, &ccm_anatop->ref_clr); + + /* Single point */ + temperature = tmp - (te1 - raw_25c); + + return temperature; +} +#endif int imx_thermal_get_temp(struct udevice *dev, int *temp) { struct thermal_data *priv = dev_get_priv(dev); int cpu_tmp = 0; - if (is_soc_type(MXC_SOC_MX6)) - cpu_tmp = read_cpu_temperature_mx6(dev); + cpu_tmp = read_cpu_temperature(dev); + while (cpu_tmp >= priv->critical) { printf("CPU Temperature (%dC) too close to max (%dC)", cpu_tmp, priv->maxc); puts(" waiting...\n"); udelay(5000000); - if (is_soc_type(MXC_SOC_MX6)) - cpu_tmp = read_cpu_temperature_mx6(dev); + cpu_tmp = read_cpu_temperature(dev); } *temp = cpu_tmp; @@ -162,9 +232,17 @@ static int imx_thermal_probe(struct udevice *dev) if (is_soc_type(MXC_SOC_MX6)) { /* Check for valid fuse */ if (fuse == 0 || fuse == ~0) { - printf("CPU: Thermal invalid data, fuse: 0x%x\n", fuse); + printf("CPU: Thermal invalid data, fuse: 0x%x\n", + fuse); return -EPERM; } + } else if (is_soc_type(MXC_SOC_MX7)) { + /* No Calibration data in FUSE? */ + if ((fuse & 0x3ffff) == 0) + return -EPERM; + /* We do not support 105C TE2 */ + if (((fuse & 0x1c0000) >> 18) == 0x6) + return -EPERM; } /* set critical cooling temp */ -- cgit v1.2.1 From cd562c8d07c0684a49edb41eedc207fed7690f56 Mon Sep 17 00:00:00 2001 From: Adrian Alonso Date: Wed, 2 Sep 2015 13:54:23 -0500 Subject: imx: imx7d: add imx-common cpu support for imx7d Add imx-common cpu support for imx7d SoC - Update reset_cause for imx7d - Enable watchdog driver built for imx7d Signed-off-by: Adrian Alonso Signed-off-by: Peng Fan --- drivers/watchdog/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 482a4bd5be..9e9cb55069 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o -ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa)) +ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610 ls102xa)) obj-y += imx_watchdog.o endif obj-$(CONFIG_S5P) += s5p_wdt.o -- cgit v1.2.1 From c8434ccaceb987babfc925fe86db473a44352cf4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 8 Sep 2015 14:43:09 -0300 Subject: thermal: imx_thermal: Do not print on error It is not very useful to have the message below on every boot (especially when we are using early silicon): U-Boot 2015.10-rc2-23945-g37cf215 (Sep 08 2015 - 14:12:14 -0300) CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0 - invalid sensor device , so turn the error message into debug level. Signed-off-by: Fabio Estevam --- drivers/thermal/imx_thermal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index ca35be837b..09a3c52680 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -232,7 +232,7 @@ static int imx_thermal_probe(struct udevice *dev) if (is_soc_type(MXC_SOC_MX6)) { /* Check for valid fuse */ if (fuse == 0 || fuse == ~0) { - printf("CPU: Thermal invalid data, fuse: 0x%x\n", + debug("CPU: Thermal invalid data, fuse: 0x%x\n", fuse); return -EPERM; } -- cgit v1.2.1 From 8f6edf6d30cc22a4231c5dd97a3bd82803d8f08c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 10 Sep 2015 20:45:25 -0300 Subject: pcie_imx: Use 'ms' for milliseconds milliseconds should be written as 'ms' instead of 'mS'. Signed-off-by: Fabio Estevam Tested-by: Marek Vasut --- drivers/pci/pcie_imx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index ca485ba90c..1568f20c1a 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -495,7 +495,7 @@ __weak int imx6_pcie_toggle_reset(void) * * The PCIe #PERST reset line _MUST_ be connected, otherwise your * design does not conform to the specification. You must wait at - * least 20 mS after de-asserting the #PERST so the EP device can + * least 20 ms after de-asserting the #PERST so the EP device can * do self-initialisation. * * In case your #PERST pin is connected to a plain GPIO pin of the @@ -506,7 +506,7 @@ __weak int imx6_pcie_toggle_reset(void) * In case your #PERST toggling logic is more complex, for example * connected via CPLD or somesuch, you can override this function * in your board file and implement reset logic as needed. You must - * not forget to wait at least 20 mS after de-asserting #PERST in + * not forget to wait at least 20 ms after de-asserting #PERST in * this case either though. * * In case your #PERST line of the PCIe EP device is not connected @@ -538,7 +538,7 @@ static int imx6_pcie_deassert_core_reset(void) /* * Wait for the clock to settle a bit, when the clock are sourced - * from the CPU, we need about 30mS to settle. + * from the CPU, we need about 30 ms to settle. */ mdelay(50); -- cgit v1.2.1 From 02464e386bb5f0a022c121f95ae75cf583759d95 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 6 Aug 2015 15:31:02 -0600 Subject: fdt: add new fdt address parsing functions fdtdec_get_addr_size() hard-codes the number of cells used to represent an address or size in DT. This is incorrect in many cases depending on the DT binding for a particular node or property (e.g. it is incorrect for the "reg" property). In most cases, DT parsing code must use the properties #address-cells and #size-cells to parse addres properties. This change splits up the implementation of fdtdec_get_addr_size() so that the core logic can be used for both hard-coded and non-hard-coded cases. Various wrapper functions are implemented that support cases where hard-coded cell counts should or should not be used, and where the client does and doesn't know the parent node ID that contains the properties #address-cells and #size-cells. dev_get_addr() is updated to use the new functions. Core functionality in fdtdec_get_addr_size_fixed() is widely tested via fdtdec_get_addr_size(). I tested fdtdec_get_addr_size_auto_noparent() and dev_get_addr() by manually modifying the Tegra I2C driver to invoke them. Much of the core implementation of fdtdec_get_addr_size_fixed(), fdtdec_get_addr_size_auto_parent(), and fdtdec_get_addr_size_auto_noparent() comes from Thierry Reding's previous commit "fdt: Fix fdtdec_get_addr_size() for 64-bit". Based-on-work-by: Thierry Reding Cc: Thierry Reding Cc: Simon Glass Cc: Michal Suchanek Signed-off-by: Stephen Warren Acked-by: Simon Glass Dropped #define DEBUG at the top of fdtdec.c: Signed-off-by: Simon Glass --- drivers/core/device.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/core/device.c b/drivers/core/device.c index 0ccd443f25..0bc04d4876 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -581,7 +581,10 @@ fdt_addr_t dev_get_addr(struct udevice *dev) #if CONFIG_IS_ENABLED(OF_CONTROL) fdt_addr_t addr; - addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); + addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, + dev->parent->of_offset, + dev->of_offset, "reg", + 0, NULL); if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) { if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS) addr = simple_bus_translate(dev->parent, addr); -- cgit v1.2.1 From 62c390f8a3f0aabe61656d6996f1d49766de2c20 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 14 Sep 2015 08:47:47 +0200 Subject: mtd: nand: fsmc: Fixes and cleanup for fsmc_nand_switch_ecc() This patch addresses some comments raised by Scott in the last versions. Here the changes in detail: - Removed __maybe_unused as its not needed - Added check for strength == 4 and error out for the unsupported ECC strength values - Don't set .caclulate, .correct, and .bytes for NAND_ECC_SOFT_BCH as this will be done in nand_scan_tail() - Set .caclulate back to fsmc_read_hwecc() in the HW case - Added comment that this function will only be called on SPEAr platforms, not supporting the BCH8 HW ECC (FSMC_VER8) Signed-off-by: Stefan Roese Cc: Scott Wood Cc: Tom Rini Acked-by: Scott Wood --- drivers/mtd/nand/fsmc_nand.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c index 0976a67ff8..e0e9e1ebd0 100644 --- a/drivers/mtd/nand/fsmc_nand.c +++ b/drivers/mtd/nand/fsmc_nand.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -398,12 +397,18 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, * @eccstrength - the number of bits that could be corrected * (1 - HW, 4 - SW BCH4) */ -int __maybe_unused fsmc_nand_switch_ecc(uint32_t eccstrength) +int fsmc_nand_switch_ecc(uint32_t eccstrength) { struct nand_chip *nand; struct mtd_info *mtd; int err; + /* + * This functions is only called on SPEAr600 platforms, supporting + * 1 bit HW ECC. The BCH8 HW ECC (FSMC_VER8) from the ST-Ericsson + * Nomadik SoC is currently supporting this fsmc_nand_switch_ecc() + * function, as it doesn't need to switch to a different ECC layout. + */ mtd = &nand_info[nand_curr_device]; nand = mtd->priv; @@ -413,14 +418,18 @@ int __maybe_unused fsmc_nand_switch_ecc(uint32_t eccstrength) nand->ecc.bytes = 3; nand->ecc.strength = 1; nand->ecc.layout = &fsmc_ecc1_layout; + nand->ecc.calculate = fsmc_read_hwecc; nand->ecc.correct = nand_correct_data; - } else { + } else if (eccstrength == 4) { + /* + * .calculate .correct and .bytes will be set in + * nand_scan_tail() + */ nand->ecc.mode = NAND_ECC_SOFT_BCH; - nand->ecc.calculate = nand_bch_calculate_ecc; - nand->ecc.correct = nand_bch_correct_data; - nand->ecc.bytes = 7; nand->ecc.strength = 4; nand->ecc.layout = NULL; + } else { + printf("Error: ECC strength %d not supported!\n", eccstrength); } /* Update NAND handling after ECC mode switch */ -- cgit v1.2.1 From 68282f55b8465660af105086ad327ecdd8f35c67 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 14 Sep 2015 09:17:36 +0200 Subject: arm: Remove unused ST-Ericsson u8500 arch This arch does not seem to be supported / used at all in the current U-Boot mainline source tree any more. So lets remove the core u8500 code and code that was only referenced by this platform. Please note that this patch also removes these config options: - CONFIG_PL011_SERIAL_RLCR - CONFIG_PL011_SERIAL_FLUSH_ON_INIT As they only seem to be referenced by u8500 based boards. Without any such board in the current code, these config option don't make sense any more. Lets remove them as well. If someone still wants to use this platform, then please send patches to re-enable support by adding at least one board that references this code. Signed-off-by: Stefan Roese Cc: Mathieu Poirier Cc: John Rigby Cc: Simon Glass Cc: Masahiro Yamada Cc: Tom Rini Cc: Heiko Schocher Cc: Albert Aribaud Reviewed-by: Masahiro Yamada --- drivers/i2c/Makefile | 1 - drivers/i2c/u8500_i2c.c | 601 --------------------------------------- drivers/i2c/u8500_i2c.h | 178 ------------ drivers/serial/serial_pl01x.c | 22 -- drivers/usb/musb-new/musb_core.c | 2 +- 5 files changed, 1 insertion(+), 803 deletions(-) delete mode 100644 drivers/i2c/u8500_i2c.c delete mode 100644 drivers/i2c/u8500_i2c.h (limited to 'drivers') diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 8ce294b02a..32198bd5b2 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -14,7 +14,6 @@ obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o obj-$(CONFIG_I2C_MV) += mv_i2c.o obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o -obj-$(CONFIG_U8500_I2C) += u8500_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o diff --git a/drivers/i2c/u8500_i2c.c b/drivers/i2c/u8500_i2c.c deleted file mode 100644 index 81ffb8ed79..0000000000 --- a/drivers/i2c/u8500_i2c.c +++ /dev/null @@ -1,601 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Basic U-Boot I2C interface for STn8500/DB8500 - * Author: Michael Brandt for ST-Ericsson - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Only 7-bit I2C device addresses are supported. - */ - -#include -#include - -#include "u8500_i2c.h" -#include -#include - -#define U8500_I2C_ENDAD_COUNTER (CONFIG_SYS_HZ/100) /* I2C bus timeout */ -#define U8500_I2C_FIFO_FLUSH_COUNTER 500000 /* flush "timeout" */ -#define U8500_I2C_SCL_FREQ 100000 /* I2C bus clock freq */ -#define U8500_I2C_INPUT_FREQ 48000000 /* Input clock freq */ -#define TX_FIFO_THRESHOLD 0x4 -#define RX_FIFO_THRESHOLD 0x4 -#define SLAVE_SETUP_TIME 14 /* Slave data setup time, 250ns for 48MHz i2c_clk */ - -#define WRITE_FIELD(var, mask, shift, value) \ - (var = ((var & ~(mask)) | ((value) << (shift)))) - -static unsigned int bus_initialized[CONFIG_SYS_U8500_I2C_BUS_MAX]; -static unsigned int i2c_bus_num; -static unsigned int i2c_bus_speed[] = { - CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED, - CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED -}; -static struct u8500_i2c_regs *i2c_dev[] = { - (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C0_BASE, - (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C1_BASE, - (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C2_BASE, - (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C3_BASE, -}; - -static struct { - int periph; - int pcken; - int kcken; -} i2c_clock_bits[] = { - {3, 3, 3}, /* I2C0 */ - {1, 2, 2}, /* I2C1 */ - {1, 6, 6}, /* I2C2 */ - {2, 0, 0}, /* I2C3 */ -}; - -static void i2c_set_bit(void *reg, u32 mask) -{ - writel(readl(reg) | mask, reg); -} - -static void i2c_clr_bit(void *reg, u32 mask) -{ - writel(readl(reg) & ~mask, reg); -} - -static void i2c_write_field(void *reg, u32 mask, uint shift, u32 value) -{ - writel((readl(reg) & ~mask) | (value << shift), reg); -} - -static int __i2c_set_bus_speed(unsigned int speed) -{ - u32 value; - struct u8500_i2c_regs *i2c_regs; - - i2c_regs = i2c_dev[i2c_bus_num]; - - /* Select standard (100 kbps) speed mode */ - i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_SM, - U8500_I2C_CR_SHIFT_SM, 0x0); - - /* - * Set the Baud Rate Counter 2 value - * Baud rate (standard) = fi2cclk / ( (BRCNT2 x 2) + Foncycle ) - * Foncycle = 0 (no digital filtering) - */ - value = (u32) (U8500_I2C_INPUT_FREQ / (speed * 2)); - i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT2, - U8500_I2C_BRCR_SHIFT_BRCNT2, value); - - /* ensure that BRCNT value is zero */ - i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT1, - U8500_I2C_BRCR_SHIFT_BRCNT1, 0); - - return U8500_I2C_INPUT_FREQ/(value * 2); -} - -/* - * i2c_init - initialize the i2c bus - * - * speed: bus speed (in HZ) - * slaveaddr: address of device in slave mode - * - * Slave mode is not implemented. - */ -void i2c_init(int speed, int slaveaddr) -{ - struct u8500_i2c_regs *i2c_regs; - - debug("i2c_init bus %d, speed %d\n", i2c_bus_num, speed); - - u8500_clock_enable(i2c_clock_bits[i2c_bus_num].periph, - i2c_clock_bits[i2c_bus_num].pcken, - i2c_clock_bits[i2c_bus_num].kcken); - - i2c_regs = i2c_dev[i2c_bus_num]; - - /* Disable the controller */ - i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_PE); - - /* Clear registers */ - writel(0, &i2c_regs->cr); - writel(0, &i2c_regs->scr); - writel(0, &i2c_regs->hsmcr); - writel(0, &i2c_regs->tftr); - writel(0, &i2c_regs->rftr); - writel(0, &i2c_regs->dmar); - - i2c_bus_speed[i2c_bus_num] = __i2c_set_bus_speed(speed); - - /* - * Set our own address. - * Set slave address mode to 7 bit addressing mode - */ - i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_SAM); - i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_ADDR, - U8500_I2C_SCR_SHIFT_ADDR, slaveaddr); - /* Slave Data Set up Time */ - i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_DATA_SETUP_TIME, - U8500_I2C_SCR_SHIFT_DATA_SETUP_TIME, SLAVE_SETUP_TIME); - - /* Disable the DMA sync logic */ - i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_DMA_SLE, - U8500_I2C_CR_SHIFT_DMA_SLE, 0); - - /* Disable interrupts */ - writel(0, &i2c_regs->imscr); - - /* Configure bus master mode */ - i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_OM, U8500_I2C_CR_SHIFT_OM, - U8500_I2C_BUS_MASTER_MODE); - /* Set FIFO threshold values */ - writel(TX_FIFO_THRESHOLD, &i2c_regs->tftr); - writel(RX_FIFO_THRESHOLD, &i2c_regs->rftr); - - /* Enable the I2C Controller */ - i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_PE); - - bus_initialized[i2c_bus_num] = 1; -} - - -/* - * loop_till_bit_clear - polls on a bit till it clears - * ioreg: register where you want to check status - * mask: bit mask for the bit you wish to check - * timeout: timeout in ticks/s - */ -static int loop_till_bit_clear(void *io_reg, u32 mask, unsigned long timeout) -{ - unsigned long timebase = get_timer(0); - - do { - if ((readl(io_reg) & mask) == 0x0UL) - return 0; - } while (get_timer(timebase) < timeout); - - debug("loop_till_bit_clear timed out\n"); - return -1; -} - -/* - * loop_till_bit_set - polls on a bit till it is set. - * ioreg: register where you want to check status - * mask: bit mask for the bit you wish to check - * timeout: timeout in ticks/s - */ -static int loop_till_bit_set(void *io_reg, u32 mask, unsigned long timeout) -{ - unsigned long timebase = get_timer(0); - - do { - if ((readl(io_reg) & mask) != 0x0UL) - return 0; - } while (get_timer(timebase) < timeout); - - debug("loop_till_bit_set timed out\n"); - return -1; -} - -/* - * flush_fifo - flush the I2C TX and RX FIFOs - */ -static void flush_fifo(struct u8500_i2c_regs *i2c_regs) -{ - int counter = U8500_I2C_FIFO_FLUSH_COUNTER; - - /* Flush Tx FIFO */ - i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FTX); - /* Flush Rx FIFO */ - i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FRX); - while (counter--) { - if (!(readl(&i2c_regs->cr) & - (U8500_I2C_CR_FTX | U8500_I2C_CR_FRX))) - break; - } - return; -} - -#ifdef DEBUG -static void print_abort_reason(struct u8500_i2c_regs *i2c_regs) -{ - int cause; - - printf("abort: risr %08x, sr %08x\n", i2c_regs->risr, i2c_regs->sr); - cause = (readl(&i2c_regs->sr) & U8500_I2C_SR_CAUSE) >> - U8500_I2C_SR_SHIFT_CAUSE; - switch (cause) { - case U8500_I2C_NACK_ADDR: - printf("No Ack received after Slave Address xmission\n"); - break; - case U8500_I2C_NACK_DATA: - printf("Valid for MASTER_WRITE: No Ack received " - "during data phase\n"); - break; - case U8500_I2C_ACK_MCODE: - printf("Master recv ack after xmission of master code" - "in hs mode\n"); - break; - case U8500_I2C_ARB_LOST: - printf("Master Lost arbitration\n"); - break; - case U8500_I2C_BERR_START: - printf("Slave restarts\n"); - break; - case U8500_I2C_BERR_STOP: - printf("Slave reset\n"); - break; - case U8500_I2C_OVFL: - printf("Overflow\n"); - break; - default: - printf("Unknown error type\n"); - } -} -#endif - -/* - * i2c_abort - called when a I2C transaction failed - */ -static void i2c_abort(struct u8500_i2c_regs *i2c_regs) -{ -#ifdef DEBUG - print_abort_reason(i2c_regs); -#endif - /* flush RX and TX fifos */ - flush_fifo(i2c_regs); - - /* Acknowledge the Master Transaction Done */ - i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD); - - /* Acknowledge the Master Transaction Done Without Stop */ - i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS); - - i2c_init(i2c_bus_speed[i2c_bus_num], CONFIG_SYS_I2C_SLAVE); -} - -/* - * write addr, alias index, to I2C bus. - */ -static int i2c_write_addr(struct u8500_i2c_regs *i2c_regs, uint addr, int alen) -{ - while (alen--) { - /* Wait until the Tx Fifo is not full */ - if (loop_till_bit_clear((void *)&i2c_regs->risr, - U8500_I2C_INT_TXFF, - U8500_I2C_ENDAD_COUNTER)) { - i2c_abort(i2c_regs); - return -1; - } - - /* MSB first */ - writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->tfr); - } - - return 0; -} - -/* - * Internal simplified read function: - * i2c_regs: Pointer to I2C registers for current bus - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one register) - * value: Where to put the data - * - * Returns: 0 on success, not 0 on failure - */ -static int i2c_read_byte(struct u8500_i2c_regs *i2c_regs, uchar chip, - uint addr, int alen, uchar *value) -{ - u32 mcr = 0; - - /* Set the address mode to 7 bit */ - WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1); - - /* Store the slave address in the master control register */ - WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip); - - if (alen != 0) { - /* Master write operation */ - mcr &= ~(U8500_I2C_MCR_OP); - - /* Configure the Frame length to one byte */ - WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, - U8500_I2C_MCR_SHIFT_LENGTH, 1); - - /* Repeated start, no stop */ - mcr &= ~(U8500_I2C_MCR_STOP); - - /* Write Master Control Register */ - writel(mcr, &i2c_regs->mcr); - - /* send addr/index */ - if (i2c_write_addr(i2c_regs, addr, alen) != 0) - return -1; - - /* Check for the Master Transaction Done Without Stop */ - if (loop_till_bit_set((void *)&i2c_regs->risr, - U8500_I2C_INT_MTDWS, - U8500_I2C_ENDAD_COUNTER)) { - return -1; - } - - /* Acknowledge the Master Transaction Done Without Stop */ - i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS); - } - - /* Master control configuration for read operation */ - mcr |= U8500_I2C_MCR_OP; - - /* Configure the STOP condition, we read only one byte */ - mcr |= U8500_I2C_MCR_STOP; - - /* Set the frame length to one byte, we support only 1 byte reads */ - WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1); - - i2c_write_field(&i2c_regs->mcr, U8500_I2C_MCR_LENGTH_STOP_OP, - U8500_I2C_MCR_SHIFT_LENGTH_STOP_OP, mcr); - - /* - * receive_data_polling - */ - - /* Wait until the Rx FIFO is not empty */ - if (loop_till_bit_clear((void *)&i2c_regs->risr, - U8500_I2C_INT_RXFE, - U8500_I2C_ENDAD_COUNTER)) - return -1; - - /* Read the data byte from Rx FIFO */ - *value = readb(&i2c_regs->rfr); - - /* Wait until the work is done */ - if (loop_till_bit_set((void *)&i2c_regs->risr, U8500_I2C_INT_MTD, - U8500_I2C_ENDAD_COUNTER)) - return -1; - - /* Acknowledge the Master Transaction Done */ - i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD); - - /* If MTD is set, Master Transaction Done Without Stop is set too */ - i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS); - - return 0; -} - -/* - * Internal simplified write function: - * i2c_regs: Pointer to I2C registers for current bus - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one register) - * data: Where to read the data - * len: How many bytes to write - * - * Returns: 0 on success, not 0 on failure - */ -static int __i2c_write(struct u8500_i2c_regs *i2c_regs, u8 chip, uint addr, - int alen, u8 *data, int len) -{ - int i; - u32 mcr = 0; - - /* Set the address mode to 7 bit */ - WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1); - - /* Store the slave address in the master control register */ - WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip); - - /* Write operation */ - mcr &= ~(U8500_I2C_MCR_OP); - - /* Current transaction is terminated by STOP condition */ - mcr |= U8500_I2C_MCR_STOP; - - /* Frame length: addr byte + len */ - WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, - (alen + len)); - - /* Write MCR register */ - writel(mcr, &i2c_regs->mcr); - - if (i2c_write_addr(i2c_regs, addr, alen) != 0) - return -1; - - for (i = 0; i < len; i++) { - /* Wait until the Tx FIFO is not full */ - if (loop_till_bit_clear((void *)&i2c_regs->risr, - U8500_I2C_INT_TXFF, - U8500_I2C_ENDAD_COUNTER)) - return -1; - - /* it is a 32 bit register with upper 24 reserved R/O */ - writeb(data[i], &i2c_regs->tfr); - } - - /* Check for Master Transaction Done */ - if (loop_till_bit_set((void *)&i2c_regs->risr, - U8500_I2C_INT_MTD, - U8500_I2C_ENDAD_COUNTER)) { - printf("i2c_write_byte error2: risr %08x\n", - i2c_regs->risr); - return -1; - } - - /* Acknowledge Master Transaction Done */ - i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD); - - /* Acknowledge Master Transaction Done Without Stop */ - i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS); - - return 0; -} - -/* - * Probe the given I2C chip address. Returns 0 if a chip responded, - * not 0 on failure. - */ -int i2c_probe(uchar chip) -{ - u32 mcr = 0; - struct u8500_i2c_regs *i2c_regs; - - if (chip == CONFIG_SYS_I2C_SLAVE) - return 1; - - i2c_regs = i2c_dev[i2c_bus_num]; - - /* Set the address mode to 7 bit */ - WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1); - - /* Store the slave address in the master control register */ - WRITE_FIELD(mcr, U8500_I2C_MCR_A10, U8500_I2C_MCR_SHIFT_A7, chip); - - /* Read operation */ - mcr |= U8500_I2C_MCR_OP; - - /* Set the frame length to one byte */ - WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1); - - /* Current transaction is terminated by STOP condition */ - mcr |= U8500_I2C_MCR_STOP; - - /* Write MCR register */ - writel(mcr, &i2c_regs->mcr); - - /* Wait until the Rx Fifo is not empty */ - if (loop_till_bit_clear((void *)&i2c_regs->risr, - U8500_I2C_INT_RXFE, - U8500_I2C_ENDAD_COUNTER)) { - i2c_abort(i2c_regs); - return -1; - } - - flush_fifo(i2c_regs); - - /* Acknowledge the Master Transaction Done */ - i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD); - - /* Acknowledge the Master Transaction Done Without Stop */ - i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS); - - return 0; -} - -/* - * Read/Write interface: - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - int i; - int rc; - struct u8500_i2c_regs *i2c_regs; - - if (alen > 2) { - debug("I2C read: addr len %d not supported\n", alen); - return 1; - } - - i2c_regs = i2c_dev[i2c_bus_num]; - - for (i = 0; i < len; i++) { - rc = i2c_read_byte(i2c_regs, chip, addr + i, alen, &buffer[i]); - if (rc != 0) { - debug("I2C read: I/O error: %d\n", rc); - i2c_abort(i2c_regs); - return rc; - } - } - - return 0; -} - -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - int rc; - struct u8500_i2c_regs *i2c_regs; - i2c_regs = i2c_dev[i2c_bus_num]; - - rc = __i2c_write(i2c_regs, chip, addr, alen, buffer, - len); - if (rc != 0) { - debug("I2C write: I/O error\n"); - i2c_abort(i2c_regs); - return rc; - } - return 0; -} - -int i2c_set_bus_num(unsigned int bus) -{ - if (bus > ARRAY_SIZE(i2c_dev) - 1) { - debug("i2c_set_bus_num: only up to bus %d supported\n", - ARRAY_SIZE(i2c_dev)-1); - return -1; - } - - i2c_bus_num = bus; - - if (!bus_initialized[i2c_bus_num]) - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - return 0; -} - -int i2c_set_bus_speed(unsigned int speed) -{ - - if (speed > U8500_I2C_MAX_STANDARD_SCL) { - debug("i2c_set_bus_speed: only up to %d supported\n", - U8500_I2C_MAX_STANDARD_SCL); - return -1; - } - - /* sets as side effect i2c_bus_speed[i2c_bus_num] */ - i2c_init(speed, CONFIG_SYS_I2C_SLAVE); - - return 0; -} - -unsigned int i2c_get_bus_num(void) -{ - return i2c_bus_num; -} - -unsigned int i2c_get_bus_speed(void) -{ - return i2c_bus_speed[i2c_bus_num]; -} diff --git a/drivers/i2c/u8500_i2c.h b/drivers/i2c/u8500_i2c.h deleted file mode 100644 index ceecdeede0..0000000000 --- a/drivers/i2c/u8500_i2c.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _U8500_I2C_H_ -#define _U8500_I2C_H_ - -#include -#include -#include -#include - -struct u8500_i2c_regs { - u32 cr; /* Control Register 0x00 */ - u32 scr; /* Slave Address Register 0x04 */ - u32 hsmcr; /* HS Master code Register 0x08 */ - u32 mcr; /* Master Control Register 0x0C */ - u32 tfr; /* Transmit Fifo Register 0x10 */ - u32 sr; /* Status Register 0x14 */ - u32 rfr; /* Receiver Fifo Register 0x18 */ - u32 tftr; /* Transmit Fifo Threshold Register 0x1C */ - u32 rftr; /* Receiver Fifo Threshold Register 0x20 */ - u32 dmar; /* DMA register 0x24 */ - u32 brcr; /* Baud Rate Counter Register 0x28 */ - u32 imscr; /* Interrupt Mask Set and Clear Register 0x2C */ - u32 risr; /* Raw interrupt status register 0x30 */ - u32 misr; /* Masked interrupt status register 0x34 */ - u32 icr; /* Interrupt Set and Clear Register 0x38 */ - u32 reserved_1[(0xFE0 - 0x3c) >> 2]; /* Reserved 0x03C to 0xFE0 */ - u32 periph_id_0; /* peripheral ID 0 0xFE0 */ - u32 periph_id_1; /* peripheral ID 1 0xFE4 */ - u32 periph_id_2; /* peripheral ID 2 0xFE8 */ - u32 periph_id_3; /* peripheral ID 3 0xFEC */ - u32 cell_id_0; /* I2C cell ID 0 0xFF0 */ - u32 cell_id_1; /* I2C cell ID 1 0xFF4 */ - u32 cell_id_2; /* I2C cell ID 2 0xFF8 */ - u32 cell_id_3; /* I2C cell ID 3 0xFFC */ -}; - - -/* Control Register */ - -/* Mask values for control register mask */ -#define U8500_I2C_CR_PE 0x0001 /* Peripheral enable */ -#define U8500_I2C_CR_OM 0x0006 /* Operation mode */ -#define U8500_I2C_CR_SAM 0x0008 /* Slave Addressing mode */ -#define U8500_I2C_CR_SM 0x0030 /* Speed mode */ -#define U8500_I2C_CR_SGCM 0x0040 /* Slave General call mode */ -#define U8500_I2C_CR_FTX 0x0080 /* Flush Transmit */ -#define U8500_I2C_CR_FRX 0x0100 /* Flush Receive */ -#define U8500_I2C_CR_DMA_TX_EN 0x0200 /* DMA TX Enable */ -#define U8500_I2C_CR_DMA_RX_EN 0x0400 /* DMA Rx Enable */ -#define U8500_I2C_CR_DMA_SLE 0x0800 /* DMA Synchronization Logic enable */ -#define U8500_I2C_CR_LM 0x1000 /* Loop back mode */ -#define U8500_I2C_CR_FON 0x6000 /* Filtering On */ - -/* shift valus for control register bit fields */ -#define U8500_I2C_CR_SHIFT_PE 0 /* Peripheral enable */ -#define U8500_I2C_CR_SHIFT_OM 1 /* Operation mode */ -#define U8500_I2C_CR_SHIFT_SAM 3 /* Slave Addressing mode */ -#define U8500_I2C_CR_SHIFT_SM 4 /* Speed mode */ -#define U8500_I2C_CR_SHIFT_SGCM 6 /* Slave General call mode */ -#define U8500_I2C_CR_SHIFT_FTX 7 /* Flush Transmit */ -#define U8500_I2C_CR_SHIFT_FRX 8 /* Flush Receive */ -#define U8500_I2C_CR_SHIFT_DMA_TX_EN 9 /* DMA TX Enable */ -#define U8500_I2C_CR_SHIFT_DMA_RX_EN 10 /* DMA Rx Enable */ -#define U8500_I2C_CR_SHIFT_DMA_SLE 11 /* DMA Synch Logic enable */ -#define U8500_I2C_CR_SHIFT_LM 12 /* Loop back mode */ -#define U8500_I2C_CR_SHIFT_FON 13 /* Filtering On */ - -/* bus operation modes */ -#define U8500_I2C_BUS_SLAVE_MODE 0 -#define U8500_I2C_BUS_MASTER_MODE 1 -#define U8500_I2C_BUS_MASTER_SLAVE_MODE 2 - - -/* Slave control register*/ - -/* Mask values slave control register */ -#define U8500_I2C_SCR_ADDR 0x3FF -#define U8500_I2C_SCR_DATA_SETUP_TIME 0xFFFF0000 - -/* Shift values for Slave control register */ -#define U8500_I2C_SCR_SHIFT_ADDR 0 -#define U8500_I2C_SCR_SHIFT_DATA_SETUP_TIME 16 - - -/* Master Control Register */ - -/* Mask values for Master control register */ -#define U8500_I2C_MCR_OP 0x00000001 /* Operation */ -#define U8500_I2C_MCR_A7 0x000000FE /* LSB bits of Address */ -#define U8500_I2C_MCR_EA10 0x00000700 /* Extended Address */ -#define U8500_I2C_MCR_SB 0x00000800 /* Start byte procedure */ -#define U8500_I2C_MCR_AM 0x00003000 /* Address type */ -#define U8500_I2C_MCR_STOP 0x00004000 /* stop condition */ -#define U8500_I2C_MCR_LENGTH 0x03FF8000 /* Frame length */ -#define U8500_I2C_MCR_A10 0x000007FE /* Enable 10 bit address */ -/* mask for length field,stop and operation */ -#define U8500_I2C_MCR_LENGTH_STOP_OP 0x3FFC001 - -/* Shift values for Master control values */ -#define U8500_I2C_MCR_SHIFT_OP 0 /* Operation */ -#define U8500_I2C_MCR_SHIFT_A7 1 /* LSB bits of Address */ -#define U8500_I2C_MCR_SHIFT_EA10 8 /* Extended Address */ -#define U8500_I2C_MCR_SHIFT_SB 11 /* Start byte procedure */ -#define U8500_I2C_MCR_SHIFT_AM 12 /* Address type */ -#define U8500_I2C_MCR_SHIFT_STOP 14 /* stop condition */ -#define U8500_I2C_MCR_SHIFT_LENGTH 15 /* Frame length */ -#define U8500_I2C_MCR_SHIFT_A10 1 /* Enable 10 bit address */ - -#define U8500_I2C_MCR_SHIFT_LENGTH_STOP_OP 0 - - -/* Status Register */ - -/* Mask values for Status register */ -#define U8500_I2C_SR_OP 0x00000003 /* Operation */ -#define U8500_I2C_SR_STATUS 0x0000000C /* Controller Status */ -#define U8500_I2C_SR_CAUSE 0x00000070 /* Abort Cause */ -#define U8500_I2C_SR_TYPE 0x00000180 /* Receive Type */ -#define U8500_I2C_SR_LENGTH 0x000FF700 /* Transfer length */ - -/* Shift values for Status register */ -#define U8500_I2C_SR_SHIFT_OP 0 /* Operation */ -#define U8500_I2C_SR_SHIFT_STATUS 2 /* Controller Status */ -#define U8500_I2C_SR_SHIFT_CAUSE 4 /* Abort Cause */ -#define U8500_I2C_SR_SHIFT_TYPE 7 /* Receive Type */ -#define U8500_I2C_SR_SHIFT_LENGTH 9 /* Transfer length */ - -/* abort cause */ -#define U8500_I2C_NACK_ADDR 0 -#define U8500_I2C_NACK_DATA 1 -#define U8500_I2C_ACK_MCODE 2 -#define U8500_I2C_ARB_LOST 3 -#define U8500_I2C_BERR_START 4 -#define U8500_I2C_BERR_STOP 5 -#define U8500_I2C_OVFL 6 - - -/* Baud rate counter registers */ - -/* Mask values for Baud rate counter register */ -#define U8500_I2C_BRCR_BRCNT2 0xFFFF /* Baud Rate Cntr BRCR for HS */ -#define U8500_I2C_BRCR_BRCNT1 0xFFFF0000 /* BRCR for Standard and Fast */ - -/* Shift values for the Baud rate counter register */ -#define U8500_I2C_BRCR_SHIFT_BRCNT2 0 -#define U8500_I2C_BRCR_SHIFT_BRCNT1 16 - - -/* Interrupt Register */ - -/* Mask values for Interrupt registers */ -#define U8500_I2C_INT_TXFE 0x00000001 /* Tx fifo empty */ -#define U8500_I2C_INT_TXFNE 0x00000002 /* Tx Fifo nearly empty */ -#define U8500_I2C_INT_TXFF 0x00000004 /* Tx Fifo Full */ -#define U8500_I2C_INT_TXFOVR 0x00000008 /* Tx Fifo over run */ -#define U8500_I2C_INT_RXFE 0x00000010 /* Rx Fifo Empty */ -#define U8500_I2C_INT_RXFNF 0x00000020 /* Rx Fifo nearly empty */ -#define U8500_I2C_INT_RXFF 0x00000040 /* Rx Fifo Full */ -#define U8500_I2C_INT_RFSR 0x00010000 /* Read From slave request */ -#define U8500_I2C_INT_RFSE 0x00020000 /* Read from slave empty */ -#define U8500_I2C_INT_WTSR 0x00040000 /* Write to Slave request */ -#define U8500_I2C_INT_MTD 0x00080000 /* Master Transcation Done*/ -#define U8500_I2C_INT_STD 0x00100000 /* Slave Transaction Done */ -#define U8500_I2C_INT_MAL 0x01000000 /* Master Arbitation Lost */ -#define U8500_I2C_INT_BERR 0x02000000 /* Bus Error */ -#define U8500_I2C_INT_MTDWS 0x10000000 /* Master Tran Done wo/ Stop */ - -/* Max clocks (Hz) */ -#define U8500_I2C_MAX_STANDARD_SCL 100000 -#define U8500_I2C_MAX_FAST_SCL 400000 -#define U8500_I2C_MAX_HIGH_SPEED_SCL 3400000 - -#endif /* _U8500_I2C_H_ */ diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index ecf3bc0240..3a5c1d0eaa 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -80,13 +80,6 @@ static int pl01x_generic_serial_init(struct pl01x_regs *regs, writel(0, ®s->pl010_cr); break; case TYPE_PL011: -#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT - /* Empty RX fifo if necessary */ - if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) { - while (!(readl(®s->fr) & UART_PL01x_FR_RXFE)) - readl(®s->dr); - } -#endif /* disable everything */ writel(0, ®s->pl011_cr); break; @@ -105,21 +98,6 @@ static int pl011_set_line_control(struct pl01x_regs *regs) * control register write */ lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN; -#ifdef CONFIG_PL011_SERIAL_RLCR - { - int i; - - /* - * Program receive line control register after waiting - * 10 bus cycles. Delay be writing to readonly register - * 10 times - */ - for (i = 0; i < 10; i++) - writel(lcr, ®s->fr); - - writel(lcr, ®s->pl011_rlcr); - } -#endif writel(lcr, ®s->pl011_lcrh); return 0; } diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c index 411e5a0884..d1b6d15c8e 100644 --- a/drivers/usb/musb-new/musb_core.c +++ b/drivers/usb/musb-new/musb_core.c @@ -1550,7 +1550,7 @@ static int __devinit musb_core_init(u16 musb_type, struct musb *musb) /*-------------------------------------------------------------------------*/ #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ - defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) + defined(CONFIG_ARCH_OMAP4) static irqreturn_t generic_interrupt(int irq, void *__hci) { -- cgit v1.2.1 From 1e0f226362ffd2bd8c1a238af1d1b21ea86d3111 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 11 Sep 2015 03:24:34 -0700 Subject: dm: pci: Add an inline API to test if a device is on a PCI bus Introduce device_is_on_pci_bus() which can be utilized by driver to test if a device is on a PCI bus. Signed-off-by: Bin Meng Acked-by: Simon Glass --- drivers/pci/pci-uclass.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index ea70853da2..0756bbe8f1 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -238,7 +238,7 @@ int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, { struct udevice *bus; - for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;) + for (bus = dev; device_is_on_pci_bus(bus);) bus = bus->parent; return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size); } @@ -303,7 +303,7 @@ int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep, { struct udevice *bus; - for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;) + for (bus = dev; device_is_on_pci_bus(bus);) bus = bus->parent; return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep, size); -- cgit v1.2.1 From 8b7ee66cec950899eace0caf729cf2100155020a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 11 Sep 2015 03:24:35 -0700 Subject: net: designware: Add support to PCI designware devices The Designware ethernet controller is also seen on PCI bus, e.g. on Intel Quark SoC. Add this support in the DM version driver. Signed-off-by: Bin Meng Acked-by: Simon Glass --- drivers/net/designware.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'drivers') diff --git a/drivers/net/designware.c b/drivers/net/designware.c index ae78d21db6..6433896eec 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -558,6 +559,22 @@ static int designware_eth_write_hwaddr(struct udevice *dev) return _dw_write_hwaddr(priv, pdata->enetaddr); } +static int designware_eth_bind(struct udevice *dev) +{ +#ifdef CONFIG_DM_PCI + static int num_cards; + char name[20]; + + /* Create a unique device name for PCI type devices */ + if (device_is_on_pci_bus(dev)) { + sprintf(name, "eth_designware#%u", num_cards++); + device_set_name(dev, name); + } +#endif + + return 0; +} + static int designware_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); @@ -565,6 +582,23 @@ static int designware_eth_probe(struct udevice *dev) u32 iobase = pdata->iobase; int ret; +#ifdef CONFIG_DM_PCI + /* + * If we are on PCI bus, either directly attached to a PCI root port, + * or via a PCI bridge, fill in platdata before we probe the hardware. + */ + if (device_is_on_pci_bus(dev)) { + pci_dev_t bdf = pci_get_bdf(dev); + + dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); + iobase &= PCI_BASE_ADDRESS_MEM_MASK; + iobase = pci_mem_to_phys(bdf, iobase); + + pdata->iobase = iobase; + pdata->phy_interface = PHY_INTERFACE_MODE_RMII; + } +#endif + debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); priv->mac_regs_p = (struct eth_mac_regs *)iobase; priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET); @@ -617,10 +651,18 @@ U_BOOT_DRIVER(eth_designware) = { .id = UCLASS_ETH, .of_match = designware_eth_ids, .ofdata_to_platdata = designware_eth_ofdata_to_platdata, + .bind = designware_eth_bind, .probe = designware_eth_probe, .ops = &designware_eth_ops, .priv_auto_alloc_size = sizeof(struct dw_eth_dev), .platdata_auto_alloc_size = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; + +static struct pci_device_id supported[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, + { } +}; + +U_BOOT_PCI_DEVICE(eth_designware, supported); #endif -- cgit v1.2.1 From 8a5f6129d1450f5ff92a55cfcfd7b96ee019e303 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sun, 6 Sep 2015 01:44:50 +0900 Subject: pinctrl: move dm_scan_fdt_node() out of pinctrl uclass Commit c5acf4a2b3c6 ("pinctrl: Add the concept of peripheral IDs") added some additional change that was not mentioned in the git-log. That commit added dm_scan_fdt_node() in the pinctrl uclass binding. It should be handled by the simple-bus driver or the low-level driver, not by the pinctrl framework. I guess Simon's motivation was to bind GPIO banks located under the Rockchip pinctrl device. It is true some chips have sub-devices under their pinctrl devices, but it is basically SoC-specific matter. This commit partly reverts commit c5acf4a2b3c6 to keep the only pinctrl-generic features in the uclass. The dm_scan_fdt_node() should be called from the rk3288_pinctrl driver. Signed-off-by: Masahiro Yamada Acked-by: Simon Glass Tested-by: Simon Glass --- drivers/pinctrl/pinctrl-uclass.c | 15 +++++++++------ drivers/pinctrl/rockchip/pinctrl_rk3288.c | 8 ++++++++ 2 files changed, 17 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index 58001ef572..b5fdcd12a8 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -11,7 +11,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -160,8 +159,7 @@ static int pinctrl_select_state_full(struct udevice *dev, const char *statename) static int pinconfig_post_bind(struct udevice *dev) { - /* Scan the bus for devices */ - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); + return 0; } #endif @@ -249,10 +247,15 @@ static int pinctrl_post_bind(struct udevice *dev) } /* - * The pinctrl driver child nodes should be bound so that peripheral - * devices can easily search in parent devices during later DT-parsing. + * If set_state callback is set, we assume this pinctrl driver is the + * full implementation. In this case, its child nodes should be bound + * so that peripheral devices can easily search in parent devices + * during later DT-parsing. */ - return pinconfig_post_bind(dev); + if (ops->set_state) + return pinconfig_post_bind(dev); + + return 0; } UCLASS_DRIVER(pinctrl) = { diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c index 5205498b36..c432a008e7 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c @@ -17,6 +17,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -415,6 +416,12 @@ static struct pinctrl_ops rk3288_pinctrl_ops = { .get_periph_id = rk3288_pinctrl_get_periph_id, }; +static int rk3288_pinctrl_bind(struct udevice *dev) +{ + /* scan child GPIO banks */ + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); +} + static int rk3288_pinctrl_probe(struct udevice *dev) { struct rk3288_pinctrl_priv *priv = dev_get_priv(dev); @@ -437,5 +444,6 @@ U_BOOT_DRIVER(pinctrl_rk3288) = { .of_match = rk3288_pinctrl_ids, .priv_auto_alloc_size = sizeof(struct rk3288_pinctrl_priv), .ops = &rk3288_pinctrl_ops, + .bind = rk3288_pinctrl_bind, .probe = rk3288_pinctrl_probe, }; -- cgit v1.2.1 From 623d96e89aca64c2762150087f4e872c55481f13 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 14 Sep 2015 13:34:44 +0800 Subject: imx: wdog: correct wcr register settings We should not simple use "writew(WCR_WDE, &wdog->wcr)" to set wcr, since this will override bits set before reset_cpu. Use clrsetbits_le16 instead of writew to fix this issue. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Cc: Sebastian Siewior Tested-by: Fabio Estevam --- drivers/watchdog/imx_watchdog.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 1d18d4b269..9a77a54192 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -55,7 +55,8 @@ void reset_cpu(ulong addr) { struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; - writew(WCR_WDE, &wdog->wcr); + clrsetbits_le16(&wdog->wcr, 0, WCR_WDE); + writew(0x5555, &wdog->wsr); writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ while (1) { -- cgit v1.2.1 From 168617c9b547c4b1b24e7b4ce7078aa35a99efd2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Sep 2015 16:12:11 +0800 Subject: mtd: nand: mxs check maximum ecc that platfrom supports Check maximum ecc strength for each platfrom to avoid the calculated ecc exceed the limitation. Signed-off-by: Peng Fan Signed-off-by: Han Xu Tested-By: Tim Harvey Reviewed-by: Marek Vasut Acked-by: Scott Wood Cc: Stefano Babic --- drivers/mtd/nand/mxs_nand.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index 1d689015a5..f15cf36c88 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -149,6 +149,13 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size, uint32_t page_oob_size) { int ecc_strength; + int max_ecc_strength_supported; + + /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */ + if (is_cpu_type(MXC_CPU_MX6SX)) + max_ecc_strength_supported = 62; + else + max_ecc_strength_supported = 40; /* * Determine the ECC layout with the formula: @@ -162,7 +169,7 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size, / (galois_field * mxs_nand_ecc_chunk_cnt(page_data_size)); - return round_down(ecc_strength, 2); + return min(round_down(ecc_strength, 2), max_ecc_strength_supported); } static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size, -- cgit v1.2.1 From c4390486a6f198f82a5944eb1e123d9673331cf5 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:52:44 +0300 Subject: drivers/net/vsc9953: Remove 'CONFIG_' from macros' name Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index fed7358448..068ab8695b 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -202,26 +202,26 @@ void vsc9953_init(bd_t *bis) VSC9953_DEVCPU_GCB); out_le32(&l2dev_gcb->chip_regs.soft_rst, - CONFIG_VSC9953_SOFT_SWC_RST_ENA); + VSC9953_SOFT_SWC_RST_ENA); timeout = 50000; while ((in_le32(&l2dev_gcb->chip_regs.soft_rst) & - CONFIG_VSC9953_SOFT_SWC_RST_ENA) && --timeout) + VSC9953_SOFT_SWC_RST_ENA) && --timeout) udelay(1); /* busy wait for vsc9953 soft reset */ if (timeout == 0) debug("Timeout waiting for VSC9953 to reset\n"); - out_le32(&l2sys_reg->sys.reset_cfg, CONFIG_VSC9953_MEM_ENABLE | - CONFIG_VSC9953_MEM_INIT); + out_le32(&l2sys_reg->sys.reset_cfg, VSC9953_MEM_ENABLE | + VSC9953_MEM_INIT); timeout = 50000; while ((in_le32(&l2sys_reg->sys.reset_cfg) & - CONFIG_VSC9953_MEM_INIT) && --timeout) + VSC9953_MEM_INIT) && --timeout) udelay(1); /* busy wait for vsc9953 memory init */ if (timeout == 0) debug("Timeout waiting for VSC9953 memory to initialize\n"); out_le32(&l2sys_reg->sys.reset_cfg, (in_le32(&l2sys_reg->sys.reset_cfg) - | CONFIG_VSC9953_CORE_ENABLE)); + | VSC9953_CORE_ENABLE)); /* VSC9953 Setting to be done once only */ out_le32(&l2qsys_reg->sys.ext_cpu_cfg, 0x00000b00); @@ -233,34 +233,34 @@ void vsc9953_init(bd_t *bis) /* Enable VSC9953 GMII Ports Port ID 0 - 7 */ if (VSC9953_INTERNAL_PORT_CHECK(i)) { out_le32(&l2ana_reg->pfc[i].pfc_cfg, - CONFIG_VSC9953_PFC_FC_QSGMII); + VSC9953_PFC_FC_QSGMII); out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i], - CONFIG_VSC9953_MAC_FC_CFG_QSGMII); + VSC9953_MAC_FC_CFG_QSGMII); } else { out_le32(&l2ana_reg->pfc[i].pfc_cfg, - CONFIG_VSC9953_PFC_FC); + VSC9953_PFC_FC); out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i], - CONFIG_VSC9953_MAC_FC_CFG); + VSC9953_MAC_FC_CFG); } out_le32(&l2dev_gmii_reg->port_mode.clock_cfg, - CONFIG_VSC9953_CLOCK_CFG); + VSC9953_CLOCK_CFG); out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ena_cfg, - CONFIG_VSC9953_MAC_ENA_CFG); + VSC9953_MAC_ENA_CFG); out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_mode_cfg, - CONFIG_VSC9953_MAC_MODE_CFG); + VSC9953_MAC_MODE_CFG); out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ifg_cfg, - CONFIG_VSC9953_MAC_IFG_CFG); + VSC9953_MAC_IFG_CFG); /* mac_hdx_cfg varies with port id*/ - hdx_cfg = (CONFIG_VSC9953_MAC_HDX_CFG | (i << 16)); + hdx_cfg = VSC9953_MAC_HDX_CFG | (i << 16); out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_hdx_cfg, hdx_cfg); out_le32(&l2sys_reg->sys.front_port_mode[i], - CONFIG_VSC9953_FRONT_PORT_MODE); + VSC9953_FRONT_PORT_MODE); out_le32(&l2qsys_reg->sys.switch_port_mode[i], - CONFIG_VSC9953_PORT_ENA); + VSC9953_PORT_ENA); out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_maxlen_cfg, - CONFIG_VSC9953_MAC_MAX_LEN); + VSC9953_MAC_MAX_LEN); out_le32(&l2sys_reg->pause_cfg.pause_cfg[i], - CONFIG_VSC9953_PAUSE_CFG); + VSC9953_PAUSE_CFG); /* WAIT FOR 2 us*/ udelay(2); -- cgit v1.2.1 From 3cc8cfffb21b618a51a51e746aac709a12540b79 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:52:45 +0300 Subject: drivers/net/vsc9953: Cleanup patch This patch groups some macros defined for registers and replaces some magic numbers from vsc9953 with macros. Also, "port" and "port_nr" words are replaced with "port_no", puts each variable declaration on a line and removes unnecessary tabs. Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 144 +++++++++++++++++++++++++------------------------- 1 file changed, 73 insertions(+), 71 deletions(-) (limited to 'drivers') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 068ab8695b..524b979d52 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include static struct vsc9953_info vsc9953_l2sw = { @@ -25,50 +27,50 @@ static struct vsc9953_info vsc9953_l2sw = { .port[9] = VSC9953_PORT_INFO_INITIALIZER(9), }; -void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus) +void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus) { - if (!VSC9953_PORT_CHECK(port)) + if (!VSC9953_PORT_CHECK(port_no)) return; - vsc9953_l2sw.port[port].bus = bus; + vsc9953_l2sw.port[port_no].bus = bus; } -void vsc9953_port_info_set_phy_address(int port, int address) +void vsc9953_port_info_set_phy_address(int port_no, int address) { - if (!VSC9953_PORT_CHECK(port)) + if (!VSC9953_PORT_CHECK(port_no)) return; - vsc9953_l2sw.port[port].phyaddr = address; + vsc9953_l2sw.port[port_no].phyaddr = address; } -void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int) +void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int) { - if (!VSC9953_PORT_CHECK(port)) + if (!VSC9953_PORT_CHECK(port_no)) return; - vsc9953_l2sw.port[port].enet_if = phy_int; + vsc9953_l2sw.port[port_no].enet_if = phy_int; } -void vsc9953_port_enable(int port) +void vsc9953_port_enable(int port_no) { - if (!VSC9953_PORT_CHECK(port)) + if (!VSC9953_PORT_CHECK(port_no)) return; - vsc9953_l2sw.port[port].enabled = 1; + vsc9953_l2sw.port[port_no].enabled = 1; } -void vsc9953_port_disable(int port) +void vsc9953_port_disable(int port_no) { - if (!VSC9953_PORT_CHECK(port)) + if (!VSC9953_PORT_CHECK(port_no)) return; - vsc9953_l2sw.port[port].enabled = 0; + vsc9953_l2sw.port[port_no].enabled = 0; } static void vsc9953_mdio_write(struct vsc9953_mii_mng *phyregs, int port_addr, int regnum, int value) { - int timeout = 50000; + int timeout = 50000; out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) | ((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) | @@ -85,8 +87,8 @@ static void vsc9953_mdio_write(struct vsc9953_mii_mng *phyregs, int port_addr, static int vsc9953_mdio_read(struct vsc9953_mii_mng *phyregs, int port_addr, int regnum) { - int value = 0xFFFF; - int timeout = 50000; + int value = 0xFFFF; + int timeout = 50000; while ((in_le32(&phyregs->miimstatus) & MIIMIND_OPR_PEND) && --timeout) udelay(1); @@ -120,8 +122,8 @@ static int vsc9953_mdio_read(struct vsc9953_mii_mng *phyregs, int port_addr, static int init_phy(struct eth_device *dev) { - struct vsc9953_port_info *l2sw_port = dev->priv; - struct phy_device *phydev = NULL; + struct vsc9953_port_info *l2sw_port = dev->priv; + struct phy_device *phydev = NULL; #ifdef CONFIG_PHYLIB if (!l2sw_port->bus) @@ -148,21 +150,21 @@ static int init_phy(struct eth_device *dev) return 0; } -static int vsc9953_port_init(int port) +static int vsc9953_port_init(int port_no) { - struct eth_device *dev; + struct eth_device *dev; /* Internal ports never have a PHY */ - if (VSC9953_INTERNAL_PORT_CHECK(port)) + if (VSC9953_INTERNAL_PORT_CHECK(port_no)) return 0; /* alloc eth device */ dev = (struct eth_device *)calloc(1, sizeof(struct eth_device)); if (!dev) - return 1; + return -ENOMEM; - sprintf(dev->name, "SW@PORT%d", port); - dev->priv = &vsc9953_l2sw.port[port]; + sprintf(dev->name, "SW@PORT%d", port_no); + dev->priv = &vsc9953_l2sw.port[port_no]; dev->init = NULL; dev->halt = NULL; dev->send = NULL; @@ -170,7 +172,7 @@ static int vsc9953_port_init(int port) if (init_phy(dev)) { free(dev); - return 1; + return -ENODEV; } return 0; @@ -178,13 +180,15 @@ static int vsc9953_port_init(int port) void vsc9953_init(bd_t *bis) { - u32 i, hdx_cfg = 0, phy_addr = 0; - int timeout; - struct vsc9953_system_reg *l2sys_reg; - struct vsc9953_qsys_reg *l2qsys_reg; - struct vsc9953_dev_gmii *l2dev_gmii_reg; - struct vsc9953_analyzer *l2ana_reg; - struct vsc9953_devcpu_gcb *l2dev_gcb; + u32 i; + u32 hdx_cfg = 0; + u32 phy_addr = 0; + int timeout; + struct vsc9953_system_reg *l2sys_reg; + struct vsc9953_qsys_reg *l2qsys_reg; + struct vsc9953_dev_gmii *l2dev_gmii_reg; + struct vsc9953_analyzer *l2ana_reg; + struct vsc9953_devcpu_gcb *l2dev_gcb; l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(VSC9953_OFFSET + VSC9953_DEV_GMII_OFFSET); @@ -312,83 +316,81 @@ void vsc9953_init(bd_t *bis) #ifdef CONFIG_VSC9953_CMD /* Enable/disable status of a VSC9953 port */ -static void vsc9953_port_status_set(int port_nr, u8 enabled) +static void vsc9953_port_status_set(int port_no, u8 enabled) { - u32 val; - struct vsc9953_qsys_reg *l2qsys_reg; + struct vsc9953_qsys_reg *l2qsys_reg; /* Administrative down */ - if (vsc9953_l2sw.port[port_nr].enabled == 0) + if (!vsc9953_l2sw.port[port_no].enabled) return; l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + VSC9953_QSYS_OFFSET); - val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_nr]); - if (enabled == 1) - val |= (1 << 13); + if (enabled) + setbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], + VSC9953_PORT_ENA); else - val &= ~(1 << 13); - - out_le32(&l2qsys_reg->sys.switch_port_mode[port_nr], val); + clrbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], + VSC9953_PORT_ENA); } /* Set all VSC9953 ports' status */ static void vsc9953_port_all_status_set(u8 enabled) { - int i; + int i; for (i = 0; i < VSC9953_MAX_PORTS; i++) vsc9953_port_status_set(i, enabled); } /* Start autonegotiation for a VSC9953 PHY */ -static void vsc9953_phy_autoneg(int port_nr) +static void vsc9953_phy_autoneg(int port_no) { - if (!vsc9953_l2sw.port[port_nr].phydev) + if (!vsc9953_l2sw.port[port_no].phydev) return; - if (vsc9953_l2sw.port[port_nr].phydev->drv->startup( - vsc9953_l2sw.port[port_nr].phydev)) - printf("Failed to start PHY for port %d\n", port_nr); + if (vsc9953_l2sw.port[port_no].phydev->drv->startup( + vsc9953_l2sw.port[port_no].phydev)) + printf("Failed to start PHY for port %d\n", port_no); } /* Start autonegotiation for all VSC9953 PHYs */ static void vsc9953_phy_all_autoneg(void) { - int i; + int i; for (i = 0; i < VSC9953_MAX_PORTS; i++) vsc9953_phy_autoneg(i); } /* Print a VSC9953 port's configuration */ -static void vsc9953_port_config_show(int port) +static void vsc9953_port_config_show(int port_no) { - int speed; - int duplex; - int link; - u8 enabled; - u32 val; + int speed; + int duplex; + int link; + u8 enabled; + u32 val; struct vsc9953_qsys_reg *l2qsys_reg; l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + VSC9953_QSYS_OFFSET); - val = in_le32(&l2qsys_reg->sys.switch_port_mode[port]); - enabled = vsc9953_l2sw.port[port].enabled & - ((val & 0x00002000) >> 13); + val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_no]); + enabled = vsc9953_l2sw.port[port_no].enabled && + (val & VSC9953_PORT_ENA); /* internal ports (8 and 9) are fixed */ - if (VSC9953_INTERNAL_PORT_CHECK(port)) { + if (VSC9953_INTERNAL_PORT_CHECK(port_no)) { link = 1; speed = SPEED_2500; duplex = DUPLEX_FULL; } else { - if (vsc9953_l2sw.port[port].phydev) { - link = vsc9953_l2sw.port[port].phydev->link; - speed = vsc9953_l2sw.port[port].phydev->speed; - duplex = vsc9953_l2sw.port[port].phydev->duplex; + if (vsc9953_l2sw.port[port_no].phydev) { + link = vsc9953_l2sw.port[port_no].phydev->link; + speed = vsc9953_l2sw.port[port_no].phydev->speed; + duplex = vsc9953_l2sw.port[port_no].phydev->duplex; } else { link = -1; speed = -1; @@ -396,7 +398,7 @@ static void vsc9953_port_config_show(int port) } } - printf("%8d ", port); + printf("%8d ", port_no); printf("%8s ", enabled == 1 ? "enabled" : "disabled"); printf("%8s ", link == 1 ? "up" : "down"); @@ -426,7 +428,7 @@ static void vsc9953_port_config_show(int port) /* Print VSC9953 ports' configuration */ static void vsc9953_port_all_config_show(void) { - int i; + int i; for (i = 0; i < VSC9953_MAX_PORTS; i++) vsc9953_port_config_show(i); @@ -487,11 +489,11 @@ static int do_ethsw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD(ethsw, 5, 0, do_ethsw, "vsc9953 l2 switch commands", - "port enable|disable\n" + "port enable|disable\n" " - enable/disable an l2 switch port\n" - " port_nr=0..9; use \"all\" for all ports\n" - "ethsw port show\n" + " port_no=0..9; use \"all\" for all ports\n" + "ethsw port show\n" " - show an l2 switch port's configuration\n" - " port_nr=0..9; use \"all\" for all ports\n" + " port_no=0..9; use \"all\" for all ports\n" ); #endif /* CONFIG_VSC9953_CMD */ -- cgit v1.2.1 From fe91095b799d21428bd39392650ca0b06789776e Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:52:46 +0300 Subject: drivers/net/vsc9953: Fix bug when enabling a port When a port is enabled at init time, the initializing function touches more bits than necessary to enable a port (also touches reserved bits and default bit values). This patch fixes this issue by changing the value of the define used to enable the port and assures that no other bits are changes by replacing out_le32() with setbits_le32(). Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 524b979d52..2e8eec41f8 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -259,8 +259,8 @@ void vsc9953_init(bd_t *bis) out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_hdx_cfg, hdx_cfg); out_le32(&l2sys_reg->sys.front_port_mode[i], VSC9953_FRONT_PORT_MODE); - out_le32(&l2qsys_reg->sys.switch_port_mode[i], - VSC9953_PORT_ENA); + setbits_le32(&l2qsys_reg->sys.switch_port_mode[i], + VSC9953_PORT_ENA); out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_maxlen_cfg, VSC9953_MAC_MAX_LEN); out_le32(&l2sys_reg->pause_cfg.pause_cfg[i], -- cgit v1.2.1 From 9de059871f8364dd898faf0b6057b8fa69fa2728 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:26 +0300 Subject: drivers/net/vsc9953: Add default configuration for VSC9953 L2 Switch At startup, the default configuration should be: - enable HW learning on all ports (HW default); - all ports are VLAN aware; - all ports are members of VLAN 1; - all ports have Port-based VLAN 1; - on all ports, the switch is allowed to remove maximum one VLAN tag, - on egress, the switch should add a VLAN tag if the frame is classified to a different VLAN than the port's Port-based VLAN; Signed-off-by: Johnson Leung Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 253 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 253 insertions(+) (limited to 'drivers') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 2e8eec41f8..59e0fabbd9 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -178,6 +179,256 @@ static int vsc9953_port_init(int port_no) return 0; } +static int vsc9953_vlan_table_poll_idle(void) +{ + struct vsc9953_analyzer *l2ana_reg; + int timeout; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + timeout = 50000; + while (((in_le32(&l2ana_reg->ana_tables.vlan_access) & + VSC9953_VLAN_CMD_MASK) != VSC9953_VLAN_CMD_IDLE) && --timeout) + udelay(1); + + return timeout ? 0 : -EBUSY; +} + +/* vlan table set/clear all membership of vid */ +static void vsc9953_vlan_table_membership_all_set(int vid, int set_member) +{ + uint val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + /* read current vlan configuration */ + val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); + out_le32(&l2ana_reg->ana_tables.vlan_tidx, + bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid)); + + clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, + VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ); + + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); + out_le32(&l2ana_reg->ana_tables.vlan_tidx, + bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid)); + + clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, + VSC9953_VLAN_PORT_MASK | VSC9953_VLAN_CMD_MASK, + VSC9953_VLAN_CMD_WRITE | + (set_member ? VSC9953_VLAN_PORT_MASK : 0)); +} + +/* Set PVID for a VSC9953 port */ +static void vsc9953_port_vlan_pvid_set(int port_no, int pvid) +{ + uint val; + struct vsc9953_analyzer *l2ana_reg; + struct vsc9953_rew_reg *l2rew_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + + VSC9953_REW_OFFSET); + + /* Set PVID on ingress */ + val = in_le32(&l2ana_reg->port[port_no].vlan_cfg); + val = bitfield_replace_by_mask(val, VSC9953_VLAN_CFG_VID_MASK, pvid); + out_le32(&l2ana_reg->port[port_no].vlan_cfg, val); + + /* Set PVID on egress */ + val = in_le32(&l2rew_reg->port[port_no].port_vlan_cfg); + val = bitfield_replace_by_mask(val, VSC9953_PORT_VLAN_CFG_VID_MASK, + pvid); + out_le32(&l2rew_reg->port[port_no].port_vlan_cfg, val); +} + +static void vsc9953_port_all_vlan_pvid_set(int pvid) +{ + int i; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_pvid_set(i, pvid); +} + +/* Enable/disable vlan aware of a VSC9953 port */ +static void vsc9953_port_vlan_aware_set(int port_no, int enabled) +{ + struct vsc9953_analyzer *l2ana_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (enabled) + setbits_le32(&l2ana_reg->port[port_no].vlan_cfg, + VSC9953_VLAN_CFG_AWARE_ENA); + else + clrbits_le32(&l2ana_reg->port[port_no].vlan_cfg, + VSC9953_VLAN_CFG_AWARE_ENA); +} + +/* Set all VSC9953 ports' vlan aware */ +static void vsc9953_port_all_vlan_aware_set(int enabled) +{ + int i; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_aware_set(i, enabled); +} + +/* Enable/disable vlan pop count of a VSC9953 port */ +static void vsc9953_port_vlan_popcnt_set(int port_no, int popcnt) +{ + uint val; + struct vsc9953_analyzer *l2ana_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + if (popcnt > 3 || popcnt < 0) { + printf("Invalid pop count value: %d\n", port_no); + return; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + val = in_le32(&l2ana_reg->port[port_no].vlan_cfg); + val = bitfield_replace_by_mask(val, VSC9953_VLAN_CFG_POP_CNT_MASK, + popcnt); + out_le32(&l2ana_reg->port[port_no].vlan_cfg, val); +} + +/* Set all VSC9953 ports' pop count */ +static void vsc9953_port_all_vlan_poncnt_set(int popcnt) +{ + int i; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_popcnt_set(i, popcnt); +} + +/* Enable/disable learning for frames dropped due to ingress filtering */ +static void vsc9953_vlan_ingr_fltr_learn_drop(int enable) +{ + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (enable) + setbits_le32(&l2ana_reg->ana.adv_learn, VSC9953_VLAN_CHK); + else + clrbits_le32(&l2ana_reg->ana.adv_learn, VSC9953_VLAN_CHK); +} + +/* Egress untag modes of a VSC9953 port */ +enum egress_untag_mode { + EGRESS_UNTAG_ALL = 0, + EGRESS_UNTAG_PVID_AND_ZERO, + EGRESS_UNTAG_ZERO, + EGRESS_UNTAG_NONE, +}; + +static void vsc9953_port_vlan_egr_untag_set(int port_no, + enum egress_untag_mode mode) +{ + struct vsc9953_rew_reg *l2rew_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + + VSC9953_REW_OFFSET); + + switch (mode) { + case EGRESS_UNTAG_ALL: + clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_CFG_MASK, VSC9953_TAG_CFG_NONE); + break; + case EGRESS_UNTAG_PVID_AND_ZERO: + clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_CFG_MASK, + VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO); + break; + case EGRESS_UNTAG_ZERO: + clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_CFG_MASK, + VSC9953_TAG_CFG_ALL_BUT_ZERO); + break; + case EGRESS_UNTAG_NONE: + clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_CFG_MASK, VSC9953_TAG_CFG_ALL); + break; + default: + printf("Unknown untag mode for port %d\n", port_no); + } +} + +static void vsc9953_port_all_vlan_egress_untagged_set( + enum egress_untag_mode mode) +{ + int i; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_egr_untag_set(i, mode); +} + +/***************************************************************************** +At startup, the default configuration would be: + - HW learning enabled on all ports; (HW default) + - All ports are in VLAN 1; + - All ports are VLAN aware; + - All ports have POP_COUNT 1; + - All ports have PVID 1; + - All ports have TPID 0x8100; (HW default) + - All ports tag frames classified to all VLANs that are not PVID; +*****************************************************************************/ +void vsc9953_default_configuration(void) +{ + int i; + + for (i = 0; i < VSC9953_MAX_VLAN; i++) + vsc9953_vlan_table_membership_all_set(i, 0); + vsc9953_port_all_vlan_aware_set(1); + vsc9953_port_all_vlan_pvid_set(1); + vsc9953_port_all_vlan_poncnt_set(1); + vsc9953_vlan_table_membership_all_set(1, 1); + vsc9953_vlan_ingr_fltr_learn_drop(1); + vsc9953_port_all_vlan_egress_untagged_set(EGRESS_UNTAG_PVID_AND_ZERO); +} + void vsc9953_init(bd_t *bis) { u32 i; @@ -310,6 +561,8 @@ void vsc9953_init(bd_t *bis) } } + vsc9953_default_configuration(); + printf("VSC9953 L2 switch initialized\n"); return; } -- cgit v1.2.1 From 24a23deb90eea0acf049e226a70d8507394833c5 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:28 +0300 Subject: drivers/net/vsc9953: Use the generic Ethernet Switch parser This patch replaces the parser used by VSC9953 L2 Switch driver with the generic one. Also, the config macro that enables the VSC9953 commands has been replaced in all the platforms that use this driver with the config macro that corresponds to the generic parser. Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 349 ++++++++++++++++++++++++-------------------------- 1 file changed, 165 insertions(+), 184 deletions(-) (limited to 'drivers') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 59e0fabbd9..bf53535fb4 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -14,6 +14,7 @@ #include #include #include +#include static struct vsc9953_info vsc9953_l2sw = { .port[0] = VSC9953_PORT_INFO_INITIALIZER(0), @@ -405,6 +406,165 @@ static void vsc9953_port_all_vlan_egress_untagged_set( vsc9953_port_vlan_egr_untag_set(i, mode); } +#ifdef CONFIG_CMD_ETHSW + +/* Enable/disable status of a VSC9953 port */ +static void vsc9953_port_status_set(int port_no, u8 enabled) +{ + struct vsc9953_qsys_reg *l2qsys_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) + return; + + l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + + VSC9953_QSYS_OFFSET); + + if (enabled) + setbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], + VSC9953_PORT_ENA); + else + clrbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], + VSC9953_PORT_ENA); +} + +/* Start autonegotiation for a VSC9953 PHY */ +static void vsc9953_phy_autoneg(int port_no) +{ + if (!vsc9953_l2sw.port[port_no].phydev) + return; + + if (vsc9953_l2sw.port[port_no].phydev->drv->startup( + vsc9953_l2sw.port[port_no].phydev)) + printf("Failed to start PHY for port %d\n", port_no); +} + +/* Print a VSC9953 port's configuration */ +static void vsc9953_port_config_show(int port_no) +{ + int speed; + int duplex; + int link; + u8 enabled; + u32 val; + struct vsc9953_qsys_reg *l2qsys_reg; + + l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + + VSC9953_QSYS_OFFSET); + + val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_no]); + enabled = vsc9953_l2sw.port[port_no].enabled && + (val & VSC9953_PORT_ENA); + + /* internal ports (8 and 9) are fixed */ + if (VSC9953_INTERNAL_PORT_CHECK(port_no)) { + link = 1; + speed = SPEED_2500; + duplex = DUPLEX_FULL; + } else { + if (vsc9953_l2sw.port[port_no].phydev) { + link = vsc9953_l2sw.port[port_no].phydev->link; + speed = vsc9953_l2sw.port[port_no].phydev->speed; + duplex = vsc9953_l2sw.port[port_no].phydev->duplex; + } else { + link = -1; + speed = -1; + duplex = -1; + } + } + + printf("%8d ", port_no); + printf("%8s ", enabled == 1 ? "enabled" : "disabled"); + printf("%8s ", link == 1 ? "up" : "down"); + + switch (speed) { + case SPEED_10: + printf("%8d ", 10); + break; + case SPEED_100: + printf("%8d ", 100); + break; + case SPEED_1000: + printf("%8d ", 1000); + break; + case SPEED_2500: + printf("%8d ", 2500); + break; + case SPEED_10000: + printf("%8d ", 10000); + break; + default: + printf("%8s ", "-"); + } + + printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half"); +} + +static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + u8 enabled; + + /* Last keyword should tell us if we should enable/disable the port */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_enable) + enabled = 1; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_disable) + enabled = 0; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_status_set(parsed_cmd->port, enabled); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_status_set(i, enabled); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_port_config_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_phy_autoneg(parsed_cmd->port); + printf("%8s %8s %8s %8s %8s\n", + "Port", "Status", "Link", "Speed", + "Duplex"); + vsc9953_port_config_show(parsed_cmd->port); + + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_phy_autoneg(i); + printf("%8s %8s %8s %8s %8s\n", + "Port", "Status", "Link", "Speed", "Duplex"); + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_config_show(i); + } + + return CMD_RET_SUCCESS; +} + +static struct ethsw_command_func vsc9953_cmd_func = { + .ethsw_name = "L2 Switch VSC9953", + .port_enable = &vsc9953_port_status_key_func, + .port_disable = &vsc9953_port_status_key_func, + .port_show = &vsc9953_port_config_key_func, +}; + +#endif /* CONFIG_CMD_ETHSW */ + /***************************************************************************** At startup, the default configuration would be: - HW learning enabled on all ports; (HW default) @@ -563,190 +723,11 @@ void vsc9953_init(bd_t *bis) vsc9953_default_configuration(); +#ifdef CONFIG_CMD_ETHSW + if (ethsw_define_functions(&vsc9953_cmd_func) < 0) + debug("Unable to use \"ethsw\" commands\n"); +#endif + printf("VSC9953 L2 switch initialized\n"); return; } - -#ifdef CONFIG_VSC9953_CMD -/* Enable/disable status of a VSC9953 port */ -static void vsc9953_port_status_set(int port_no, u8 enabled) -{ - struct vsc9953_qsys_reg *l2qsys_reg; - - /* Administrative down */ - if (!vsc9953_l2sw.port[port_no].enabled) - return; - - l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + - VSC9953_QSYS_OFFSET); - - if (enabled) - setbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], - VSC9953_PORT_ENA); - else - clrbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], - VSC9953_PORT_ENA); -} - -/* Set all VSC9953 ports' status */ -static void vsc9953_port_all_status_set(u8 enabled) -{ - int i; - - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_status_set(i, enabled); -} - -/* Start autonegotiation for a VSC9953 PHY */ -static void vsc9953_phy_autoneg(int port_no) -{ - if (!vsc9953_l2sw.port[port_no].phydev) - return; - - if (vsc9953_l2sw.port[port_no].phydev->drv->startup( - vsc9953_l2sw.port[port_no].phydev)) - printf("Failed to start PHY for port %d\n", port_no); -} - -/* Start autonegotiation for all VSC9953 PHYs */ -static void vsc9953_phy_all_autoneg(void) -{ - int i; - - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_phy_autoneg(i); -} - -/* Print a VSC9953 port's configuration */ -static void vsc9953_port_config_show(int port_no) -{ - int speed; - int duplex; - int link; - u8 enabled; - u32 val; - struct vsc9953_qsys_reg *l2qsys_reg; - - l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + - VSC9953_QSYS_OFFSET); - - val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_no]); - enabled = vsc9953_l2sw.port[port_no].enabled && - (val & VSC9953_PORT_ENA); - - /* internal ports (8 and 9) are fixed */ - if (VSC9953_INTERNAL_PORT_CHECK(port_no)) { - link = 1; - speed = SPEED_2500; - duplex = DUPLEX_FULL; - } else { - if (vsc9953_l2sw.port[port_no].phydev) { - link = vsc9953_l2sw.port[port_no].phydev->link; - speed = vsc9953_l2sw.port[port_no].phydev->speed; - duplex = vsc9953_l2sw.port[port_no].phydev->duplex; - } else { - link = -1; - speed = -1; - duplex = -1; - } - } - - printf("%8d ", port_no); - printf("%8s ", enabled == 1 ? "enabled" : "disabled"); - printf("%8s ", link == 1 ? "up" : "down"); - - switch (speed) { - case SPEED_10: - printf("%8d ", 10); - break; - case SPEED_100: - printf("%8d ", 100); - break; - case SPEED_1000: - printf("%8d ", 1000); - break; - case SPEED_2500: - printf("%8d ", 2500); - break; - case SPEED_10000: - printf("%8d ", 10000); - break; - default: - printf("%8s ", "-"); - } - - printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half"); -} - -/* Print VSC9953 ports' configuration */ -static void vsc9953_port_all_config_show(void) -{ - int i; - - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_config_show(i); -} - -/* function to interpret commands starting with "ethsw " */ -static int do_ethsw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - u8 enable; - u32 port; - - if (argc < 4) - return -1; - - if (strcmp(argv[1], "port")) - return -1; - - if (!strcmp(argv[3], "show")) { - if (!strcmp(argv[2], "all")) { - vsc9953_phy_all_autoneg(); - printf("%8s %8s %8s %8s %8s\n", - "Port", "Status", "Link", "Speed", - "Duplex"); - vsc9953_port_all_config_show(); - return 0; - } else { - port = simple_strtoul(argv[2], NULL, 10); - if (!VSC9953_PORT_CHECK(port)) - return -1; - vsc9953_phy_autoneg(port); - printf("%8s %8s %8s %8s %8s\n", - "Port", "Status", "Link", "Speed", - "Duplex"); - vsc9953_port_config_show(port); - return 0; - } - } else if (!strcmp(argv[3], "enable")) { - enable = 1; - } else if (!strcmp(argv[3], "disable")) { - enable = 0; - } else { - return -1; - } - - if (!strcmp(argv[2], "all")) { - vsc9953_port_all_status_set(enable); - return 0; - } else { - port = simple_strtoul(argv[2], NULL, 10); - if (!VSC9953_PORT_CHECK(port)) - return -1; - vsc9953_port_status_set(port, enable); - return 0; - } - - return -1; -} - -U_BOOT_CMD(ethsw, 5, 0, do_ethsw, - "vsc9953 l2 switch commands", - "port enable|disable\n" - " - enable/disable an l2 switch port\n" - " port_no=0..9; use \"all\" for all ports\n" - "ethsw port show\n" - " - show an l2 switch port's configuration\n" - " port_no=0..9; use \"all\" for all ports\n" -); -#endif /* CONFIG_VSC9953_CMD */ -- cgit v1.2.1 From 86719f0cd55bc13186798217b08fa6a048eda27c Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:29 +0300 Subject: drivers/net/vsc9953: Add command to show/clear port counters The new added command: ethsw [port ] statistics { [help] | [clear] } will print counters like the number of Rx/Tx frames, number of Rx/Tx bytes, number of Rx/Tx unicast frames, etc. This patch also adds this commnd in the genereric ethsw parser from cmd_ethsw.c Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 256 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 256 insertions(+) (limited to 'drivers') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index bf53535fb4..1dddb44c8b 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -500,6 +500,223 @@ static void vsc9953_port_config_show(int port_no) printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half"); } +/* Show VSC9953 ports' statistics */ +static void vsc9953_port_statistics_show(int port_no) +{ + u32 rx_val; + u32 tx_val; + struct vsc9953_system_reg *l2sys_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET + + VSC9953_SYS_OFFSET); + + printf("Statistics for L2 Switch port %d:\n", port_no); + + /* Set counter view for our port */ + out_le32(&l2sys_reg->sys.stat_cfg, port_no); + +#define VSC9953_STATS_PRINTF "%-15s %10u" + + /* Get number of Rx and Tx frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_short) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_frag) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_jabber) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_long) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_64) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_65_127) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_128_255) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_256_511) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_512_1023) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_1024_1526) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_jumbo); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx frames:", rx_val, "Tx frames:", tx_val); + + /* Get number of Rx and Tx bytes */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_oct); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_oct); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx bytes:", rx_val, "Tx bytes:", tx_val); + + /* Get number of Rx frames received ok and Tx frames sent ok */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_0) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_1) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_2) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_3) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_4) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_5) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_6) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_7) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_0) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_1) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_2) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_3) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_4) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_5) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_6) + + in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_7); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx frames ok:", rx_val, "Tx frames ok:", tx_val); + + /* Get number of Rx and Tx unicast frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_uc); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_uc); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx unicast:", rx_val, "Tx unicast:", tx_val); + + /* Get number of Rx and Tx broadcast frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_bc); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_bc); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx broadcast:", rx_val, "Tx broadcast:", tx_val); + + /* Get number of Rx and Tx frames of 64B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_64); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 64B:", rx_val, "Tx 64B:", tx_val); + + /* Get number of Rx and Tx frames with sizes between 65B and 127B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_65_127); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 65B-127B:", rx_val, "Tx 65B-127B:", tx_val); + + /* Get number of Rx and Tx frames with sizes between 128B and 255B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_128_255); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 128B-255B:", rx_val, "Tx 128B-255B:", tx_val); + + /* Get number of Rx and Tx frames with sizes between 256B and 511B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_256_511); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 256B-511B:", rx_val, "Tx 256B-511B:", tx_val); + + /* Get number of Rx and Tx frames with sizes between 512B and 1023B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_512_1023); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 512B-1023B:", rx_val, "Tx 512B-1023B:", tx_val); + + /* Get number of Rx and Tx frames with sizes between 1024B and 1526B */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_1024_1526); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx 1024B-1526B:", rx_val, "Tx 1024B-1526B:", tx_val); + + /* Get number of Rx and Tx jumbo frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_jumbo); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx jumbo:", rx_val, "Tx jumbo:", tx_val); + + /* Get number of Rx and Tx dropped frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_cat_drop) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_tail) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_0) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_1) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_2) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_3) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_4) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_5) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_6) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_7) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_0) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_1) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_2) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_3) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_4) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_5) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_6) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_7); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_drop) + + in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_aged); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx drops:", rx_val, "Tx drops:", tx_val); + + /* + * Get number of Rx frames with CRC or alignment errors + * and number of detected Tx collisions + */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_crc); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_col); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx CRC&align:", rx_val, "Tx coll:", tx_val); + + /* + * Get number of Rx undersized frames and + * number of Tx aged frames + */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_short); + tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_aged); + printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", + "Rx undersize:", rx_val, "Tx aged:", tx_val); + + /* Get number of Rx oversized frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_long); + printf(VSC9953_STATS_PRINTF"\n", "Rx oversized:", rx_val); + + /* Get number of Rx fragmented frames */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_frag); + printf(VSC9953_STATS_PRINTF"\n", "Rx fragments:", rx_val); + + /* Get number of Rx jabber errors */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_jabber); + printf(VSC9953_STATS_PRINTF"\n", "Rx jabbers:", rx_val); + + /* + * Get number of Rx frames filtered due to classification rules or + * no destination ports + */ + rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_cat_drop) + + in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_local); + printf(VSC9953_STATS_PRINTF"\n", "Rx filtered:", rx_val); + + printf("\n"); +} + +/* Clear statistics for a VSC9953 port */ +static void vsc9953_port_statistics_clear(int port_no) +{ + struct vsc9953_system_reg *l2sys_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET + + VSC9953_SYS_OFFSET); + + /* Clear all counter groups for our ports */ + out_le32(&l2sys_reg->sys.stat_cfg, port_no | + VSC9953_STAT_CLEAR_RX | VSC9953_STAT_CLEAR_TX | + VSC9953_STAT_CLEAR_DR); +} + static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) { int i; @@ -556,11 +773,50 @@ static int vsc9953_port_config_key_func(struct ethsw_command_def *parsed_cmd) return CMD_RET_SUCCESS; } +static int vsc9953_port_stats_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_statistics_show(parsed_cmd->port); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_statistics_show(i); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_port_stats_clear_key_func(struct ethsw_command_def + *parsed_cmd) +{ + int i; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_statistics_clear(parsed_cmd->port); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_statistics_clear(i); + } + + return CMD_RET_SUCCESS; +} + static struct ethsw_command_func vsc9953_cmd_func = { .ethsw_name = "L2 Switch VSC9953", .port_enable = &vsc9953_port_status_key_func, .port_disable = &vsc9953_port_status_key_func, .port_show = &vsc9953_port_config_key_func, + .port_stats = &vsc9953_port_stats_key_func, + .port_stats_clear = &vsc9953_port_stats_clear_key_func, }; #endif /* CONFIG_CMD_ETHSW */ -- cgit v1.2.1 From 68c929da6bf754ace639b2159e2d5b9e22323aaa Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:30 +0300 Subject: drivers/net/vsc9953: Add commands to enable/disable HW learning The command: ethsw [port ] learning { [help] | show | auto | disable } can be used to enable/disable HW learning on a port. This patch also adds this command to the generic ethsw parser from cmd_ethsw. Signed-off-by: Johnson Leung Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 141 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) (limited to 'drivers') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 1dddb44c8b..21b14e6a19 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -717,6 +717,72 @@ static void vsc9953_port_statistics_clear(int port_no) VSC9953_STAT_CLEAR_DR); } +enum port_learn_mode { + PORT_LEARN_NONE, + PORT_LEARN_AUTO +}; + +/* Set learning configuration for a VSC9953 port */ +static void vsc9953_port_learn_mode_set(int port_no, enum port_learn_mode mode) +{ + struct vsc9953_analyzer *l2ana_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + switch (mode) { + case PORT_LEARN_NONE: + clrbits_le32(&l2ana_reg->port[port_no].port_cfg, + VSC9953_PORT_CFG_LEARN_DROP | + VSC9953_PORT_CFG_LEARN_CPU | + VSC9953_PORT_CFG_LEARN_AUTO | + VSC9953_PORT_CFG_LEARN_ENA); + break; + case PORT_LEARN_AUTO: + clrsetbits_le32(&l2ana_reg->port[port_no].port_cfg, + VSC9953_PORT_CFG_LEARN_DROP | + VSC9953_PORT_CFG_LEARN_CPU, + VSC9953_PORT_CFG_LEARN_ENA | + VSC9953_PORT_CFG_LEARN_AUTO); + break; + default: + printf("Unknown learn mode for port %d\n", port_no); + } +} + +/* Get learning configuration for a VSC9953 port */ +static int vsc9953_port_learn_mode_get(int port_no, enum port_learn_mode *mode) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return -1; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* For now we only support HW learning (auto) and no learning */ + val = in_le32(&l2ana_reg->port[port_no].port_cfg); + if ((val & (VSC9953_PORT_CFG_LEARN_ENA | + VSC9953_PORT_CFG_LEARN_AUTO)) == + (VSC9953_PORT_CFG_LEARN_ENA | VSC9953_PORT_CFG_LEARN_AUTO)) + *mode = PORT_LEARN_AUTO; + else + *mode = PORT_LEARN_NONE; + + return 0; +} + static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) { int i; @@ -810,6 +876,79 @@ static int vsc9953_port_stats_clear_key_func(struct ethsw_command_def return CMD_RET_SUCCESS; } +static int vsc9953_learn_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + enum port_learn_mode mode; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + if (vsc9953_port_learn_mode_get(parsed_cmd->port, &mode)) + return CMD_RET_FAILURE; + printf("%7s %11s\n", "Port", "Learn mode"); + switch (mode) { + case PORT_LEARN_NONE: + printf("%7d %11s\n", parsed_cmd->port, "disable"); + break; + case PORT_LEARN_AUTO: + printf("%7d %11s\n", parsed_cmd->port, "auto"); + break; + default: + printf("%7d %11s\n", parsed_cmd->port, "-"); + } + } else { + printf("%7s %11s\n", "Port", "Learn mode"); + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (vsc9953_port_learn_mode_get(i, &mode)) + continue; + switch (mode) { + case PORT_LEARN_NONE: + printf("%7d %11s\n", i, "disable"); + break; + case PORT_LEARN_AUTO: + printf("%7d %11s\n", i, "auto"); + break; + default: + printf("%7d %11s\n", i, "-"); + } + } + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_learn_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + enum port_learn_mode mode; + + /* Last keyword should tell us the learn mode */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_auto) + mode = PORT_LEARN_AUTO; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_disable) + mode = PORT_LEARN_NONE; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_learn_mode_set(parsed_cmd->port, mode); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_learn_mode_set(i, mode); + } + + return CMD_RET_SUCCESS; +} + static struct ethsw_command_func vsc9953_cmd_func = { .ethsw_name = "L2 Switch VSC9953", .port_enable = &vsc9953_port_status_key_func, @@ -817,6 +956,8 @@ static struct ethsw_command_func vsc9953_cmd_func = { .port_show = &vsc9953_port_config_key_func, .port_stats = &vsc9953_port_stats_key_func, .port_stats_clear = &vsc9953_port_stats_clear_key_func, + .port_learn = &vsc9953_learn_set_key_func, + .port_learn_show = &vsc9953_learn_show_key_func, }; #endif /* CONFIG_CMD_ETHSW */ -- cgit v1.2.1 From 22449858f8eae3f03399f76b4a982dd2f0d4df00 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Wed, 9 Sep 2015 18:00:52 +0300 Subject: drivers/net/vsc9953: Add commands to manipulate the FDB for VSC9953 The new command: ethsw [port ] [vlan ] fdb { [help] | show | flush | { add | del } } Can be used to add and delete FDB entries. Also, the command can be used to show entries from the FDB tables. When used with [port ] and [vlan ], only the matching the FDB entries can be seen or flushed. The command has also been added to the generic ethsw parser from cmd_ethsw.c. Signed-off-by: Johnson Leung Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 472 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 472 insertions(+) (limited to 'drivers') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 21b14e6a19..071906c1fb 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -783,6 +783,389 @@ static int vsc9953_port_learn_mode_get(int port_no, enum port_learn_mode *mode) return 0; } +/* wait for FDB to become available */ +static int vsc9953_mac_table_poll_idle(void) +{ + struct vsc9953_analyzer *l2ana_reg; + u32 timeout; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + timeout = 50000; + while (((in_le32(&l2ana_reg->ana_tables.mac_access) & + VSC9953_MAC_CMD_MASK) != + VSC9953_MAC_CMD_IDLE) && --timeout) + udelay(1); + + return timeout ? 0 : -EBUSY; +} + +/* enum describing available commands for the MAC table */ +enum mac_table_cmd { + MAC_TABLE_READ, + MAC_TABLE_LOOKUP, + MAC_TABLE_WRITE, + MAC_TABLE_LEARN, + MAC_TABLE_FORGET, + MAC_TABLE_GET_NEXT, + MAC_TABLE_AGE, +}; + +/* Issues a command to the FDB table */ +static int vsc9953_mac_table_cmd(enum mac_table_cmd cmd) +{ + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + switch (cmd) { + case MAC_TABLE_READ: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | VSC9953_MAC_CMD_VALID, + VSC9953_MAC_CMD_READ); + break; + case MAC_TABLE_LOOKUP: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK, VSC9953_MAC_CMD_READ | + VSC9953_MAC_CMD_VALID); + break; + case MAC_TABLE_WRITE: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | + VSC9953_MAC_ENTRYTYPE_MASK, + VSC9953_MAC_CMD_WRITE | + VSC9953_MAC_ENTRYTYPE_LOCKED); + break; + case MAC_TABLE_LEARN: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | + VSC9953_MAC_ENTRYTYPE_MASK, + VSC9953_MAC_CMD_LEARN | + VSC9953_MAC_ENTRYTYPE_LOCKED | + VSC9953_MAC_CMD_VALID); + break; + case MAC_TABLE_FORGET: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | + VSC9953_MAC_ENTRYTYPE_MASK, + VSC9953_MAC_CMD_FORGET); + break; + case MAC_TABLE_GET_NEXT: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | + VSC9953_MAC_ENTRYTYPE_MASK, + VSC9953_MAC_CMD_NEXT); + break; + case MAC_TABLE_AGE: + clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, + VSC9953_MAC_CMD_MASK | + VSC9953_MAC_ENTRYTYPE_MASK, + VSC9953_MAC_CMD_AGE); + break; + default: + printf("Unknown MAC table command\n"); + } + + if (vsc9953_mac_table_poll_idle() < 0) { + debug("MAC table timeout\n"); + return -1; + } + + return 0; +} + +/* show the FDB entries that correspond to a port and a VLAN */ +static void vsc9953_mac_table_show(int port_no, int vid) +{ + int rc[VSC9953_MAX_PORTS]; + enum port_learn_mode mode[VSC9953_MAX_PORTS]; + int i; + u32 val; + u32 vlan; + u32 mach; + u32 macl; + u32 dest_indx; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* disable auto learning */ + if (port_no == ETHSW_CMD_PORT_ALL) { + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + rc[i] = vsc9953_port_learn_mode_get(i, &mode[i]); + if (!rc[i] && mode[i] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(i, PORT_LEARN_NONE); + } + } else { + rc[port_no] = vsc9953_port_learn_mode_get(port_no, + &mode[port_no]); + if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(port_no, PORT_LEARN_NONE); + } + + /* write port and vid to get selected FDB entries */ + val = in_le32(&l2ana_reg->ana.anag_efil); + if (port_no != ETHSW_CMD_PORT_ALL) { + val = bitfield_replace_by_mask(val, VSC9953_AGE_PORT_MASK, + port_no) | VSC9953_AGE_PORT_EN; + } + if (vid != ETHSW_CMD_VLAN_ALL) { + val = bitfield_replace_by_mask(val, VSC9953_AGE_VID_MASK, + vid) | VSC9953_AGE_VID_EN; + } + out_le32(&l2ana_reg->ana.anag_efil, val); + + /* set MAC and VLAN to 0 to look from beginning */ + clrbits_le32(&l2ana_reg->ana_tables.mach_data, + VSC9953_MAC_VID_MASK | VSC9953_MAC_MACH_MASK); + out_le32(&l2ana_reg->ana_tables.macl_data, 0); + + /* get entries */ + printf("%10s %17s %5s %4s\n", "EntryType", "MAC", "PORT", "VID"); + do { + if (vsc9953_mac_table_cmd(MAC_TABLE_GET_NEXT) < 0) { + debug("GET NEXT MAC table command failed\n"); + break; + } + + val = in_le32(&l2ana_reg->ana_tables.mac_access); + + /* get out when an invalid entry is found */ + if (!(val & VSC9953_MAC_CMD_VALID)) + break; + + switch (val & VSC9953_MAC_ENTRYTYPE_MASK) { + case VSC9953_MAC_ENTRYTYPE_NORMAL: + printf("%10s ", "Dynamic"); + break; + case VSC9953_MAC_ENTRYTYPE_LOCKED: + printf("%10s ", "Static"); + break; + case VSC9953_MAC_ENTRYTYPE_IPV4MCAST: + printf("%10s ", "IPv4 Mcast"); + break; + case VSC9953_MAC_ENTRYTYPE_IPV6MCAST: + printf("%10s ", "IPv6 Mcast"); + break; + default: + printf("%10s ", "Unknown"); + } + + dest_indx = bitfield_extract_by_mask(val, + VSC9953_MAC_DESTIDX_MASK); + + val = in_le32(&l2ana_reg->ana_tables.mach_data); + vlan = bitfield_extract_by_mask(val, VSC9953_MAC_VID_MASK); + mach = bitfield_extract_by_mask(val, VSC9953_MAC_MACH_MASK); + macl = in_le32(&l2ana_reg->ana_tables.macl_data); + + printf("%02x:%02x:%02x:%02x:%02x:%02x ", (mach >> 8) & 0xff, + mach & 0xff, (macl >> 24) & 0xff, (macl >> 16) & 0xff, + (macl >> 8) & 0xff, macl & 0xff); + printf("%5d ", dest_indx); + printf("%4d\n", vlan); + } while (1); + + /* set learning mode to previous value */ + if (port_no == ETHSW_CMD_PORT_ALL) { + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (!rc[i] && mode[i] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(i, mode[i]); + } + } else { + /* If administrative down, skip */ + if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(port_no, mode[port_no]); + } + + /* reset FDB port and VLAN FDB selection */ + clrbits_le32(&l2ana_reg->ana.anag_efil, VSC9953_AGE_PORT_EN | + VSC9953_AGE_PORT_MASK | VSC9953_AGE_VID_EN | + VSC9953_AGE_VID_MASK); +} + +/* Add a static FDB entry */ +static int vsc9953_mac_table_add(u8 port_no, uchar mac[6], int vid) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + val = in_le32(&l2ana_reg->ana_tables.mach_data); + val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | + (mac[0] << 8) | (mac[1] << 0); + out_le32(&l2ana_reg->ana_tables.mach_data, val); + + out_le32(&l2ana_reg->ana_tables.macl_data, + (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | + (mac[5] << 0)); + + /* set on which port is the MAC address added */ + val = in_le32(&l2ana_reg->ana_tables.mac_access); + val = bitfield_replace_by_mask(val, VSC9953_MAC_DESTIDX_MASK, port_no); + out_le32(&l2ana_reg->ana_tables.mac_access, val); + + if (vsc9953_mac_table_cmd(MAC_TABLE_LEARN) < 0) + return -1; + + /* check if the MAC address was indeed added */ + val = in_le32(&l2ana_reg->ana_tables.mach_data); + val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | + (mac[0] << 8) | (mac[1] << 0); + out_le32(&l2ana_reg->ana_tables.mach_data, val); + + out_le32(&l2ana_reg->ana_tables.macl_data, + (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | + (mac[5] << 0)); + + if (vsc9953_mac_table_cmd(MAC_TABLE_READ) < 0) + return -1; + + val = in_le32(&l2ana_reg->ana_tables.mac_access); + + if ((port_no != bitfield_extract_by_mask(val, + VSC9953_MAC_DESTIDX_MASK))) { + printf("Failed to add MAC address\n"); + return -1; + } + return 0; +} + +/* Delete a FDB entry */ +static int vsc9953_mac_table_del(uchar mac[6], u16 vid) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* check first if MAC entry is present */ + val = in_le32(&l2ana_reg->ana_tables.mach_data); + val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | + (mac[0] << 8) | (mac[1] << 0); + out_le32(&l2ana_reg->ana_tables.mach_data, val); + + out_le32(&l2ana_reg->ana_tables.macl_data, + (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | + (mac[5] << 0)); + + if (vsc9953_mac_table_cmd(MAC_TABLE_LOOKUP) < 0) { + debug("Lookup in the MAC table failed\n"); + return -1; + } + + if (!(in_le32(&l2ana_reg->ana_tables.mac_access) & + VSC9953_MAC_CMD_VALID)) { + printf("The MAC address: %02x:%02x:%02x:%02x:%02x:%02x ", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + printf("VLAN: %d does not exist.\n", vid); + return -1; + } + + /* FDB entry found, proceed to delete */ + val = in_le32(&l2ana_reg->ana_tables.mach_data); + val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | + (mac[0] << 8) | (mac[1] << 0); + out_le32(&l2ana_reg->ana_tables.mach_data, val); + + out_le32(&l2ana_reg->ana_tables.macl_data, (mac[2] << 24) | + (mac[3] << 16) | (mac[4] << 8) | (mac[5] << 0)); + + if (vsc9953_mac_table_cmd(MAC_TABLE_FORGET) < 0) + return -1; + + /* check if the MAC entry is still in FDB */ + val = in_le32(&l2ana_reg->ana_tables.mach_data); + val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | + (mac[0] << 8) | (mac[1] << 0); + out_le32(&l2ana_reg->ana_tables.mach_data, val); + + out_le32(&l2ana_reg->ana_tables.macl_data, (mac[2] << 24) | + (mac[3] << 16) | (mac[4] << 8) | (mac[5] << 0)); + + if (vsc9953_mac_table_cmd(MAC_TABLE_LOOKUP) < 0) { + debug("Lookup in the MAC table failed\n"); + return -1; + } + if (in_le32(&l2ana_reg->ana_tables.mac_access) & + VSC9953_MAC_CMD_VALID) { + printf("Failed to delete MAC address\n"); + return -1; + } + + return 0; +} + +/* age the unlocked entries in FDB */ +static void vsc9953_mac_table_age(int port_no, int vid) +{ + int rc[VSC9953_MAX_PORTS]; + enum port_learn_mode mode[VSC9953_MAX_PORTS]; + u32 val; + int i; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* set port and VID for selective aging */ + val = in_le32(&l2ana_reg->ana.anag_efil); + if (port_no != ETHSW_CMD_PORT_ALL) { + /* disable auto learning */ + rc[port_no] = vsc9953_port_learn_mode_get(port_no, + &mode[port_no]); + if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(port_no, PORT_LEARN_NONE); + + val = bitfield_replace_by_mask(val, VSC9953_AGE_PORT_MASK, + port_no) | VSC9953_AGE_PORT_EN; + } else { + /* disable auto learning on all ports */ + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + rc[i] = vsc9953_port_learn_mode_get(i, &mode[i]); + if (!rc[i] && mode[i] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(i, PORT_LEARN_NONE); + } + } + + if (vid != ETHSW_CMD_VLAN_ALL) { + val = bitfield_replace_by_mask(val, VSC9953_AGE_VID_MASK, vid) | + VSC9953_AGE_VID_EN; + } + out_le32(&l2ana_reg->ana.anag_efil, val); + + /* age the dynamic FDB entries */ + vsc9953_mac_table_cmd(MAC_TABLE_AGE); + + /* clear previously set port and VID */ + clrbits_le32(&l2ana_reg->ana.anag_efil, VSC9953_AGE_PORT_EN | + VSC9953_AGE_PORT_MASK | VSC9953_AGE_VID_EN | + VSC9953_AGE_VID_MASK); + + if (port_no != ETHSW_CMD_PORT_ALL) { + if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(port_no, mode[port_no]); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (!rc[i] && mode[i] != PORT_LEARN_NONE) + vsc9953_port_learn_mode_set(i, mode[i]); + } + } +} + +/* Delete all the dynamic FDB entries */ +static void vsc9953_mac_table_flush(int port, int vid) +{ + vsc9953_mac_table_age(port, vid); + vsc9953_mac_table_age(port, vid); +} + static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) { int i; @@ -949,6 +1332,91 @@ static int vsc9953_learn_set_key_func(struct ethsw_command_def *parsed_cmd) return CMD_RET_SUCCESS; } +static int vsc9953_fdb_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL && + !VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + + if (parsed_cmd->vid != ETHSW_CMD_VLAN_ALL && + !VSC9953_VLAN_CHECK(parsed_cmd->vid)) { + printf("Invalid VID number: %d\n", parsed_cmd->vid); + return CMD_RET_FAILURE; + } + + vsc9953_mac_table_show(parsed_cmd->port, parsed_cmd->vid); + + return CMD_RET_SUCCESS; +} + +static int vsc9953_fdb_flush_key_func(struct ethsw_command_def *parsed_cmd) +{ + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL && + !VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + + if (parsed_cmd->vid != ETHSW_CMD_VLAN_ALL && + !VSC9953_VLAN_CHECK(parsed_cmd->vid)) { + printf("Invalid VID number: %d\n", parsed_cmd->vid); + return CMD_RET_FAILURE; + } + + vsc9953_mac_table_flush(parsed_cmd->port, parsed_cmd->vid); + + return CMD_RET_SUCCESS; +} + +static int vsc9953_fdb_entry_add_key_func(struct ethsw_command_def *parsed_cmd) +{ + int vid; + + /* a port number must be present */ + if (parsed_cmd->port == ETHSW_CMD_PORT_ALL) { + printf("Please specify a port\n"); + return CMD_RET_FAILURE; + } + + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + + /* Use VLAN 1 if VID is not set */ + vid = (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL ? 1 : parsed_cmd->vid); + + if (!VSC9953_VLAN_CHECK(vid)) { + printf("Invalid VID number: %d\n", vid); + return CMD_RET_FAILURE; + } + + if (vsc9953_mac_table_add(parsed_cmd->port, parsed_cmd->ethaddr, vid)) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static int vsc9953_fdb_entry_del_key_func(struct ethsw_command_def *parsed_cmd) +{ + int vid; + + /* Use VLAN 1 if VID is not set */ + vid = (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL ? 1 : parsed_cmd->vid); + + if (!VSC9953_VLAN_CHECK(vid)) { + printf("Invalid VID number: %d\n", vid); + return CMD_RET_FAILURE; + } + + if (vsc9953_mac_table_del(parsed_cmd->ethaddr, vid)) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + static struct ethsw_command_func vsc9953_cmd_func = { .ethsw_name = "L2 Switch VSC9953", .port_enable = &vsc9953_port_status_key_func, @@ -958,6 +1426,10 @@ static struct ethsw_command_func vsc9953_cmd_func = { .port_stats_clear = &vsc9953_port_stats_clear_key_func, .port_learn = &vsc9953_learn_set_key_func, .port_learn_show = &vsc9953_learn_show_key_func, + .fdb_show = &vsc9953_fdb_show_key_func, + .fdb_flush = &vsc9953_fdb_flush_key_func, + .fdb_entry_add = &vsc9953_fdb_entry_add_key_func, + .fdb_entry_del = &vsc9953_fdb_entry_del_key_func, }; #endif /* CONFIG_CMD_ETHSW */ -- cgit v1.2.1 From a2477924cd302cfae730ebefb431814eb99ad861 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:33 +0300 Subject: drivers/net/vsc9953: Add VLAN commands for VSC9953 The new added commands can be used to configure VLANs for a port on both ingress and egress. The new commands are: ethsw [port ] pvid { [help] | show | } - set/show PVID (ingress and egress VLAN tagging) for a port; ethsw [port ] vlan { [help] | show | add | del } - add a VLAN to a port (VLAN members); ethsw [port ] untagged { [help] | show | all | none | pvid } - set egress tagging mod for a port" ethsw [port ] egress tag { [help] | show | pvid | classified } - Configure VID source for egress tag. Tag's VID could be the frame's classified VID or the PVID of the port These commands have also been added to the ethsw generic parser from common/cmd_ethsw.c Signed-off-by: Johnson Leung Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 478 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 478 insertions(+) (limited to 'drivers') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 071906c1fb..c5c0e5c60f 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -196,6 +196,100 @@ static int vsc9953_vlan_table_poll_idle(void) return timeout ? 0 : -EBUSY; } +#ifdef CONFIG_CMD_ETHSW +/* Add/remove a port to/from a VLAN */ +static void vsc9953_vlan_table_membership_set(int vid, u32 port_no, u8 add) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); + val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid); + out_le32(&l2ana_reg->ana_tables.vlan_tidx, val); + + clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, + VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ); + + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); + val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid); + out_le32(&l2ana_reg->ana_tables.vlan_tidx, val); + + val = in_le32(&l2ana_reg->ana_tables.vlan_access); + if (!add) { + val = bitfield_replace_by_mask(val, VSC9953_VLAN_CMD_MASK, + VSC9953_VLAN_CMD_WRITE) & + ~(bitfield_replace_by_mask(0, VSC9953_VLAN_PORT_MASK, + (1 << port_no))); + ; + } else { + val = bitfield_replace_by_mask(val, VSC9953_VLAN_CMD_MASK, + VSC9953_VLAN_CMD_WRITE) | + bitfield_replace_by_mask(0, VSC9953_VLAN_PORT_MASK, + (1 << port_no)); + } + out_le32(&l2ana_reg->ana_tables.vlan_access, val); + + /* wait for VLAN table command to flush */ + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } +} + +/* show VLAN membership for a port */ +static void vsc9953_vlan_membership_show(int port_no) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + u32 vid; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + printf("Port %d VLAN membership: ", port_no); + + for (vid = 0; vid < VSC9953_MAX_VLAN; vid++) { + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); + val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, + vid); + out_le32(&l2ana_reg->ana_tables.vlan_tidx, val); + + clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, + VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ); + + if (vsc9953_vlan_table_poll_idle() < 0) { + debug("VLAN table timeout\n"); + return; + } + + val = in_le32(&l2ana_reg->ana_tables.vlan_access); + + if (bitfield_extract_by_mask(val, VSC9953_VLAN_PORT_MASK) & + (1 << port_no)) + printf("%d ", vid); + } + printf("\n"); +} +#endif + /* vlan table set/clear all membership of vid */ static void vsc9953_vlan_table_membership_all_set(int vid, int set_member) { @@ -233,6 +327,30 @@ static void vsc9953_vlan_table_membership_all_set(int vid, int set_member) (set_member ? VSC9953_VLAN_PORT_MASK : 0)); } +#ifdef CONFIG_CMD_ETHSW +/* Get PVID of a VSC9953 port */ +static int vsc9953_port_vlan_pvid_get(int port_nr, int *pvid) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + /* Administrative down */ + if (vsc9953_l2sw.port[port_nr].enabled) { + printf("Port %d is administrative down\n", port_nr); + return -1; + } + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* Get ingress PVID */ + val = in_le32(&l2ana_reg->port[port_nr].vlan_cfg); + *pvid = bitfield_extract_by_mask(val, VSC9953_VLAN_CFG_VID_MASK); + + return 0; +} +#endif + /* Set PVID for a VSC9953 port */ static void vsc9953_port_vlan_pvid_set(int port_no, int pvid) { @@ -359,6 +477,75 @@ enum egress_untag_mode { EGRESS_UNTAG_NONE, }; +#ifdef CONFIG_CMD_ETHSW +/* Get egress tagging configuration for a VSC9953 port */ +static int vsc9953_port_vlan_egr_untag_get(int port_no, + enum egress_untag_mode *mode) +{ + u32 val; + struct vsc9953_rew_reg *l2rew_reg; + + /* Administrative down */ + if (!vsc9953_l2sw.port[port_no].enabled) { + printf("Port %d is administrative down\n", port_no); + return -1; + } + + l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + + VSC9953_REW_OFFSET); + + val = in_le32(&l2rew_reg->port[port_no].port_tag_cfg); + + switch (val & VSC9953_TAG_CFG_MASK) { + case VSC9953_TAG_CFG_NONE: + *mode = EGRESS_UNTAG_ALL; + return 0; + case VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO: + *mode = EGRESS_UNTAG_PVID_AND_ZERO; + return 0; + case VSC9953_TAG_CFG_ALL_BUT_ZERO: + *mode = EGRESS_UNTAG_ZERO; + return 0; + case VSC9953_TAG_CFG_ALL: + *mode = EGRESS_UNTAG_NONE; + return 0; + default: + printf("Unknown egress tagging configuration for port %d\n", + port_no); + return -1; + } +} + +/* Show egress tagging configuration for a VSC9953 port */ +static void vsc9953_port_vlan_egr_untag_show(int port_no) +{ + enum egress_untag_mode mode; + + if (vsc9953_port_vlan_egr_untag_get(port_no, &mode)) { + printf("%7d\t%17s\n", port_no, "-"); + return; + } + + printf("%7d\t", port_no); + switch (mode) { + case EGRESS_UNTAG_ALL: + printf("%17s\n", "all"); + break; + case EGRESS_UNTAG_NONE: + printf("%17s\n", "none"); + break; + case EGRESS_UNTAG_PVID_AND_ZERO: + printf("%17s\n", "PVID and 0"); + break; + case EGRESS_UNTAG_ZERO: + printf("%17s\n", "0"); + break; + default: + printf("%17s\n", "-"); + } +} +#endif + static void vsc9953_port_vlan_egr_untag_set(int port_no, enum egress_untag_mode mode) { @@ -1166,6 +1353,51 @@ static void vsc9953_mac_table_flush(int port, int vid) vsc9953_mac_table_age(port, vid); } +enum egress_vlan_tag { + EGR_TAG_CLASS = 0, + EGR_TAG_PVID, +}; + +/* Set egress tag mode for a VSC9953 port */ +static void vsc9953_port_vlan_egress_tag_set(int port_no, + enum egress_vlan_tag mode) +{ + struct vsc9953_rew_reg *l2rew_reg; + + l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + + VSC9953_REW_OFFSET); + + switch (mode) { + case EGR_TAG_CLASS: + clrbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_VID_PVID); + break; + case EGR_TAG_PVID: + setbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, + VSC9953_TAG_VID_PVID); + break; + default: + printf("Unknown egress VLAN tag mode for port %d\n", port_no); + } +} + +/* Get egress tag mode for a VSC9953 port */ +static void vsc9953_port_vlan_egress_tag_get(int port_no, + enum egress_vlan_tag *mode) +{ + u32 val; + struct vsc9953_rew_reg *l2rew_reg; + + l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + + VSC9953_REW_OFFSET); + + val = in_le32(&l2rew_reg->port[port_no].port_tag_cfg); + if (val & VSC9953_TAG_VID_PVID) + *mode = EGR_TAG_PVID; + else + *mode = EGR_TAG_CLASS; +} + static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) { int i; @@ -1417,6 +1649,244 @@ static int vsc9953_fdb_entry_del_key_func(struct ethsw_command_def *parsed_cmd) return CMD_RET_SUCCESS; } +static int vsc9953_pvid_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + int pvid; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + + if (vsc9953_port_vlan_pvid_get(parsed_cmd->port, &pvid)) + return CMD_RET_FAILURE; + printf("%7s %7s\n", "Port", "PVID"); + printf("%7d %7d\n", parsed_cmd->port, pvid); + } else { + printf("%7s %7s\n", "Port", "PVID"); + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (vsc9953_port_vlan_pvid_get(i, &pvid)) + continue; + printf("%7d %7d\n", i, pvid); + } + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_pvid_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + /* PVID number should be set in parsed_cmd->vid */ + if (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL) { + printf("Please set a pvid value\n"); + return CMD_RET_FAILURE; + } + + if (!VSC9953_VLAN_CHECK(parsed_cmd->vid)) { + printf("Invalid VID number: %d\n", parsed_cmd->vid); + return CMD_RET_FAILURE; + } + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_vlan_pvid_set(parsed_cmd->port, parsed_cmd->vid); + } else { + vsc9953_port_all_vlan_pvid_set(parsed_cmd->vid); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_vlan_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_vlan_membership_show(parsed_cmd->port); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_vlan_membership_show(i); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_vlan_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + int add; + + /* VLAN should be set in parsed_cmd->vid */ + if (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL) { + printf("Please set a vlan value\n"); + return CMD_RET_FAILURE; + } + + if (!VSC9953_VLAN_CHECK(parsed_cmd->vid)) { + printf("Invalid VID number: %d\n", parsed_cmd->vid); + return CMD_RET_FAILURE; + } + + /* keywords add/delete should be the last but one in array */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 2] == + ethsw_id_add) + add = 1; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 2] == + ethsw_id_del) + add = 0; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_vlan_table_membership_set(parsed_cmd->vid, + parsed_cmd->port, add); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_vlan_table_membership_set(parsed_cmd->vid, i, + add); + } + + return CMD_RET_SUCCESS; +} +static int vsc9953_port_untag_show_key_func( + struct ethsw_command_def *parsed_cmd) +{ + int i; + + printf("%7s\t%17s\n", "Port", "Untag"); + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_vlan_egr_untag_show(parsed_cmd->port); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_egr_untag_show(i); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_port_untag_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + enum egress_untag_mode mode; + + /* keywords for the untagged mode are the last in the array */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_all) + mode = EGRESS_UNTAG_ALL; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_none) + mode = EGRESS_UNTAG_NONE; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_pvid) + mode = EGRESS_UNTAG_PVID_AND_ZERO; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_vlan_egr_untag_set(parsed_cmd->port, mode); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_egr_untag_set(i, mode); + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_egr_vlan_tag_show_key_func( + struct ethsw_command_def *parsed_cmd) +{ + int i; + enum egress_vlan_tag mode; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_vlan_egress_tag_get(parsed_cmd->port, &mode); + printf("%7s\t%12s\n", "Port", "Egress VID"); + printf("%7d\t", parsed_cmd->port); + switch (mode) { + case EGR_TAG_CLASS: + printf("%12s\n", "classified"); + break; + case EGR_TAG_PVID: + printf("%12s\n", "pvid"); + break; + default: + printf("%12s\n", "-"); + } + } else { + printf("%7s\t%12s\n", "Port", "Egress VID"); + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + vsc9953_port_vlan_egress_tag_get(i, &mode); + switch (mode) { + case EGR_TAG_CLASS: + printf("%7d\t%12s\n", i, "classified"); + break; + case EGR_TAG_PVID: + printf("%7d\t%12s\n", i, "pvid"); + break; + default: + printf("%7d\t%12s\n", i, "-"); + } + } + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_egr_vlan_tag_set_key_func( + struct ethsw_command_def *parsed_cmd) +{ + int i; + enum egress_vlan_tag mode; + + /* keywords for the egress vlan tag mode are the last in the array */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_pvid) + mode = EGR_TAG_PVID; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_classified) + mode = EGR_TAG_CLASS; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_vlan_egress_tag_set(parsed_cmd->port, mode); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_vlan_egress_tag_set(i, mode); + } + + return CMD_RET_SUCCESS; +} + static struct ethsw_command_func vsc9953_cmd_func = { .ethsw_name = "L2 Switch VSC9953", .port_enable = &vsc9953_port_status_key_func, @@ -1430,6 +1900,14 @@ static struct ethsw_command_func vsc9953_cmd_func = { .fdb_flush = &vsc9953_fdb_flush_key_func, .fdb_entry_add = &vsc9953_fdb_entry_add_key_func, .fdb_entry_del = &vsc9953_fdb_entry_del_key_func, + .pvid_show = &vsc9953_pvid_show_key_func, + .pvid_set = &vsc9953_pvid_set_key_func, + .vlan_show = &vsc9953_vlan_show_key_func, + .vlan_set = &vsc9953_vlan_set_key_func, + .port_untag_show = &vsc9953_port_untag_show_key_func, + .port_untag_set = &vsc9953_port_untag_set_key_func, + .port_egr_vlan_show = &vsc9953_egr_vlan_tag_show_key_func, + .port_egr_vlan_set = &vsc9953_egr_vlan_tag_set_key_func, }; #endif /* CONFIG_CMD_ETHSW */ -- cgit v1.2.1 From 21d214fcd0a12c75ebb9c675f0f07b8e69f6cb44 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:34 +0300 Subject: drivers/net/vsc9953: Add command for shared/private VLAN learning The command: ethsw vlan fdb { [help] | show | shared | private } - make VLAN learning shared or private" configures the FDB to share the FDB entries learned on multiple VLANs or to keep them separated. By default, the FBD uses private VLAN learning. This command has also been added to the ethsw generic parser from common/cmd_ethsw.c Signed-off-by: Johnson Leung Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 95 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) (limited to 'drivers') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index c5c0e5c60f..f8f52334b9 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -1398,6 +1398,55 @@ static void vsc9953_port_vlan_egress_tag_get(int port_no, *mode = EGR_TAG_CLASS; } +/* VSC9953 VLAN learning modes */ +enum vlan_learning_mode { + SHARED_VLAN_LEARNING, + PRIVATE_VLAN_LEARNING, +}; + +/* Set VLAN learning mode for VSC9953 */ +static void vsc9953_vlan_learning_set(enum vlan_learning_mode lrn_mode) +{ + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + switch (lrn_mode) { + case SHARED_VLAN_LEARNING: + setbits_le32(&l2ana_reg->ana.agen_ctrl, VSC9953_FID_MASK_ALL); + break; + case PRIVATE_VLAN_LEARNING: + clrbits_le32(&l2ana_reg->ana.agen_ctrl, VSC9953_FID_MASK_ALL); + break; + default: + printf("Unknown VLAN learn mode\n"); + } +} + +/* Get VLAN learning mode for VSC9953 */ +static int vsc9953_vlan_learning_get(enum vlan_learning_mode *lrn_mode) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + val = in_le32(&l2ana_reg->ana.agen_ctrl); + + if (!(val & VSC9953_FID_MASK_ALL)) { + *lrn_mode = PRIVATE_VLAN_LEARNING; + } else if ((val & VSC9953_FID_MASK_ALL) == VSC9953_FID_MASK_ALL) { + *lrn_mode = SHARED_VLAN_LEARNING; + } else { + printf("Unknown VLAN learning mode\n"); + return -EINVAL; + } + + return 0; +} + static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) { int i; @@ -1887,6 +1936,50 @@ static int vsc9953_egr_vlan_tag_set_key_func( return CMD_RET_SUCCESS; } +static int vsc9953_vlan_learn_show_key_func( + struct ethsw_command_def *parsed_cmd) +{ + int rc; + enum vlan_learning_mode mode; + + rc = vsc9953_vlan_learning_get(&mode); + if (rc) + return CMD_RET_FAILURE; + + switch (mode) { + case SHARED_VLAN_LEARNING: + printf("VLAN learning mode: shared\n"); + break; + case PRIVATE_VLAN_LEARNING: + printf("VLAN learning mode: private\n"); + break; + default: + printf("Unknown VLAN learning mode\n"); + rc = CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_vlan_learn_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + enum vlan_learning_mode mode; + + /* keywords for shared/private are the last in the array */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_shared) + mode = SHARED_VLAN_LEARNING; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_private) + mode = PRIVATE_VLAN_LEARNING; + else + return CMD_RET_USAGE; + + vsc9953_vlan_learning_set(mode); + + return CMD_RET_SUCCESS; +} + static struct ethsw_command_func vsc9953_cmd_func = { .ethsw_name = "L2 Switch VSC9953", .port_enable = &vsc9953_port_status_key_func, @@ -1908,6 +2001,8 @@ static struct ethsw_command_func vsc9953_cmd_func = { .port_untag_set = &vsc9953_port_untag_set_key_func, .port_egr_vlan_show = &vsc9953_egr_vlan_tag_show_key_func, .port_egr_vlan_set = &vsc9953_egr_vlan_tag_set_key_func, + .vlan_learn_show = &vsc9953_vlan_learn_show_key_func, + .vlan_learn_set = &vsc9953_vlan_learn_set_key_func, }; #endif /* CONFIG_CMD_ETHSW */ -- cgit v1.2.1 From 5ed1bacd3402a3153c8306766ad099b2261ebe36 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:35 +0300 Subject: drivers/net/vsc9953: Add commands for VLAN ingress filtering The command: ethsw [port ] ingress filtering { [help] | show | enable | disable } - enable/disable VLAN ingress filtering on port can be used to enable/disable/show VLAN ingress filtering on a port. This command has also been added to the ethsw generic parser from common/cmd_ethsw.c Signed-off-by: Johnson Leung Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) (limited to 'drivers') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index f8f52334b9..8be87a15b2 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -1447,6 +1447,33 @@ static int vsc9953_vlan_learning_get(enum vlan_learning_mode *lrn_mode) return 0; } +/* Enable/disable VLAN ingress filtering on a VSC9953 port */ +static void vsc9953_port_ingress_filtering_set(int port_no, int enabled) +{ + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (enabled) + setbits_le32(&l2ana_reg->ana.vlan_mask, 1 << port_no); + else + clrbits_le32(&l2ana_reg->ana.vlan_mask, 1 << port_no); +} + +/* Return VLAN ingress filtering on a VSC9953 port */ +static int vsc9953_port_ingress_filtering_get(int port_no) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + val = in_le32(&l2ana_reg->ana.vlan_mask); + return !!(val & (1 << port_no)); +} + static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) { int i; @@ -1980,6 +2007,63 @@ static int vsc9953_vlan_learn_set_key_func(struct ethsw_command_def *parsed_cmd) return CMD_RET_SUCCESS; } +static int vsc9953_ingr_fltr_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + int enabled; + + printf("%7s\t%18s\n", "Port", "Ingress filtering"); + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + enabled = vsc9953_port_ingress_filtering_get(parsed_cmd->port); + printf("%7d\t%18s\n", parsed_cmd->port, enabled ? "enable" : + "disable"); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + enabled = vsc9953_port_ingress_filtering_get(i); + printf("%7d\t%18s\n", parsed_cmd->port, enabled ? + "enable" : + "disable"); + } + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_ingr_fltr_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + int enable; + + /* keywords for enabling/disabling ingress filtering + * are the last in the array + */ + if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_enable) + enable = 1; + else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == + ethsw_id_disable) + enable = 0; + else + return CMD_RET_USAGE; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + vsc9953_port_ingress_filtering_set(parsed_cmd->port, enable); + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) + vsc9953_port_ingress_filtering_set(i, enable); + } + + return CMD_RET_SUCCESS; +} + static struct ethsw_command_func vsc9953_cmd_func = { .ethsw_name = "L2 Switch VSC9953", .port_enable = &vsc9953_port_status_key_func, @@ -2003,6 +2087,8 @@ static struct ethsw_command_func vsc9953_cmd_func = { .port_egr_vlan_set = &vsc9953_egr_vlan_tag_set_key_func, .vlan_learn_show = &vsc9953_vlan_learn_show_key_func, .vlan_learn_set = &vsc9953_vlan_learn_set_key_func, + .port_ingr_filt_show = &vsc9953_ingr_fltr_show_key_func, + .port_ingr_filt_set = &vsc9953_ingr_fltr_set_key_func }; #endif /* CONFIG_CMD_ETHSW */ -- cgit v1.2.1 From a857d5f835c53f7b66de61b19120ea1188e94999 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 24 Jul 2015 16:55:36 +0300 Subject: drivers/net/vsc9953: Add GPL-2.0+ SPDX-License-Identifier Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- drivers/net/vsc9953.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 8be87a15b2..7595db1acb 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2014 - 2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ * -- cgit v1.2.1 From 5dc626f836190fa2ef27f34e263b53641c14087c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:32 +0900 Subject: pinctrl: uniphier: add UniPhier pinctrl core support The core support for the pinctrl drivers for all the UniPhier SoCs. Signed-off-by: Masahiro Yamada Reviewed-by: Simon Glass --- drivers/pinctrl/Kconfig | 2 + drivers/pinctrl/Makefile | 2 + drivers/pinctrl/uniphier/Kconfig | 6 + drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 154 +++++++++++++++++++++++ drivers/pinctrl/uniphier/pinctrl-uniphier.h | 113 +++++++++++++++++ 6 files changed, 278 insertions(+) create mode 100644 drivers/pinctrl/uniphier/Kconfig create mode 100644 drivers/pinctrl/uniphier/Makefile create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier.h (limited to 'drivers') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index b8146df99b..3b6e3b7060 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -124,4 +124,6 @@ config PINCTRL_SANDBOX endif +source "drivers/pinctrl/uniphier/Kconfig" + endmenu diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f537df4e88..e56a17f966 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -3,3 +3,5 @@ obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o + +obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/ diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig new file mode 100644 index 0000000000..29a623dfc1 --- /dev/null +++ b/drivers/pinctrl/uniphier/Kconfig @@ -0,0 +1,6 @@ +if ARCH_UNIPHIER + +config PINCTRL_UNIPHIER_CORE + bool + +endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile new file mode 100644 index 0000000000..748aa1b4e4 --- /dev/null +++ b/drivers/pinctrl/uniphier/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c new file mode 100644 index 0000000000..37a920ca8b --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#include "pinctrl-uniphier.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int uniphier_pinctrl_get_groups_count(struct udevice *dev) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->socdata->groups_count; +} + +static const char *uniphier_pinctrl_get_group_name(struct udevice *dev, + unsigned selector) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->socdata->groups[selector].name; +} + +static int uniphier_pinmux_get_functions_count(struct udevice *dev) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->socdata->functions_count; +} + +static const char *uniphier_pinmux_get_function_name(struct udevice *dev, + unsigned selector) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->socdata->functions[selector]; +} + +static void uniphier_pinconf_input_enable(struct udevice *dev, unsigned pin) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + int pins_count = priv->socdata->pins_count; + const struct uniphier_pinctrl_pin *pins = priv->socdata->pins; + int i; + + for (i = 0; i < pins_count; i++) { + if (pins[i].number == pin) { + unsigned int iectrl; + u32 tmp; + + iectrl = uniphier_pin_get_iectrl(pins[i].data); + tmp = readl(priv->base + UNIPHIER_PINCTRL_IECTRL); + tmp |= 1 << iectrl; + writel(tmp, priv->base + UNIPHIER_PINCTRL_IECTRL); + } + } +} + +static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin, + unsigned muxval) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + unsigned mux_bits = priv->socdata->mux_bits; + unsigned reg_stride = priv->socdata->reg_stride; + unsigned reg, reg_end, shift, mask; + u32 tmp; + + reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride; + reg_end = reg + reg_stride; + shift = pin * mux_bits % 32; + mask = (1U << mux_bits) - 1; + + /* + * If reg_stride is greater than 4, the MSB of each pinsel shall be + * stored in the offset+4. + */ + for (; reg < reg_end; reg += 4) { + tmp = readl(priv->base + reg); + tmp &= ~(mask << shift); + tmp |= (mask & muxval) << shift; + writel(tmp, priv->base + reg); + + muxval >>= mux_bits; + } + + if (priv->socdata->load_pinctrl) + writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX); + + /* some pins need input-enabling */ + uniphier_pinconf_input_enable(dev, pin); +} + +static int uniphier_pinmux_group_set(struct udevice *dev, + unsigned group_selector, + unsigned func_selector) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + const struct uniphier_pinctrl_group *grp = + &priv->socdata->groups[group_selector]; + int i; + + for (i = 0; i < grp->num_pins; i++) + uniphier_pinmux_set_one(dev, grp->pins[i], grp->muxvals[i]); + + return 0; +} + +const struct pinctrl_ops uniphier_pinctrl_ops = { + .get_groups_count = uniphier_pinctrl_get_groups_count, + .get_group_name = uniphier_pinctrl_get_group_name, + .get_functions_count = uniphier_pinmux_get_functions_count, + .get_function_name = uniphier_pinmux_get_function_name, + .pinmux_group_set = uniphier_pinmux_group_set, + .set_state = pinctrl_generic_set_state, +}; + +int uniphier_pinctrl_probe(struct udevice *dev, + struct uniphier_pinctrl_socdata *socdata) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", + &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = map_sysmem(addr, size); + if (!priv->base) + return -ENOMEM; + + priv->socdata = socdata; + + return 0; +} + +int uniphier_pinctrl_remove(struct udevice *dev) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + + unmap_sysmem(priv->base); + + return 0; +} diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h new file mode 100644 index 0000000000..7eaec6a702 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PINCTRL_UNIPHIER_H__ +#define __PINCTRL_UNIPHIER_H__ + +/* TODO: move this to include/linux/bug.h */ +#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:-!!(e); })) + +#include +#include + +#define UNIPHIER_PINCTRL_PINMUX_BASE 0x0 +#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x700 +#define UNIPHIER_PINCTRL_IECTRL 0xd00 + +#define UNIPHIER_PIN_ATTR_PACKED(iectrl) (iectrl) + +static inline unsigned int uniphier_pin_get_iectrl(unsigned long data) +{ + return data; +} + +/** + * struct uniphier_pinctrl_pin - pin data for UniPhier SoC + * + * @number: pin number + * @data: additional per-pin data + */ +struct uniphier_pinctrl_pin { + unsigned number; + unsigned long data; +}; + +/** + * struct uniphier_pinctrl_group - pin group data for UniPhier SoC + * + * @name: pin group name + * @pins: array of pins that belong to the group + * @num_pins: number of pins in the group + * @muxvals: array of values to be set to pinmux registers + */ +struct uniphier_pinctrl_group { + const char *name; + const unsigned *pins; + unsigned num_pins; + const unsigned *muxvals; +}; + +/** + * struct uniphier_pinctrl_socdata - SoC data for UniPhier pin controller + * + * @pins: array of pin data + * @pins_count: number of pin data + * @groups: array of pin group data + * @groups_count: number of pin group data + * @functions: array of pinmux function names + * @functions_count: number of pinmux functions + * @mux_bits: bit width of each pinmux register + * @reg_stride: stride of pinmux register address + * @load_pinctrl: if true, LOAD_PINMUX register must be set to one for new + * values in pinmux registers to become really effective + */ +struct uniphier_pinctrl_socdata { + const struct uniphier_pinctrl_pin *pins; + int pins_count; + const struct uniphier_pinctrl_group *groups; + int groups_count; + const char * const *functions; + int functions_count; + unsigned mux_bits; + unsigned reg_stride; + bool load_pinctrl; +}; + +#define UNIPHIER_PINCTRL_PIN(a, b) \ +{ \ + .number = a, \ + .data = UNIPHIER_PIN_ATTR_PACKED(b), \ +} + +#define UNIPHIER_PINCTRL_GROUP(grp) \ + { \ + .name = #grp, \ + .pins = grp##_pins, \ + .num_pins = ARRAY_SIZE(grp##_pins), \ + .muxvals = grp##_muxvals + \ + BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \ + ARRAY_SIZE(grp##_muxvals)), \ + } + +/** + * struct uniphier_pinctrl_priv - private data for UniPhier pinctrl driver + * + * @base: base address of the pinctrl device + * @socdata: SoC specific data + */ +struct uniphier_pinctrl_priv { + void __iomem *base; + struct uniphier_pinctrl_socdata *socdata; +}; + +extern const struct pinctrl_ops uniphier_pinctrl_ops; + +int uniphier_pinctrl_probe(struct udevice *dev, + struct uniphier_pinctrl_socdata *socdata); + +int uniphier_pinctrl_remove(struct udevice *dev); + +#endif /* __PINCTRL_UNIPHIER_H__ */ -- cgit v1.2.1 From e4410e820756891129f7c15f701c51956013804b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:33 +0900 Subject: pinctrl: uniphier: add UniPhier PH1-LD4 pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/Kconfig | 6 ++ drivers/pinctrl/uniphier/Makefile | 2 + drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c | 133 +++++++++++++++++++++++++++++ 3 files changed, 141 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c (limited to 'drivers') diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 29a623dfc1..03593cdd8b 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -3,4 +3,10 @@ if ARCH_UNIPHIER config PINCTRL_UNIPHIER_CORE bool +config PINCTRL_UNIPHIER_PH1_LD4 + bool "UniPhier PH1-LD4 SoC pinctrl driver" + depends on MACH_PH1_LD4 + default y + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index 748aa1b4e4..b4bd042ac4 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -1 +1,3 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o + +obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c new file mode 100644 index 0000000000..b3d47f0915 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "pinctrl-uniphier.h" + +static const struct uniphier_pinctrl_pin ph1_ld4_pins[] = { + UNIPHIER_PINCTRL_PIN(53, 0), + UNIPHIER_PINCTRL_PIN(54, 0), + UNIPHIER_PINCTRL_PIN(55, 0), + UNIPHIER_PINCTRL_PIN(56, 0), + UNIPHIER_PINCTRL_PIN(67, 0), + UNIPHIER_PINCTRL_PIN(68, 0), + UNIPHIER_PINCTRL_PIN(69, 0), + UNIPHIER_PINCTRL_PIN(70, 0), + UNIPHIER_PINCTRL_PIN(85, 0), + UNIPHIER_PINCTRL_PIN(88, 0), + UNIPHIER_PINCTRL_PIN(156, 0), +}; + +static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27}; +static const unsigned emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1}; +static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31}; +static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1}; +static const unsigned i2c0_pins[] = {102, 103}; +static const unsigned i2c0_muxvals[] = {0, 0}; +static const unsigned i2c1_pins[] = {104, 105}; +static const unsigned i2c1_muxvals[] = {0, 0}; +static const unsigned i2c2_pins[] = {108, 109}; +static const unsigned i2c2_muxvals[] = {2, 2}; +static const unsigned i2c3_pins[] = {108, 109}; +static const unsigned i2c3_muxvals[] = {3, 3}; +static const unsigned nand_pins[] = {24, 25, 26, 27, 28, 29, 30, 31, 158, 159, + 160, 161, 162, 163, 164}; +static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}; +static const unsigned nand_cs1_pins[] = {22, 23}; +static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned uart0_pins[] = {85, 88}; +static const unsigned uart0_muxvals[] = {1, 1}; +static const unsigned uart1_pins[] = {155, 156}; +static const unsigned uart1_muxvals[] = {13, 13}; +static const unsigned uart1b_pins[] = {69, 70}; +static const unsigned uart1b_muxvals[] = {23, 23}; +static const unsigned uart2_pins[] = {128, 129}; +static const unsigned uart2_muxvals[] = {13, 13}; +static const unsigned uart3_pins[] = {110, 111}; +static const unsigned uart3_muxvals[] = {1, 1}; +static const unsigned usb0_pins[] = {53, 54}; +static const unsigned usb0_muxvals[] = {0, 0}; +static const unsigned usb1_pins[] = {55, 56}; +static const unsigned usb1_muxvals[] = {0, 0}; +static const unsigned usb2_pins[] = {155, 156}; +static const unsigned usb2_muxvals[] = {4, 4}; +static const unsigned usb2b_pins[] = {67, 68}; +static const unsigned usb2b_muxvals[] = {23, 23}; + +static const struct uniphier_pinctrl_group ph1_ld4_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart1b), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP(usb2b), +}; + +static const char * const ph1_ld4_functions[] = { + "emmc", + "i2c0", + "i2c1", + "i2c2", + "i2c3", + "nand", + "sd", + "uart0", + "uart1", + "uart2", + "uart3", + "usb0", + "usb1", + "usb2", +}; + +static struct uniphier_pinctrl_socdata ph1_ld4_pinctrl_socdata = { + .pins = ph1_ld4_pins, + .pins_count = ARRAY_SIZE(ph1_ld4_pins), + .groups = ph1_ld4_groups, + .groups_count = ARRAY_SIZE(ph1_ld4_groups), + .functions = ph1_ld4_functions, + .functions_count = ARRAY_SIZE(ph1_ld4_functions), + .mux_bits = 8, + .reg_stride = 4, + .load_pinctrl = false, +}; + +static int ph1_ld4_pinctrl_probe(struct udevice *dev) +{ + return uniphier_pinctrl_probe(dev, &ph1_ld4_pinctrl_socdata); +} + +static const struct udevice_id ph1_ld4_pinctrl_match[] = { + { .compatible = "socionext,ph1-ld4-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(ph1_ld4_pinctrl) = { + .name = "ph1-ld4-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(ph1_ld4_pinctrl_match), + .probe = ph1_ld4_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), + .ops = &uniphier_pinctrl_ops, +}; -- cgit v1.2.1 From a343812461d40dfe72622176c6581a9e2f673ea2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:34 +0900 Subject: pinctrl: uniphier: add UniPhier PH1-Pro4 pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/Kconfig | 6 ++ drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c | 130 ++++++++++++++++++++++++++++ 3 files changed, 137 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c (limited to 'drivers') diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 03593cdd8b..c417a9f4ea 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -9,4 +9,10 @@ config PINCTRL_UNIPHIER_PH1_LD4 default y select PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER_PH1_PRO4 + bool "UniPhier PH1-Pro4 SoC pinctrl driver" + depends on MACH_PH1_PRO4 + default y + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index b4bd042ac4..b1b597e0dc 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c new file mode 100644 index 0000000000..b3eaf138f7 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "pinctrl-uniphier.h" + +static const struct uniphier_pinctrl_pin ph1_pro4_pins[] = { +}; + +static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53}; +static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; +static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47}; +static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1}; +static const unsigned i2c0_pins[] = {142, 143}; +static const unsigned i2c0_muxvals[] = {0, 0}; +static const unsigned i2c1_pins[] = {144, 145}; +static const unsigned i2c1_muxvals[] = {0, 0}; +static const unsigned i2c2_pins[] = {146, 147}; +static const unsigned i2c2_muxvals[] = {0, 0}; +static const unsigned i2c3_pins[] = {148, 149}; +static const unsigned i2c3_muxvals[] = {0, 0}; +static const unsigned i2c6_pins[] = {308, 309}; +static const unsigned i2c6_muxvals[] = {6, 6}; +static const unsigned nand_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, 49, + 50, 51, 52, 53, 54}; +static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}; +static const unsigned nand_cs1_pins[] = {131, 132}; +static const unsigned nand_cs1_muxvals[] = {1, 1}; +static const unsigned sd_pins[] = {150, 151, 152, 153, 154, 155, 156, 157, 158}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326, + 327}; +static const unsigned sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned uart0_pins[] = {127, 128}; +static const unsigned uart0_muxvals[] = {0, 0}; +static const unsigned uart1_pins[] = {129, 130}; +static const unsigned uart1_muxvals[] = {0, 0}; +static const unsigned uart2_pins[] = {131, 132}; +static const unsigned uart2_muxvals[] = {0, 0}; +static const unsigned uart3_pins[] = {88, 89}; +static const unsigned uart3_muxvals[] = {2, 2}; +static const unsigned usb0_pins[] = {180, 181}; +static const unsigned usb0_muxvals[] = {0, 0}; +static const unsigned usb1_pins[] = {182, 183}; +static const unsigned usb1_muxvals[] = {0, 0}; +static const unsigned usb2_pins[] = {184, 185}; +static const unsigned usb2_muxvals[] = {0, 0}; +static const unsigned usb3_pins[] = {186, 187}; +static const unsigned usb3_muxvals[] = {0, 0}; + +static const struct uniphier_pinctrl_group ph1_pro4_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(i2c6), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(sd1), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP(usb3), +}; + +static const char * const ph1_pro4_functions[] = { + "emmc", + "i2c0", + "i2c1", + "i2c2", + "i2c3", + "i2c6", + "nand", + "sd", + "sd1", + "uart0", + "uart1", + "uart2", + "uart3", + "usb0", + "usb1", + "usb2", + "usb3", +}; + +static struct uniphier_pinctrl_socdata ph1_pro4_pinctrl_socdata = { + .pins = ph1_pro4_pins, + .pins_count = ARRAY_SIZE(ph1_pro4_pins), + .groups = ph1_pro4_groups, + .groups_count = ARRAY_SIZE(ph1_pro4_groups), + .functions = ph1_pro4_functions, + .functions_count = ARRAY_SIZE(ph1_pro4_functions), + .mux_bits = 4, + .reg_stride = 8, + .load_pinctrl = true, +}; + +static int ph1_pro4_pinctrl_probe(struct udevice *dev) +{ + return uniphier_pinctrl_probe(dev, &ph1_pro4_pinctrl_socdata); +} + +static const struct udevice_id ph1_pro4_pinctrl_match[] = { + { .compatible = "socionext,ph1-pro4-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(ph1_pro4_pinctrl) = { + .name = "ph1-pro4-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(ph1_pro4_pinctrl_match), + .probe = ph1_pro4_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), + .ops = &uniphier_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- cgit v1.2.1 From 06b2ae5890fad1531965ae8ad844336e67fc9bb0 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:35 +0900 Subject: pinctrl: uniphier: add UniPhier PH1-sLD8 pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/Kconfig | 6 ++ drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c | 141 ++++++++++++++++++++++++++++ 3 files changed, 148 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c (limited to 'drivers') diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index c417a9f4ea..a156a28c28 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -15,4 +15,10 @@ config PINCTRL_UNIPHIER_PH1_PRO4 default y select PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER_PH1_SLD8 + bool "UniPhier PH1-sLD8 SoC pinctrl driver" + depends on MACH_PH1_SLD8 + default y + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index b1b597e0dc..3349fff80a 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c new file mode 100644 index 0000000000..5fafdb6100 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "pinctrl-uniphier.h" + +static const struct uniphier_pinctrl_pin ph1_sld8_pins[] = { + UNIPHIER_PINCTRL_PIN(32, 8), + UNIPHIER_PINCTRL_PIN(33, 8), + UNIPHIER_PINCTRL_PIN(34, 8), + UNIPHIER_PINCTRL_PIN(35, 8), + UNIPHIER_PINCTRL_PIN(36, 8), + UNIPHIER_PINCTRL_PIN(37, 8), + UNIPHIER_PINCTRL_PIN(38, 8), + UNIPHIER_PINCTRL_PIN(39, 8), + UNIPHIER_PINCTRL_PIN(40, 9), + UNIPHIER_PINCTRL_PIN(41, 0), + UNIPHIER_PINCTRL_PIN(42, 0), + UNIPHIER_PINCTRL_PIN(43, 0), + UNIPHIER_PINCTRL_PIN(44, 0), + UNIPHIER_PINCTRL_PIN(70, 0), + UNIPHIER_PINCTRL_PIN(71, 0), + UNIPHIER_PINCTRL_PIN(102, 10), + UNIPHIER_PINCTRL_PIN(103, 10), + UNIPHIER_PINCTRL_PIN(104, 11), + UNIPHIER_PINCTRL_PIN(105, 11), + UNIPHIER_PINCTRL_PIN(108, 13), + UNIPHIER_PINCTRL_PIN(109, 13), + UNIPHIER_PINCTRL_PIN(112, 0), + UNIPHIER_PINCTRL_PIN(113, 0), + UNIPHIER_PINCTRL_PIN(114, 0), + UNIPHIER_PINCTRL_PIN(115, 0), +}; + +static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27}; +static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; +static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31}; +static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1}; +static const unsigned i2c0_pins[] = {102, 103}; +static const unsigned i2c0_muxvals[] = {0, 0}; +static const unsigned i2c1_pins[] = {104, 105}; +static const unsigned i2c1_muxvals[] = {0, 0}; +static const unsigned i2c2_pins[] = {108, 109}; +static const unsigned i2c2_muxvals[] = {2, 2}; +static const unsigned i2c3_pins[] = {108, 109}; +static const unsigned i2c3_muxvals[] = {3, 3}; +static const unsigned nand_pins[] = {15, 16, 17, 18, 19, 20, 21, 24, 25, 26, + 27, 28, 29, 30, 31}; +static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}; +static const unsigned nand_cs1_pins[] = {22, 23}; +static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned uart0_pins[] = {70, 71}; +static const unsigned uart0_muxvals[] = {3, 3}; +static const unsigned uart1_pins[] = {114, 115}; +static const unsigned uart1_muxvals[] = {0, 0}; +static const unsigned uart2_pins[] = {112, 113}; +static const unsigned uart2_muxvals[] = {1, 1}; +static const unsigned uart3_pins[] = {110, 111}; +static const unsigned uart3_muxvals[] = {1, 1}; +static const unsigned usb0_pins[] = {41, 42}; +static const unsigned usb0_muxvals[] = {0, 0}; +static const unsigned usb1_pins[] = {43, 44}; +static const unsigned usb1_muxvals[] = {0, 0}; +static const unsigned usb2_pins[] = {114, 115}; +static const unsigned usb2_muxvals[] = {1, 1}; + +static const struct uniphier_pinctrl_group ph1_sld8_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), +}; + +static const char * const ph1_sld8_functions[] = { + "emmc", + "i2c0", + "i2c1", + "i2c2", + "i2c3", + "nand", + "sd", + "uart0", + "uart1", + "uart2", + "uart3", + "usb0", + "usb1", + "usb2", +}; + +static struct uniphier_pinctrl_socdata ph1_sld8_pinctrl_socdata = { + .pins = ph1_sld8_pins, + .pins_count = ARRAY_SIZE(ph1_sld8_pins), + .groups = ph1_sld8_groups, + .groups_count = ARRAY_SIZE(ph1_sld8_groups), + .functions = ph1_sld8_functions, + .functions_count = ARRAY_SIZE(ph1_sld8_functions), + .mux_bits = 8, + .reg_stride = 4, + .load_pinctrl = false, +}; + +static int ph1_sld8_pinctrl_probe(struct udevice *dev) +{ + return uniphier_pinctrl_probe(dev, &ph1_sld8_pinctrl_socdata); +} + +static const struct udevice_id ph1_sld8_pinctrl_match[] = { + { .compatible = "socionext,ph1-sld8-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(ph1_sld8_pinctrl) = { + .name = "ph1-sld8-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(ph1_sld8_pinctrl_match), + .probe = ph1_sld8_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), + .ops = &uniphier_pinctrl_ops, +}; -- cgit v1.2.1 From b82ca82ed23759150f2e00e5299ce1583ba97dd6 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:36 +0900 Subject: pinctrl: uniphier: add UniPhier PH1-Pro5 pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-Pro5 SoC. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/Kconfig | 6 ++ drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c | 144 ++++++++++++++++++++++++++++ 3 files changed, 151 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c (limited to 'drivers') diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index a156a28c28..9d3065db30 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -21,4 +21,10 @@ config PINCTRL_UNIPHIER_PH1_SLD8 default y select PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER_PH1_PRO5 + bool "UniPhier PH1-Pro5 SoC pinctrl driver" + depends on MACH_PH1_PRO5 + default y + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index 3349fff80a..b0cd3e86bc 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c new file mode 100644 index 0000000000..3749250066 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "pinctrl-uniphier.h" + +static const struct uniphier_pinctrl_pin ph1_pro5_pins[] = { + UNIPHIER_PINCTRL_PIN(47, 0), + UNIPHIER_PINCTRL_PIN(48, 0), + UNIPHIER_PINCTRL_PIN(49, 0), + UNIPHIER_PINCTRL_PIN(50, 0), + UNIPHIER_PINCTRL_PIN(53, 0), + UNIPHIER_PINCTRL_PIN(54, 0), + UNIPHIER_PINCTRL_PIN(87, 0), + UNIPHIER_PINCTRL_PIN(88, 0), + UNIPHIER_PINCTRL_PIN(101, 0), + UNIPHIER_PINCTRL_PIN(102, 0), +}; + +static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42}; +static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0}; +static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46}; +static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0}; +static const unsigned i2c0_pins[] = {112, 113}; +static const unsigned i2c0_muxvals[] = {0, 0}; +static const unsigned i2c1_pins[] = {114, 115}; +static const unsigned i2c1_muxvals[] = {0, 0}; +static const unsigned i2c2_pins[] = {116, 117}; +static const unsigned i2c2_muxvals[] = {0, 0}; +static const unsigned i2c3_pins[] = {118, 119}; +static const unsigned i2c3_muxvals[] = {0, 0}; +static const unsigned i2c5_pins[] = {87, 88}; +static const unsigned i2c5_muxvals[] = {2, 2}; +static const unsigned i2c5b_pins[] = {196, 197}; +static const unsigned i2c5b_muxvals[] = {2, 2}; +static const unsigned i2c5c_pins[] = {215, 216}; +static const unsigned i2c5c_muxvals[] = {2, 2}; +static const unsigned i2c6_pins[] = {101, 102}; +static const unsigned i2c6_muxvals[] = {2, 2}; +static const unsigned nand_pins[] = {19, 20, 21, 22, 23, 24, 25, 28, 29, 30, + 31, 32, 33, 34, 35}; +static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}; +static const unsigned nand_cs1_pins[] = {26, 27}; +static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned uart0_pins[] = {47, 48}; +static const unsigned uart0_muxvals[] = {0, 0}; +static const unsigned uart0b_pins[] = {227, 228}; +static const unsigned uart0b_muxvals[] = {3, 3}; +static const unsigned uart1_pins[] = {49, 50}; +static const unsigned uart1_muxvals[] = {0, 0}; +static const unsigned uart2_pins[] = {51, 52}; +static const unsigned uart2_muxvals[] = {0, 0}; +static const unsigned uart3_pins[] = {53, 54}; +static const unsigned uart3_muxvals[] = {0, 0}; +static const unsigned usb0_pins[] = {124, 125}; +static const unsigned usb0_muxvals[] = {0, 0}; +static const unsigned usb1_pins[] = {126, 127}; +static const unsigned usb1_muxvals[] = {0, 0}; +static const unsigned usb2_pins[] = {128, 129}; +static const unsigned usb2_muxvals[] = {0, 0}; + +static const struct uniphier_pinctrl_group ph1_pro5_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(i2c5), + UNIPHIER_PINCTRL_GROUP(i2c5b), + UNIPHIER_PINCTRL_GROUP(i2c5c), + UNIPHIER_PINCTRL_GROUP(i2c6), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart0b), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), +}; + +static const char * const ph1_pro5_functions[] = { + "emmc", + "i2c0", + "i2c1", + "i2c2", + "i2c3", + "i2c5", + "i2c6", + "nand", + "sd", + "uart0", + "uart1", + "uart2", + "uart3", + "usb0", + "usb1", + "usb2", +}; + +static struct uniphier_pinctrl_socdata ph1_pro5_pinctrl_socdata = { + .pins = ph1_pro5_pins, + .pins_count = ARRAY_SIZE(ph1_pro5_pins), + .groups = ph1_pro5_groups, + .groups_count = ARRAY_SIZE(ph1_pro5_groups), + .functions = ph1_pro5_functions, + .functions_count = ARRAY_SIZE(ph1_pro5_functions), + .mux_bits = 4, + .reg_stride = 8, + .load_pinctrl = true, +}; + +static int ph1_pro5_pinctrl_probe(struct udevice *dev) +{ + return uniphier_pinctrl_probe(dev, &ph1_pro5_pinctrl_socdata); +} + +static const struct udevice_id ph1_pro5_pinctrl_match[] = { + { .compatible = "socionext,ph1-pro5-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(ph1_pro5_pinctrl) = { + .name = "ph1-pro5-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(ph1_pro5_pinctrl_match), + .probe = ph1_pro5_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), + .ops = &uniphier_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- cgit v1.2.1 From 833de5fafb43df835f5a9d2a8b77c0ffbbde9cb0 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:37 +0900 Subject: pinctrl: uniphier: add UniPhier ProXstream2 pinctrl driver Add pin configuration and pinmux support for UniPhier ProXstream2 SoC. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/Kconfig | 6 ++ drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-proxstream2.c | 140 +++++++++++++++++++++++++ 3 files changed, 147 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-proxstream2.c (limited to 'drivers') diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 9d3065db30..7f729b68a1 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -27,4 +27,10 @@ config PINCTRL_UNIPHIER_PH1_PRO5 default y select PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER_PROXSTREAM2 + bool "UniPhier ProXstream2 SoC pinctrl driver" + depends on MACH_PROXSTREAM2 + default y + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index b0cd3e86bc..aed038c59f 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o diff --git a/drivers/pinctrl/uniphier/pinctrl-proxstream2.c b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c new file mode 100644 index 0000000000..2cca69d514 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "pinctrl-uniphier.h" + +static const struct uniphier_pinctrl_pin proxstream2_pins[] = { + UNIPHIER_PINCTRL_PIN(113, 0), + UNIPHIER_PINCTRL_PIN(114, 0), + UNIPHIER_PINCTRL_PIN(115, 0), + UNIPHIER_PINCTRL_PIN(116, 0), +}; + +static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42}; +static const unsigned emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9}; +static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46}; +static const unsigned emmc_dat8_muxvals[] = {9, 9, 9, 9}; +static const unsigned i2c0_pins[] = {109, 110}; +static const unsigned i2c0_muxvals[] = {8, 8}; +static const unsigned i2c1_pins[] = {111, 112}; +static const unsigned i2c1_muxvals[] = {8, 8}; +static const unsigned i2c2_pins[] = {171, 172}; +static const unsigned i2c2_muxvals[] = {8, 8}; +static const unsigned i2c3_pins[] = {159, 160}; +static const unsigned i2c3_muxvals[] = {8, 8}; +static const unsigned i2c5_pins[] = {183, 184}; +static const unsigned i2c5_muxvals[] = {11, 11}; +static const unsigned i2c6_pins[] = {185, 186}; +static const unsigned i2c6_muxvals[] = {11, 11}; +static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41, + 42, 43, 44, 45, 46}; +static const unsigned nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8}; +static const unsigned nand_cs1_pins[] = {37, 38}; +static const unsigned nand_cs1_muxvals[] = {8, 8}; +static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55}; +static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8}; +static const unsigned uart0_pins[] = {217, 218}; +static const unsigned uart0_muxvals[] = {8, 8}; +static const unsigned uart0b_pins[] = {179, 180}; +static const unsigned uart0b_muxvals[] = {10, 10}; +static const unsigned uart1_pins[] = {115, 116}; +static const unsigned uart1_muxvals[] = {8, 8}; +static const unsigned uart2_pins[] = {113, 114}; +static const unsigned uart2_muxvals[] = {8, 8}; +static const unsigned uart3_pins[] = {219, 220}; +static const unsigned uart3_muxvals[] = {8, 8}; +static const unsigned uart3b_pins[] = {181, 182}; +static const unsigned uart3b_muxvals[] = {10, 10}; +static const unsigned usb0_pins[] = {56, 57}; +static const unsigned usb0_muxvals[] = {8, 8}; +static const unsigned usb1_pins[] = {58, 59}; +static const unsigned usb1_muxvals[] = {8, 8}; +static const unsigned usb2_pins[] = {60, 61}; +static const unsigned usb2_muxvals[] = {8, 8}; +static const unsigned usb3_pins[] = {62, 63}; +static const unsigned usb3_muxvals[] = {8, 8}; + +static const struct uniphier_pinctrl_group proxstream2_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(i2c5), + UNIPHIER_PINCTRL_GROUP(i2c6), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart0b), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(uart3b), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP(usb3), +}; + +static const char * const proxstream2_functions[] = { + "emmc", + "i2c0", + "i2c1", + "i2c2", + "i2c3", + "i2c5", + "i2c6", + "nand", + "sd", + "uart0", + "uart0b", + "uart1", + "uart2", + "uart3", + "uart3b", + "usb0", + "usb1", + "usb2", + "usb3", +}; + +static struct uniphier_pinctrl_socdata proxstream2_pinctrl_socdata = { + .pins = proxstream2_pins, + .pins_count = ARRAY_SIZE(proxstream2_pins), + .groups = proxstream2_groups, + .groups_count = ARRAY_SIZE(proxstream2_groups), + .functions = proxstream2_functions, + .functions_count = ARRAY_SIZE(proxstream2_functions), + .mux_bits = 8, + .reg_stride = 4, + .load_pinctrl = false, +}; + +static int proxstream2_pinctrl_probe(struct udevice *dev) +{ + return uniphier_pinctrl_probe(dev, &proxstream2_pinctrl_socdata); +} + +static const struct udevice_id proxstream2_pinctrl_match[] = { + { .compatible = "socionext,proxstream2-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(proxstream2_pinctrl) = { + .name = "proxstream2-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(proxstream2_pinctrl_match), + .probe = proxstream2_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), + .ops = &uniphier_pinctrl_ops, +}; -- cgit v1.2.1 From 080b7a5b4522d4a8fcda4a4e0c34b757ac99bdae Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:38 +0900 Subject: pinctrl: uniphier: add UniPhier PH1-LD6b pinctrl driver Add pin configuration and pinmux support for UniPhier PH1-LD6b SoC. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/Kconfig | 6 ++ drivers/pinctrl/uniphier/Makefile | 1 + drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c | 133 ++++++++++++++++++++++++++++ 3 files changed, 140 insertions(+) create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c (limited to 'drivers') diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 7f729b68a1..757edce178 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -33,4 +33,10 @@ config PINCTRL_UNIPHIER_PROXSTREAM2 default y select PINCTRL_UNIPHIER_CORE +config PINCTRL_UNIPHIER_PH1_LD6B + bool "UniPhier PH1-LD6b SoC pinctrl driver" + depends on MACH_PH1_LD6B + default y + select PINCTRL_UNIPHIER_CORE + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index aed038c59f..e215b10972 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o obj-$(CONFIG_PINCTRL_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD6B) += pinctrl-ph1-ld6b.o diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c new file mode 100644 index 0000000000..8703a215e4 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "pinctrl-uniphier.h" + +static const struct uniphier_pinctrl_pin ph1_ld6b_pins[] = { + UNIPHIER_PINCTRL_PIN(113, 0), + UNIPHIER_PINCTRL_PIN(114, 0), + UNIPHIER_PINCTRL_PIN(115, 0), + UNIPHIER_PINCTRL_PIN(116, 0), + UNIPHIER_PINCTRL_PIN(217, 0), + UNIPHIER_PINCTRL_PIN(218, 0), + UNIPHIER_PINCTRL_PIN(219, 0), + UNIPHIER_PINCTRL_PIN(220, 0), +}; + +static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42}; +static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; +static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46}; +static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1}; +static const unsigned i2c0_pins[] = {109, 110}; +static const unsigned i2c0_muxvals[] = {0, 0}; +static const unsigned i2c1_pins[] = {111, 112}; +static const unsigned i2c1_muxvals[] = {0, 0}; +static const unsigned i2c2_pins[] = {115, 116}; +static const unsigned i2c2_muxvals[] = {1, 1}; +static const unsigned i2c3_pins[] = {118, 119}; +static const unsigned i2c3_muxvals[] = {1, 1}; +static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41, + 42, 43, 44, 45, 46}; +static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}; +static const unsigned nand_cs1_pins[] = {37, 38}; +static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned uart0_pins[] = {135, 136}; +static const unsigned uart0_muxvals[] = {3, 3}; +static const unsigned uart0b_pins[] = {11, 12}; +static const unsigned uart0b_muxvals[] = {2, 2}; +static const unsigned uart1_pins[] = {115, 116}; +static const unsigned uart1_muxvals[] = {0, 0}; +static const unsigned uart1b_pins[] = {113, 114}; +static const unsigned uart1b_muxvals[] = {1, 1}; +static const unsigned uart2_pins[] = {113, 114}; +static const unsigned uart2_muxvals[] = {2, 2}; +static const unsigned uart2b_pins[] = {86, 87}; +static const unsigned uart2b_muxvals[] = {1, 1}; +static const unsigned usb0_pins[] = {56, 57}; +static const unsigned usb0_muxvals[] = {0, 0}; +static const unsigned usb1_pins[] = {58, 59}; +static const unsigned usb1_muxvals[] = {0, 0}; +static const unsigned usb2_pins[] = {60, 61}; +static const unsigned usb2_muxvals[] = {0, 0}; +static const unsigned usb3_pins[] = {62, 63}; +static const unsigned usb3_muxvals[] = {0, 0}; + +static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart0b), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart1b), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart2b), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP(usb3), +}; + +static const char * const ph1_ld6b_functions[] = { + "emmc", + "i2c0", + "i2c1", + "i2c2", + "i2c3", + "nand", + "sd", + "uart0", + "uart1", + "uart2", + "usb0", + "usb1", + "usb2", + "usb3", +}; + +static struct uniphier_pinctrl_socdata ph1_ld6b_pinctrl_socdata = { + .pins = ph1_ld6b_pins, + .pins_count = ARRAY_SIZE(ph1_ld6b_pins), + .groups = ph1_ld6b_groups, + .groups_count = ARRAY_SIZE(ph1_ld6b_groups), + .functions = ph1_ld6b_functions, + .functions_count = ARRAY_SIZE(ph1_ld6b_functions), + .mux_bits = 8, + .reg_stride = 4, + .load_pinctrl = false, +}; + +static int ph1_ld6b_pinctrl_probe(struct udevice *dev) +{ + return uniphier_pinctrl_probe(dev, &ph1_ld6b_pinctrl_socdata); +} + +static const struct udevice_id ph1_ld6b_pinctrl_match[] = { + { .compatible = "socionext,ph1-ld6b-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(ph1_ld6b_pinctrl) = { + .name = "ph1-ld6b-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(ph1_ld6b_pinctrl_match), + .probe = ph1_ld6b_pinctrl_probe, + .remove = uniphier_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), + .ops = &uniphier_pinctrl_ops, +}; -- cgit v1.2.1 From 8497ccc4c23beae38130489d85c97ae38058f20b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 22 Sep 2015 00:27:34 +0900 Subject: ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_* I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify they belong to UniPhier SoC family. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/Kconfig | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 757edce178..2ff616e946 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -5,37 +5,37 @@ config PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_LD4 bool "UniPhier PH1-LD4 SoC pinctrl driver" - depends on MACH_PH1_LD4 + depends on ARCH_UNIPHIER_PH1_LD4 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_PRO4 bool "UniPhier PH1-Pro4 SoC pinctrl driver" - depends on MACH_PH1_PRO4 + depends on ARCH_UNIPHIER_PH1_PRO4 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_SLD8 bool "UniPhier PH1-sLD8 SoC pinctrl driver" - depends on MACH_PH1_SLD8 + depends on ARCH_UNIPHIER_PH1_SLD8 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_PRO5 bool "UniPhier PH1-Pro5 SoC pinctrl driver" - depends on MACH_PH1_PRO5 + depends on ARCH_UNIPHIER_PH1_PRO5 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PROXSTREAM2 bool "UniPhier ProXstream2 SoC pinctrl driver" - depends on MACH_PROXSTREAM2 + depends on ARCH_UNIPHIER_PROXSTREAM2 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_LD6B bool "UniPhier PH1-LD6b SoC pinctrl driver" - depends on MACH_PH1_LD6B + depends on ARCH_UNIPHIER_PH1_LD6B default y select PINCTRL_UNIPHIER_CORE -- cgit v1.2.1 From 4d58e10e3e4900dbad3f44e65769092c631101cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Majewski?= Date: Fri, 25 Sep 2015 18:25:25 +0200 Subject: mmc: dw_mmc: Increase timeout to 4 minutes (as in Linux kernel) The commit: d9dbb97be0e4a550457aec5f11afefb446169c90 "mmc: dw_mmc: Zap endless timeout" removed endless loop waiting for end of dw mmc transfer. For some workloads - dfu test @ Odroid XU3 (sending 8MiB file) - and SD cards (e.g. MicroSD Kingston 4GiB, Adata 4GiB) the default timeout is to short. The new value - 4 minutes (240 seconds) - is the same as the one used in Linux kernel driver. Such fix should be good enough until we come up with better fix for this issue. Signed-off-by: Lukasz Majewski Cc: Marek Vasut Cc: Pantelis Antoniou Cc: Tom Rini Tested-by: Przemyslaw Marczak --- drivers/mmc/dw_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index a84c1e16d8..26d34ae5cc 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -214,7 +214,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (data) { start = get_timer(0); - timeout = 1000; + timeout = 240000; for (;;) { mask = dwmci_readl(host, DWMCI_RINTSTS); /* Error during data transfer. */ -- cgit v1.2.1 From 31c5614af406bdb686c305d707eee2a0898d864e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 31 Aug 2015 16:00:56 +0200 Subject: sunxi_nand_spl: Be smarter about where to look for backup u-boot.bin We know when u-boot is written to its own partition, in this case the layout always is: eb 0 spl eb 1 spl-backup eb 2 u-boot eb 3 u-boot-backup eb: erase-block So if we cannot load u-boot from its primary offset we know exactly where to look for it. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- drivers/mtd/nand/sunxi_nand_spl.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index 5985534e5f..b0e07aa2d0 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -356,18 +356,32 @@ static int nand_read_buffer(uint32_t offs, unsigned int size, void *dest, int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest) { +#if CONFIG_SYS_NAND_U_BOOT_OFFS == CONFIG_SPL_PAD_TO + /* + * u-boot-dtb.bin appended to SPL, use syndrome (like the BROM does) + * and try different erase block sizes to find the backup. + */ const uint32_t boot_offsets[] = { 0 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS, 1 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS, 2 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS, 4 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS, }; - int i, syndrome; - - if (CONFIG_SYS_NAND_U_BOOT_OFFS == CONFIG_SPL_PAD_TO) - syndrome = 1; /* u-boot-dtb.bin appended to SPL */ - else - syndrome = 0; /* u-boot-dtb.bin on its own partition */ + const int syndrome = 1; +#else + /* + * u-boot-dtb.bin on its own partition, do not use syndrome, u-boot + * partition sits after 2 eraseblocks (spl, spl-backup), look for + * backup u-boot 1 erase block further. + */ + const uint32_t eraseblock_size = CONFIG_SYS_NAND_U_BOOT_OFFS / 2; + const uint32_t boot_offsets[] = { + CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_U_BOOT_OFFS + eraseblock_size, + }; + const int syndrome = 0; +#endif + int i; if (offs == CONFIG_SYS_NAND_U_BOOT_OFFS) { for (i = 0; i < ARRAY_SIZE(boot_offsets); i++) { -- cgit v1.2.1 From be90974c4375cec40a91f389dfba244c20b08ef7 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 23 Sep 2015 16:13:10 +0200 Subject: sunxi: mmc: Fix clk-delay settings In recent allwinner kernel sources the mmc/sdio clk-delay settings have been slightly tweaked, and for sun9i they are completely different then what we are using. This commit brings us in sync with what allwinner does, fixing problems accessing sdcards on some A33 devices (and likely others). For pre sun9i hardware this makes the following changes: -At 400Khz change the sample delay from 7 to 0 (first introduced in A31 sdk) -At 50 Mhz change the sample delay from 5 to 4 (first introduced in A23 sdk) -Above 50 MHz change the out delay from 2 to 1 (first introduced in A20 sdk) Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- drivers/mmc/sunxi_mmc.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 25f18adb67..e717c44216 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -120,17 +120,27 @@ static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz) /* determine delays */ if (hz <= 400000) { oclk_dly = 0; - sclk_dly = 7; + sclk_dly = 0; } else if (hz <= 25000000) { oclk_dly = 0; sclk_dly = 5; +#ifdef CONFIG_MACH_SUN9I } else if (hz <= 50000000) { - oclk_dly = 3; - sclk_dly = 5; + oclk_dly = 5; + sclk_dly = 4; } else { /* hz > 50000000 */ oclk_dly = 2; sclk_dly = 4; +#else + } else if (hz <= 50000000) { + oclk_dly = 3; + sclk_dly = 4; + } else { + /* hz > 50000000 */ + oclk_dly = 1; + sclk_dly = 4; +#endif } writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) | -- cgit v1.2.1 From 26d3acdab86a4ade8e9407822d8cdbe51b1f7412 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Thu, 3 Sep 2015 15:50:21 +0530 Subject: net: phy: on phy device create do not initialize link to 1 Currently when phy device is created the link variable is initialized to 1 which denoted phy link is already up. On a power reset there is no issue as phy status register link status will not be set, so phy auto negotiate will be started. But when a cpu reset is issued (ex: dra72x-evm) phy's link status bit is already set which leads to assume that link is already setup in genphy_update_link() initial check which results in ehternet not working. So do not assume that link is already up and on phy device create set link to zero. This is verified on dra72x-evm. Reported-by: Franklin S Cooper Jr Signed-off-by: Mugunthan V N Acked-by: Joe Hershberger --- drivers/net/phy/phy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 65c731afb6..a6023f1033 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -571,7 +571,7 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr, memset(dev, 0, sizeof(*dev)); dev->duplex = -1; - dev->link = 1; + dev->link = 0; dev->interface = interface; dev->autoneg = AUTONEG_ENABLE; -- cgit v1.2.1 From c163e4367908ea625ca962ca6312fc88790b5242 Mon Sep 17 00:00:00 2001 From: Bernhard Nortmann Date: Mon, 14 Sep 2015 15:29:44 +0200 Subject: net: fix netconsole when CONFIG_DM_ETH is set This patch uses the eth_is_active() function to work around issues that prevented compilation with the newer driver model. Signed-off-by: Bernhard Nortmann Acked-by: Joe Hershberger --- drivers/net/netconsole.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index 31042a6b6b..bf972dc39b 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c @@ -170,7 +170,11 @@ int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port, static void nc_send_packet(const char *buf, int len) { +#ifdef CONFIG_DM_ETH + struct udevice *eth; +#else struct eth_device *eth; +#endif int inited = 0; uchar *pkt; uchar *ether; @@ -183,7 +187,7 @@ static void nc_send_packet(const char *buf, int len) return; if (!memcmp(nc_ether, net_null_ethaddr, 6)) { - if (eth->state == ETH_STATE_ACTIVE) + if (eth_is_active(eth)) return; /* inside net loop */ output_packet = buf; output_packet_len = len; @@ -194,7 +198,7 @@ static void nc_send_packet(const char *buf, int len) return; } - if (eth->state != ETH_STATE_ACTIVE) { + if (!eth_is_active(eth)) { if (eth_is_on_demand_init()) { if (eth_init() < 0) return; @@ -292,7 +296,11 @@ static int nc_stdio_getc(struct stdio_dev *dev) static int nc_stdio_tstc(struct stdio_dev *dev) { +#ifdef CONFIG_DM_ETH + struct udevice *eth; +#else struct eth_device *eth; +#endif if (input_recursion) return 0; @@ -301,7 +309,7 @@ static int nc_stdio_tstc(struct stdio_dev *dev) return 1; eth = eth_get_dev(); - if (eth && eth->state == ETH_STATE_ACTIVE) + if (eth_is_active(eth)) return 0; /* inside net loop */ input_recursion = 1; -- cgit v1.2.1 From 03544c6640e8a969f8409eac637f4780e1eabb1d Mon Sep 17 00:00:00 2001 From: "Albert ARIBAUD \\\\(3ADEV\\\\)" Date: Mon, 21 Sep 2015 22:43:38 +0200 Subject: I2C: mxc_i2c: make I2C1 and I2C2 optional The driver assumed that I2C1 and I2C2 were always enabled, and if they were not, then an asynchronous abort was (silently) raised, to be caught much later on in the Linux kernel. Fix this by making I2C1 and I2C2 optional just like I2C3 and I2C4 are. To make the change binary-invariant, declare I2C1 and I2C2 in every include/configs/ file which defines CONFIG_SYS_I2C_MXC. Also, while updating README about CONFIG_SYS_I2C_MXC_I2C1 and CONFIG_SYS_I2C_MXC_I2C2, add missing descriptions for I2C4 speed (CONFIG_SYS_MXC_I2C4_SPEED) and slave (CONFIG_SYS_MXC_I2C4_SLAVE) config options. Signed-off-by: Albert ARIBAUD (3ADEV) --- drivers/i2c/mxc_i2c.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index f1056e21a2..0f977d706d 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -612,16 +612,22 @@ static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) /* * Register mxc i2c adapters */ +#ifdef CONFIG_SYS_I2C_MXC_I2C1 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe, mxc_i2c_read, mxc_i2c_write, mxc_i2c_set_bus_speed, CONFIG_SYS_MXC_I2C1_SPEED, CONFIG_SYS_MXC_I2C1_SLAVE, 0) +#endif + +#ifdef CONFIG_SYS_I2C_MXC_I2C2 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe, mxc_i2c_read, mxc_i2c_write, mxc_i2c_set_bus_speed, CONFIG_SYS_MXC_I2C2_SPEED, CONFIG_SYS_MXC_I2C2_SLAVE, 1) +#endif + #ifdef CONFIG_SYS_I2C_MXC_I2C3 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, mxc_i2c_read, mxc_i2c_write, -- cgit v1.2.1 From f9d3cab091522c8470e9ebd4a8967d00f49efc4a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 23 Sep 2015 12:12:59 -0600 Subject: ARM: tegra: fix GPIO init table programming Tegra's gpio_config_table() currently uses common GPIO APIs. These used to work without requesting the GPIO, but since commit 2fccd2d96bad "tegra: Convert tegra GPIO driver to use driver model" no longer do so. This prevents any of the GPIO initialization table from being applied to HW. Fix gpio_config_table() to directly program the HW to solve this. Fixes: 2fccd2d96bad ("tegra: Convert tegra GPIO driver to use driver model") Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- drivers/gpio/tegra_gpio.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 4921f0ff42..c0ae7719e2 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -211,13 +211,15 @@ void gpio_config_table(const struct tegra_gpio_config *config, int len) for (i = 0; i < len; i++) { switch (config[i].init) { case TEGRA_GPIO_INIT_IN: - gpio_direction_input(config[i].gpio); + set_direction(config[i].gpio, 0); break; case TEGRA_GPIO_INIT_OUT0: - gpio_direction_output(config[i].gpio, 0); + set_level(config[i].gpio, 0); + set_direction(config[i].gpio, 1); break; case TEGRA_GPIO_INIT_OUT1: - gpio_direction_output(config[i].gpio, 1); + set_level(config[i].gpio, 1); + set_direction(config[i].gpio, 1); break; } set_config(config[i].gpio, 1); -- cgit v1.2.1 From 0c35e3a8b406061005c481fccdb9bf2cfe09fd41 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 23 Sep 2015 12:13:00 -0600 Subject: ARM: tegra: don't enable GPIOs until direction is set Tegra's GPIO driver currently enables pins as GPIO as soon as they're requested. This is not safe, since the desired direction and output value are not yet known. This could cause a glitch on the output pins between gpio_request() and gpio_direction_*(), depending on what values happen to be in the GPIO controller's in/out and out-value registers vs. the final desired configuration. To solve this, defer enabling pins as GPIOs until some gpio_direction_*() is invoked, and the desired configuration is explicitly programmed. In theory this change could cause regressions, if code exists that claims a GPIO, never explicitly sets a direction, and then gets/sets the GPIO value based on that assumption. However, I've read through all the Tegra- related board files and device drivers that touch GPIOs and I do not see such buggy code anywhere. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- drivers/gpio/tegra_gpio.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index c0ae7719e2..2dfd02d620 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -136,17 +136,6 @@ static void set_level(unsigned gpio, int high) * Generic_GPIO primitives. */ -static int tegra_gpio_request(struct udevice *dev, unsigned offset, - const char *label) -{ - struct tegra_port_info *state = dev_get_priv(dev); - - /* Configure as a GPIO */ - set_config(state->base_gpio + offset, 1); - - return 0; -} - /* set GPIO pin 'gpio' as an input */ static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset) { @@ -155,6 +144,9 @@ static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset) /* Configure GPIO direction as input. */ set_direction(state->base_gpio + offset, 0); + /* Enable the pin as a GPIO */ + set_config(state->base_gpio + offset, 1); + return 0; } @@ -171,6 +163,9 @@ static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset, /* Configure GPIO direction as output. */ set_direction(gpio, 1); + /* Enable the pin as a GPIO */ + set_config(state->base_gpio + offset, 1); + return 0; } @@ -256,7 +251,6 @@ static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, } static const struct dm_gpio_ops gpio_tegra_ops = { - .request = tegra_gpio_request, .direction_input = tegra_gpio_direction_input, .direction_output = tegra_gpio_direction_output, .get_value = tegra_gpio_get_value, -- cgit v1.2.1 From 9f75a222c7ff8f475e74252c71c3e83e4aef62c5 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 25 Sep 2015 10:44:07 -0600 Subject: gpio: tegra: remove unused type These enum values aren't used anywhere. Remove them. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- drivers/gpio/tegra_gpio.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 2dfd02d620..f9c06fe88b 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -25,13 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; -enum { - TEGRA_CMD_INFO, - TEGRA_CMD_PORT, - TEGRA_CMD_OUTPUT, - TEGRA_CMD_INPUT, -}; - struct tegra_gpio_platdata { struct gpio_ctlr_bank *bank; const char *port_name; /* Name of port, e.g. "B" */ -- cgit v1.2.1 From fe82857c4b1667fff8108eab77340ae76016215a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 25 Sep 2015 10:44:08 -0600 Subject: gpio: tegra: use named constants In order to make it clear what the parameters to set_config() and set_direction() mean, and similarly for the return values from the respective get_*(), define named constants for these values. Disassembly shows no diff in the generated code, except that the order of the code in the branches of tegra_gpio_get_function() gets modified without affecting behaviour. Suggested-by: Tom Warren Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- drivers/gpio/tegra_gpio.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index f9c06fe88b..8e880e276f 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -1,6 +1,6 @@ /* * NVIDIA Tegra20 GPIO handling. - * (C) Copyright 2010-2012 + * (C) Copyright 2010-2012,2015 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ @@ -25,6 +25,11 @@ DECLARE_GLOBAL_DATA_PTR; +static const int CONFIG_SFIO = 0; +static const int CONFIG_GPIO = 1; +static const int DIRECTION_INPUT = 0; +static const int DIRECTION_OUTPUT = 1; + struct tegra_gpio_platdata { struct gpio_ctlr_bank *bank; const char *port_name; /* Name of port, e.g. "B" */ @@ -37,7 +42,7 @@ struct tegra_port_info { int base_gpio; /* Port number for this port (0, 1,.., n-1) */ }; -/* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */ +/* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */ static int get_config(unsigned gpio) { struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; @@ -46,15 +51,15 @@ static int get_config(unsigned gpio) int type; u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); - type = (u >> GPIO_BIT(gpio)) & 1; + type = (u >> GPIO_BIT(gpio)) & 1; debug("get_config: port = %d, bit = %d is %s\n", GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); - return type; + return type ? CONFIG_GPIO : CONFIG_SFIO; } -/* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */ +/* Config pin 'gpio' as GPIO or SFIO, based on 'type' */ static void set_config(unsigned gpio, int type) { struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; @@ -65,7 +70,7 @@ static void set_config(unsigned gpio, int type) GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); - if (type) /* GPIO */ + if (type != CONFIG_SFIO) u |= 1 << GPIO_BIT(gpio); else u &= ~(1 << GPIO_BIT(gpio)); @@ -86,7 +91,7 @@ static int get_direction(unsigned gpio) debug("get_direction: port = %d, bit = %d, %s\n", GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN"); - return dir; + return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT; } /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */ @@ -100,7 +105,7 @@ static void set_direction(unsigned gpio, int output) GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN"); u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); - if (output) + if (output != DIRECTION_INPUT) u |= 1 << GPIO_BIT(gpio); else u &= ~(1 << GPIO_BIT(gpio)); @@ -135,7 +140,7 @@ static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset) struct tegra_port_info *state = dev_get_priv(dev); /* Configure GPIO direction as input. */ - set_direction(state->base_gpio + offset, 0); + set_direction(state->base_gpio + offset, DIRECTION_INPUT); /* Enable the pin as a GPIO */ set_config(state->base_gpio + offset, 1); @@ -154,7 +159,7 @@ static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset, set_level(gpio, value); /* Configure GPIO direction as output. */ - set_direction(gpio, 1); + set_direction(gpio, DIRECTION_OUTPUT); /* Enable the pin as a GPIO */ set_config(state->base_gpio + offset, 1); @@ -199,18 +204,18 @@ void gpio_config_table(const struct tegra_gpio_config *config, int len) for (i = 0; i < len; i++) { switch (config[i].init) { case TEGRA_GPIO_INIT_IN: - set_direction(config[i].gpio, 0); + set_direction(config[i].gpio, DIRECTION_INPUT); break; case TEGRA_GPIO_INIT_OUT0: set_level(config[i].gpio, 0); - set_direction(config[i].gpio, 1); + set_direction(config[i].gpio, DIRECTION_OUTPUT); break; case TEGRA_GPIO_INIT_OUT1: set_level(config[i].gpio, 1); - set_direction(config[i].gpio, 1); + set_direction(config[i].gpio, DIRECTION_OUTPUT); break; } - set_config(config[i].gpio, 1); + set_config(config[i].gpio, CONFIG_GPIO); } } -- cgit v1.2.1 From 6f183e869e4e1f42c0f0587883661b780bcbee4f Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 30 Sep 2015 13:14:51 +0200 Subject: gpio: s5p: call: dev_get_addr() instead of fdtdec_get_addr() After rework in lib/fdtdec.c, the function fdtdec_get_addr() doesn't work for nodes with #size-cells property set to 0. To get GPIO's 'reg' property, the code should use one of: fdtdec_get_addr_size_auto_no/parent() function. Fortunately dm core provides a function to get the property. This commit reworks function gpio_exynos_bind(), to properly use dev_get_addr() for GPIO device. This prevents setting a wrong base register for Exynos GPIOs. Tested on: Odroid U3/X2, Trats, Trats2, Odroid XU3, Snow (by Simon). Signed-off-by: Przemyslaw Marczak Acked-by: Stephen Warren Acked-by: Simon Glass Tested-by: Simon Glass --- drivers/gpio/s5p_gpio.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 17fcfbf4d3..0f22b238ba 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -341,18 +341,22 @@ static int gpio_exynos_bind(struct udevice *parent) plat = calloc(1, sizeof(*plat)); if (!plat) return -ENOMEM; - reg = fdtdec_get_addr(blob, node, "reg"); - if (reg != FDT_ADDR_T_NONE) - bank = (struct s5p_gpio_bank *)((ulong)base + reg); - plat->bank = bank; - plat->bank_name = fdt_get_name(blob, node, NULL); - debug("dev at %p: %s\n", bank, plat->bank_name); + plat->bank_name = fdt_get_name(blob, node, NULL); ret = device_bind(parent, parent->driver, - plat->bank_name, plat, -1, &dev); + plat->bank_name, plat, -1, &dev); if (ret) return ret; + dev->of_offset = node; + + reg = dev_get_addr(dev); + if (reg != FDT_ADDR_T_NONE) + bank = (struct s5p_gpio_bank *)((ulong)base + reg); + + plat->bank = bank; + + debug("dev at %p: %s\n", bank, plat->bank_name); } return 0; -- cgit v1.2.1 From d18f37c72b864323d6d1fb03685bfe04b9a7be28 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 29 Sep 2015 12:32:03 +0900 Subject: serial: rockchip: make ROCKCHIP_SERIAL depend on ARCH_ROCKCHIP It looks like this line was copy-pasted, but not modified. Signed-off-by: Masahiro Yamada Acked-by: Simon Glass --- drivers/serial/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ccb80d2d1d..ddb725d326 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -111,7 +111,7 @@ config DEBUG_UART_SHIFT config ROCKCHIP_SERIAL bool "Rockchip on-chip UART support" - depends on ARCH_UNIPHIER && DM_SERIAL + depends on ARCH_ROCKCHIP && DM_SERIAL help Select this to enable a debug UART for Rockchip devices. This uses the ns16550 driver. You will need to #define CONFIG_SYS_NS16550 in -- cgit v1.2.1 From 84d26e296ab62b172f73b5367d9b7295309dfdd5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 12 Sep 2015 08:45:19 -0600 Subject: dm: core: Don't use pinctrl for the root device Currently when driver model starts up it finds the root uclass and the pinctrl uclass. This is because even the root node handles pinctrl processing. But this is not useful. The root node is not a real hardware device so cannot require any particular pinmux settings. Also it means that the memory leak tests fails, since they end up freeing more memory than they allocate: the marker it set after the root device and pinctrl uclass are allocated, and later once the pinctrl uclass is freed the memory used by driver model is less than when the marker was set. If a platform needs 'core' pin mulitplex settings it can do this with a driver that is probed on start-up. It would be an abuse of the root node to use this for pinctrl. To avoid this problem, only process pinctrl settings for non-root nodes. Signed-off-by: Simon Glass --- drivers/core/device.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/core/device.c b/drivers/core/device.c index 0bc04d4876..833a803696 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -289,8 +289,12 @@ int device_probe_child(struct udevice *dev, void *parent_priv) dev->flags |= DM_FLAG_ACTIVATED; - /* continue regardless of the result of pinctrl */ - pinctrl_select_state(dev, "default"); + /* + * Process pinctrl for everything except the root device, and + * continue regardless of the result of pinctrl. + */ + if (dev->parent) + pinctrl_select_state(dev, "default"); ret = uclass_pre_probe_device(dev); if (ret) -- cgit v1.2.1 From 7bb91dd109e2aff5f7f51aed44ac7890f9a4d158 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 3 Oct 2015 11:21:16 -0600 Subject: sandbox: Correct operaion of 'reset' command Currently 'reset' only works with the test device tree. When run without a device tree, or with the normal device tree, the following error is displayed: Reset not supported on this platform Fix the driver and the standard device tree to avoid this. Signed-off-by: Simon Glass Reported-by: Stephen Warren Tested-by: Stephen Warren --- drivers/misc/reset_sandbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/misc/reset_sandbox.c b/drivers/misc/reset_sandbox.c index 917121bc5e..2691bb031a 100644 --- a/drivers/misc/reset_sandbox.c +++ b/drivers/misc/reset_sandbox.c @@ -40,7 +40,7 @@ static int sandbox_reset_request(struct udevice *dev, enum reset_t type) * (see the U_BOOT_DEVICE() declaration below) should not do anything. * If we are that device, return an error. */ - if (gd->fdt_blob && dev->of_offset == -1) + if (state->fdt_fname && dev->of_offset == -1) return -ENODEV; switch (type) { -- cgit v1.2.1 From 7445435fb32824e0cfd05beb7013be8f84e9ee09 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 7 Oct 2015 02:13:18 -0700 Subject: pci: Fix expansion ROM programming for multi-function devices PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator for multi-function devices. We should mask it off before using it as the header type. Signed-off-by: Bin Meng Acked-by: Simon Glass --- drivers/pci/pci_auto.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 41d5447f12..79f27c744b 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -185,6 +185,7 @@ void pciauto_setup_device(struct pci_controller *hose, #ifndef CONFIG_PCI_ENUM_ONLY /* Configure the expansion ROM address */ pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); + header_type &= 0x7f; if (header_type != PCI_HEADER_TYPE_CARDBUS) { rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1; -- cgit v1.2.1 From d5f60737dbaac82f3f7d49eb03ece443beb70fc8 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 8 Sep 2015 01:26:29 +0530 Subject: spi: xilinx_spi: Fix to configure CPOL, CPHA mask priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki --- drivers/spi/xilinx_spi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 6c21acda57..8ccc5780c9 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -247,7 +247,7 @@ static int xilinx_spi_set_speed(struct udevice *bus, uint speed) priv->freq = speed; - debug("xilinx_spi_set_speed: regs=%p, mode=%d\n", priv->regs, + debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs, priv->freq); return 0; @@ -260,13 +260,13 @@ static int xilinx_spi_set_mode(struct udevice *bus, uint mode) uint32_t spicr; spicr = readl(®s->spicr); - if (priv->mode & SPI_LSB_FIRST) + if (mode & SPI_LSB_FIRST) spicr |= SPICR_LSB_FIRST; - if (priv->mode & SPI_CPHA) + if (mode & SPI_CPHA) spicr |= SPICR_CPHA; - if (priv->mode & SPI_CPOL) + if (mode & SPI_CPOL) spicr |= SPICR_CPOL; - if (priv->mode & SPI_LOOP) + if (mode & SPI_LOOP) spicr |= SPICR_LOOP; writel(spicr, ®s->spicr); -- cgit v1.2.1 From a22bba81e40959c3675b794422508911034049d4 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 8 Sep 2015 01:38:50 +0530 Subject: spi: zynq_spi: Fix to configure CPOL, CPHA mask priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki --- drivers/spi/zynq_spi.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 310fb69c8d..d370e495cd 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -272,7 +272,8 @@ static int zynq_spi_set_speed(struct udevice *bus, uint speed) writel(confr, ®s->cr); priv->freq = speed; - debug("zynq_spi_set_speed: regs=%p, mode=%d\n", priv->regs, priv->freq); + debug("zynq_spi_set_speed: regs=%p, speed=%d\n", + priv->regs, priv->freq); return 0; } @@ -287,9 +288,9 @@ static int zynq_spi_set_mode(struct udevice *bus, uint mode) confr = readl(®s->cr); confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK); - if (priv->mode & SPI_CPHA) + if (mode & SPI_CPHA) confr |= ZYNQ_SPI_CR_CPHA_MASK; - if (priv->mode & SPI_CPOL) + if (mode & SPI_CPOL) confr |= ZYNQ_SPI_CR_CPOL_MASK; writel(confr, ®s->cr); -- cgit v1.2.1 From 5cb1b7b395c0150e179f3b748d755cdc2f613a06 Mon Sep 17 00:00:00 2001 From: Mirza Krak Date: Tue, 8 Sep 2015 10:30:49 +0200 Subject: spi: tegra20: Add support for mode selection Respect the mode passed in set_mode ops. Signed-off-by: Mirza Krak Reviewed-by: Jagan Teki --- drivers/spi/tegra20_slink.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'drivers') diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c index fbb665b86f..144716fd91 100644 --- a/drivers/spi/tegra20_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -36,6 +36,11 @@ DECLARE_GLOBAL_DATA_PTR; #define SLINK_CMD_ENB (1 << 31) #define SLINK_CMD_GO (1 << 30) #define SLINK_CMD_M_S (1 << 28) +#define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24) +#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH (1 << 24) +#define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24) +#define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24) +#define SLINK_CMD_IDLE_SCLK_MASK (3 << 24) #define SLINK_CMD_CK_SDA (1 << 21) #define SLINK_CMD_CS_POL (1 << 13) #define SLINK_CMD_CS_VAL (1 << 12) @@ -331,6 +336,22 @@ static int tegra30_spi_set_speed(struct udevice *bus, uint speed) static int tegra30_spi_set_mode(struct udevice *bus, uint mode) { struct tegra30_spi_priv *priv = dev_get_priv(bus); + struct spi_regs *regs = priv->regs; + u32 reg; + + reg = readl(®s->command); + + /* Set CPOL and CPHA */ + reg &= ~(SLINK_CMD_IDLE_SCLK_MASK | SLINK_CMD_CK_SDA); + if (mode & SPI_CPHA) + reg |= SLINK_CMD_CK_SDA; + + if (mode & SPI_CPOL) + reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH; + else + reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW; + + writel(reg, ®s->command); priv->mode = mode; debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); -- cgit v1.2.1 From f2b76c6037f8d2f54e938f42ad9ef01488c11425 Mon Sep 17 00:00:00 2001 From: Yao Yuan Date: Tue, 15 Sep 2015 18:28:19 +0800 Subject: mtd: sf: Add support AT26DF081A chip AT26DF081A is the spi flash type of TWR-MEM(SCH-26248) card. We can access the flash through DSPI2 on LS1021ATWR board. Signed-off-by: Yuan Yao Reviewed-by: Jagan Teki --- drivers/mtd/spi/sf_params.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 4a4a3afc92..8f5bdda3d7 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -23,6 +23,7 @@ const struct spi_flash_params spi_flash_params_table[] = { {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, + {"AT26DF081A", 0x1f4501, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K}, #endif #ifdef CONFIG_SPI_FLASH_EON /* EON */ {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, RD_NORM, 0}, -- cgit v1.2.1 From 04386f656bbc35abd7718a4bbbba7fcfb4f59aef Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 2 Oct 2015 08:20:35 +0200 Subject: Revert "powerpc: ppc4xx: remove lwmon5 support" This reverts commit 8fe11b8901a31d11990488c82bc23612589d57be. I'll add support to lwmon5 in the next patch and will remove support for the broken lcd4_lwmon5 as well. Signed-off-by: Stefan Roese Cc: Masahiro Yamada --- drivers/video/mb862xx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c index 868c51254d..1c74e97c5e 100644 --- a/drivers/video/mb862xx.c +++ b/drivers/video/mb862xx.c @@ -419,7 +419,8 @@ void *video_hw_init (void) board_disp_init (); #endif -#if defined(CONFIG_SOCRATES) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON) +#if (defined(CONFIG_LWMON5) || \ + defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON) /* Lamp on */ board_backlight_switch (1); #endif -- cgit v1.2.1 From d1d0167663ada7c8fdb4d9d50d3fe132ac5a8b5e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ezequiel=20Garc=C3=ADa?= Date: Sun, 4 Oct 2015 18:34:42 -0300 Subject: nand: omap_gpmc: Change correctable bit-flips messages to debug() Messages on corrected bit-flips are not really useful, as bit-flips are perfectly normal. Let's avoid cluttering the console and make them debug. Signed-off-by: Ezequiel Garcia --- drivers/mtd/nand/omap_gpmc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 4372988ed2..4814fa202a 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -558,10 +558,10 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, bit_pos = error_loc[count] % 8; if (byte_pos < SECTOR_BYTES) { dat[byte_pos] ^= 1 << bit_pos; - printf("nand: bit-flip corrected @data=%d\n", byte_pos); + debug("nand: bit-flip corrected @data=%d\n", byte_pos); } else if (byte_pos < error_max) { read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos; - printf("nand: bit-flip corrected @oob=%d\n", byte_pos - + debug("nand: bit-flip corrected @oob=%d\n", byte_pos - SECTOR_BYTES); } else { err = -EBADMSG; @@ -663,7 +663,7 @@ static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data, /* correct data only, not ecc bytes */ if (errloc[i] < 8*512) data[errloc[i]/8] ^= 1 << (errloc[i] & 7); - printf("corrected bitflip %u\n", errloc[i]); + debug("corrected bitflip %u\n", errloc[i]); #ifdef DEBUG puts("read_ecc: "); /* -- cgit v1.2.1 From f532727d16ebd3f8f9464aa503a1990f2f3b3211 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 3 Oct 2015 14:20:59 -0300 Subject: imx_watchdog: Add a header file for watchdog registers Create fsl_wdog.h to store the watchdog registers and bit fields. This can be useful when accesses to the watchdog block are made from other parts, such as arch/arm/ cpu code. Signed-off-by: Fabio Estevam --- drivers/watchdog/imx_watchdog.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 9a77a54192..0d775956bf 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -8,19 +8,7 @@ #include #include #include - -struct watchdog_regs { - u16 wcr; /* Control */ - u16 wsr; /* Service */ - u16 wrsr; /* Reset Status */ -}; - -#define WCR_WDZST 0x01 -#define WCR_WDBG 0x02 -#define WCR_WDE 0x04 /* WDOG enable */ -#define WCR_WDT 0x08 -#define WCR_SRS 0x10 -#define SET_WCR_WT(x) (x << 8) +#include #ifdef CONFIG_IMX_WATCHDOG void hw_watchdog_reset(void) -- cgit v1.2.1 From f861f51c4673d35908e4e330a86c81d7d909b51c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 3 Oct 2015 14:21:00 -0300 Subject: ls102xa: Fix reset hang Since commit 623d96e89aca6("imx: wdog: correct wcr register settings") issuing a 'reset' command causes the system to hang. Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian. This means that the watchdog on LS1021 has been working by accident as it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c. Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only revelead the endianness problem on LS102x. In order to fix the reset hang, introduce a reset_cpu() implementation that is specific for ls102x, which accesses the watchdog WCR register in big-endian format. All that is required to reset LS102x is to clear the SRS bit. This approach is a temporary workaround to avoid a regression for LS102x in the 2015.10 release. The proper fix is to make the watchdog driver endian-aware, so that it can work for i.MX, Vybrid and LS102x. Reported-by: Sinan Akman Tested-by: Sinan Akman Reviewed-by: Wolfgang Denk Signed-off-by: Fabio Estevam --- drivers/watchdog/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 9e9cb55069..a007ae8234 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o -ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610 ls102xa)) +ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610)) obj-y += imx_watchdog.o endif obj-$(CONFIG_S5P) += s5p_wdt.o -- cgit v1.2.1