From b825f158e449e1e9cf74c08e572955e122394c96 Mon Sep 17 00:00:00 2001 From: roy zang Date: Thu, 2 Nov 2006 19:12:31 +0800 Subject: Tsi108 on chip i2c support. The i2c Interface provides a master-only, serial interface that can be used for initializing Tsi108/Tsi109 registers from an EEPROM after a device reset. Signed-off-by: Alexandre Bounine Signed-off-by: Roy Zang --- drivers/tsi108_i2c.c | 300 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 300 insertions(+) create mode 100644 drivers/tsi108_i2c.c (limited to 'drivers/tsi108_i2c.c') diff --git a/drivers/tsi108_i2c.c b/drivers/tsi108_i2c.c new file mode 100644 index 0000000000..08e5e3b4f5 --- /dev/null +++ b/drivers/tsi108_i2c.c @@ -0,0 +1,300 @@ +/* + * (C) Copyright 2004 Tundra Semiconductor Corp. + * Author: Alex Bounine + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include + +#ifdef CONFIG_TSI108_I2C + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) + +#define I2C_DELAY 100000 +#undef DEBUG_I2C + +#ifdef DEBUG_I2C +#define DPRINT(x) printf(x) +#else +#define DPRINT(x) +#endif + +/* All functions assume that Tsi108 I2C block is the only master on the bus */ +/* I2C read helper function */ + +static int i2c_read_byte( + uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */ + uchar chip_addr,/* I2C device address on the bus */ + uint byte_addr, /* Byte address within I2C device */ + uchar * buffer /* pointer to data buffer */ + ) +{ + u32 temp; + u32 to_count = I2C_DELAY; + u32 op_status = TSI108_I2C_TIMEOUT_ERR; + u32 chan_offset = TSI108_I2C_OFFSET; + + DPRINT(("I2C read_byte() %d 0x%02x 0x%02x\n", + i2c_chan, chip_addr, byte_addr)); + + if (0 != i2c_chan) { + chan_offset = TSI108_I2C_SDRAM_OFFSET; + } + + /* Check if I2C operation is in progress */ + temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); + + if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | + I2C_CNTRL2_START)) + ) { + /* Set device address and operation (read = 0) */ + temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) | + ((chip_addr >> 3) & 0x0F); + *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) = + temp; + + /* Issue the read command + * (at this moment all other parameters are 0 + * (size = 1 byte, lane = 0) + */ + + *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) = + (I2C_CNTRL2_START); + + /* Wait until operation completed */ + do { + /* Read I2C operation status */ + temp = + *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + + I2C_CNTRL2); + + if (0 == + (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) + { + if (0 == + (temp & + (I2C_CNTRL2_I2C_CFGERR | + I2C_CNTRL2_I2C_TO_ERR)) + ) { + op_status = TSI108_I2C_SUCCESS; + + temp = *(u32 *) (CFG_TSI108_CSR_BASE + + chan_offset + + I2C_RD_DATA); + + *buffer = (u8) (temp & 0xFF); + } else { + /* report HW error */ + op_status = TSI108_I2C_IF_ERROR; + + DPRINT(("I2C HW error reported: 0x%02x\n", temp)); + } + + break; + } + } while (to_count--); + } else { + op_status = TSI108_I2C_IF_BUSY; + + DPRINT(("I2C Transaction start failed: 0x%02x\n", temp)); + } + + DPRINT(("I2C read_byte() status: 0x%02x\n", op_status)); + return op_status; +} + +/* + * I2C Read interface as defined in "include/i2c.h" : + * chip_addr: I2C chip address, range 0..127 + * (to read from SPD channel EEPROM use (0xD0 ... 0xD7) + * NOTE: The bit 7 in the chip_addr serves as a channel select. + * This hack is for enabling "isdram" command on Tsi108 boards + * without changes to common code. Used for I2C reads only. + * byte_addr: Memory or register address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Pointer to destination buffer for data to be read + * len: How many bytes to read + * + * Returns: 0 on success, not 0 on failure + */ + +int i2c_read(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len) +{ + u32 op_status = TSI108_I2C_PARAM_ERR; + u32 i2c_if = 0; + + /* Hack to support second (SPD) I2C controller (SPD EEPROM read only).*/ + if (0xD0 == (chip_addr & ~0x07)) { + i2c_if = 1; + chip_addr &= 0x7F; + } + /* Check for valid I2C address */ + if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { + while (len--) { + op_status = + i2c_read_byte(i2c_if, chip_addr, byte_addr++, + buffer++); + + if (TSI108_I2C_SUCCESS != op_status) { + DPRINT(("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len)); + + break; + } + } + } + + DPRINT(("I2C read() status: 0x%02x\n", op_status)); + return op_status; +} + +/* I2C write helper function */ + +static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */ + uint byte_addr, /* Byte address within I2C device */ + uchar * buffer /* pointer to data buffer */ + ) +{ + u32 temp; + u32 to_count = I2C_DELAY; + u32 op_status = TSI108_I2C_TIMEOUT_ERR; + + /* Check if I2C operation is in progress */ + temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); + + if (0 == + (temp & + (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) + { + /* Place data into the I2C Tx Register */ + *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + + I2C_TX_DATA) = (u32) * buffer; + + /* Set device address and operation */ + temp = + I2C_CNTRL1_I2CWRITE | (byte_addr << 16) | + ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F); + *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + + I2C_CNTRL1) = temp; + + /* Issue the write command (at this moment all other parameters + * are 0 (size = 1 byte, lane = 0) + */ + + *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + + I2C_CNTRL2) = (I2C_CNTRL2_START); + + op_status = TSI108_I2C_TIMEOUT_ERR; + + /* Wait until operation completed */ + do { + // Read I2C operation status + temp = + *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + + I2C_CNTRL2); + + if (0 == + (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) + { + if (0 == + (temp & + (I2C_CNTRL2_I2C_CFGERR | + I2C_CNTRL2_I2C_TO_ERR))) { + op_status = TSI108_I2C_SUCCESS; + } else { + /* report detected HW error */ + op_status = TSI108_I2C_IF_ERROR; + + DPRINT(("I2C HW error reported: 0x%02x\n", temp)); + } + + break; + } + + } while (to_count--); + } else { + op_status = TSI108_I2C_IF_BUSY; + + DPRINT(("I2C Transaction start failed: 0x%02x\n", temp)); + } + + return op_status; +} + +/* + * I2C Write interface as defined in "include/i2c.h" : + * chip_addr: I2C chip address, range 0..127 + * byte_addr: Memory or register address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Pointer to data to be written + * len: How many bytes to write + * + * Returns: 0 on success, not 0 on failure + */ + +int i2c_write(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, + int len) +{ + u32 op_status = TSI108_I2C_PARAM_ERR; + + /* Check for valid I2C address */ + if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { + while (len--) { + op_status = + i2c_write_byte(chip_addr, byte_addr++, buffer++); + + if (TSI108_I2C_SUCCESS != op_status) { + DPRINT(("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len)); + + break; + } + } + } + + return op_status; +} + +/* + * I2C interface function as defined in "include/i2c.h". + * Probe the given I2C chip address by reading single byte from offset 0. + * Returns 0 if a chip responded, not 0 on failure. + */ + +int i2c_probe(uchar chip) +{ + u32 tmp; + + /* + * Try to read the first location of the chip. + * The Tsi108 HW doesn't support sending just the chip address + * and checkong for an back. + */ + return i2c_read(chip, 0, 1, (char *)&tmp, 1); +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */ +#endif /* CONFIG_TSI108_I2C */ -- cgit v1.2.1 From ee311214e0d216f904feea269599d0934bf71f23 Mon Sep 17 00:00:00 2001 From: roy zang Date: Fri, 1 Dec 2006 11:47:36 +0800 Subject: Clean up the code according to codestyle: (1) remove some C++ comments. (2) remove trailing white space. (3) remove trailing empty line. (4) Indentation by table. (5) remove {} in one line condition. (6) add space before '(' in function call. Remove some weird printf () output. Add necessary comments. Modified Makefile to support building in a separate directory. --- drivers/tsi108_i2c.c | 60 +++++++++++++++++++++++++--------------------------- 1 file changed, 29 insertions(+), 31 deletions(-) (limited to 'drivers/tsi108_i2c.c') diff --git a/drivers/tsi108_i2c.c b/drivers/tsi108_i2c.c index 08e5e3b4f5..c100cb8247 100644 --- a/drivers/tsi108_i2c.c +++ b/drivers/tsi108_i2c.c @@ -23,19 +23,18 @@ */ #include +#include #ifdef CONFIG_TSI108_I2C - -#include #include #if (CONFIG_COMMANDS & CFG_CMD_I2C) -#define I2C_DELAY 100000 +#define I2C_DELAY 100000 #undef DEBUG_I2C #ifdef DEBUG_I2C -#define DPRINT(x) printf(x) +#define DPRINT(x) printf (x) #else #define DPRINT(x) #endif @@ -43,7 +42,7 @@ /* All functions assume that Tsi108 I2C block is the only master on the bus */ /* I2C read helper function */ -static int i2c_read_byte( +static int i2c_read_byte ( uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */ uchar chip_addr,/* I2C device address on the bus */ uint byte_addr, /* Byte address within I2C device */ @@ -55,19 +54,17 @@ static int i2c_read_byte( u32 op_status = TSI108_I2C_TIMEOUT_ERR; u32 chan_offset = TSI108_I2C_OFFSET; - DPRINT(("I2C read_byte() %d 0x%02x 0x%02x\n", + DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n", i2c_chan, chip_addr, byte_addr)); - if (0 != i2c_chan) { + if (0 != i2c_chan) chan_offset = TSI108_I2C_SDRAM_OFFSET; - } /* Check if I2C operation is in progress */ temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | - I2C_CNTRL2_START)) - ) { + I2C_CNTRL2_START))) { /* Set device address and operation (read = 0) */ temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F); @@ -75,7 +72,7 @@ static int i2c_read_byte( temp; /* Issue the read command - * (at this moment all other parameters are 0 + * (at this moment all other parameters are 0 * (size = 1 byte, lane = 0) */ @@ -108,7 +105,7 @@ static int i2c_read_byte( /* report HW error */ op_status = TSI108_I2C_IF_ERROR; - DPRINT(("I2C HW error reported: 0x%02x\n", temp)); + DPRINT (("I2C HW error reported: 0x%02x\n", temp)); } break; @@ -117,20 +114,20 @@ static int i2c_read_byte( } else { op_status = TSI108_I2C_IF_BUSY; - DPRINT(("I2C Transaction start failed: 0x%02x\n", temp)); + DPRINT (("I2C Transaction start failed: 0x%02x\n", temp)); } - DPRINT(("I2C read_byte() status: 0x%02x\n", op_status)); + DPRINT (("I2C read_byte() status: 0x%02x\n", op_status)); return op_status; } -/* +/* * I2C Read interface as defined in "include/i2c.h" : * chip_addr: I2C chip address, range 0..127 * (to read from SPD channel EEPROM use (0xD0 ... 0xD7) * NOTE: The bit 7 in the chip_addr serves as a channel select. * This hack is for enabling "isdram" command on Tsi108 boards - * without changes to common code. Used for I2C reads only. + * without changes to common code. Used for I2C reads only. * byte_addr: Memory or register address within the chip * alen: Number of bytes to use for addr (typically 1, 2 for larger * memories, 0 for register type devices with only one @@ -141,7 +138,8 @@ static int i2c_read_byte( * Returns: 0 on success, not 0 on failure */ -int i2c_read(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len) +int i2c_read (uchar chip_addr, uint byte_addr, int alen, + uchar * buffer, int len) { u32 op_status = TSI108_I2C_PARAM_ERR; u32 i2c_if = 0; @@ -159,20 +157,20 @@ int i2c_read(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len) buffer++); if (TSI108_I2C_SUCCESS != op_status) { - DPRINT(("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len)); + DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len)); break; } } } - DPRINT(("I2C read() status: 0x%02x\n", op_status)); + DPRINT (("I2C read() status: 0x%02x\n", op_status)); return op_status; } /* I2C write helper function */ -static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */ +static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */ uint byte_addr, /* Byte address within I2C device */ uchar * buffer /* pointer to data buffer */ ) @@ -210,7 +208,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */ /* Wait until operation completed */ do { - // Read I2C operation status + /* Read I2C operation status */ temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); @@ -227,7 +225,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */ /* report detected HW error */ op_status = TSI108_I2C_IF_ERROR; - DPRINT(("I2C HW error reported: 0x%02x\n", temp)); + DPRINT (("I2C HW error reported: 0x%02x\n", temp)); } break; @@ -237,13 +235,13 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */ } else { op_status = TSI108_I2C_IF_BUSY; - DPRINT(("I2C Transaction start failed: 0x%02x\n", temp)); + DPRINT (("I2C Transaction start failed: 0x%02x\n", temp)); } return op_status; } -/* +/* * I2C Write interface as defined in "include/i2c.h" : * chip_addr: I2C chip address, range 0..127 * byte_addr: Memory or register address within the chip @@ -256,7 +254,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */ * Returns: 0 on success, not 0 on failure */ -int i2c_write(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, +int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len) { u32 op_status = TSI108_I2C_PARAM_ERR; @@ -265,10 +263,10 @@ int i2c_write(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { while (len--) { op_status = - i2c_write_byte(chip_addr, byte_addr++, buffer++); + i2c_write_byte (chip_addr, byte_addr++, buffer++); if (TSI108_I2C_SUCCESS != op_status) { - DPRINT(("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len)); + DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len)); break; } @@ -278,13 +276,13 @@ int i2c_write(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, return op_status; } -/* +/* * I2C interface function as defined in "include/i2c.h". * Probe the given I2C chip address by reading single byte from offset 0. * Returns 0 if a chip responded, not 0 on failure. */ -int i2c_probe(uchar chip) +int i2c_probe (uchar chip) { u32 tmp; @@ -293,8 +291,8 @@ int i2c_probe(uchar chip) * The Tsi108 HW doesn't support sending just the chip address * and checkong for an back. */ - return i2c_read(chip, 0, 1, (char *)&tmp, 1); + return i2c_read (chip, 0, 1, (char *)&tmp, 1); } -#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */ +#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */ #endif /* CONFIG_TSI108_I2C */ -- cgit v1.2.1