From 5066e62847bddf6030262ade2aa3e7bcdc930037 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Thu, 26 Mar 2015 16:13:09 +0800 Subject: T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue T2080QDS PEX1/Slot#1 will down-train from x4 to x2, with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15. Soft reset PCIe can fix this issue. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- drivers/pci/fsl_pci_init.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers/pci') diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 231b07573f..152045ed93 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -444,6 +444,21 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) ltssm = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; enabled = (ltssm == 0x11) ? 1 : 0; +#ifdef CONFIG_FSL_PCIE_RESET + int i; + /* assert PCIe reset */ + setbits_be32(&pci->pdb_stat, 0x08000000); + (void) in_be32(&pci->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(&pci->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { + pci_hose_read_config_word(hose, dev, PCI_LTSSM, + <ssm); + udelay(1000); + } +#endif } else { /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */ /* enabled = ltssm >= PCI_LTSSM_L0; */ -- cgit v1.2.1 From 1d0b59a9b049443397f484ad03b88c6314bc7ebb Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Fri, 27 Mar 2015 13:24:39 +0800 Subject: fsl/pci: Set CFG_READY for PCIe v3.0 and later Freescale PCIe controllers v3.0 and later need to set bit CFG_READY to allow all inbound configuration transactions to be processed normally when in EP mode. However, bit CFG_READY has been moved from PCIe configuration space to CCSR PCIe configuration register comparing previous version. The patch is to set this bit according to PCIe version. Signed-off-by: Ed Swarthout Signed-off-by: Roy Zang Signed-off-by: Minghuan Lian Reviewed-by: York Sun --- drivers/pci/fsl_pci_init.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers/pci') diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 152045ed93..52792dcd59 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -697,8 +697,14 @@ void fsl_pci_config_unlock(struct pci_controller *hose) pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); if (pcie_cap != 0x0) { + ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr; + u32 block_rev = in_be32(&pci->block_rev1); /* PCIe - set CFG_READY bit of Configuration Ready Register */ - pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1); + if (block_rev >= PEX_IP_BLK_REV_3_0) + setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY); + else + pci_hose_write_config_byte(hose, dev, + FSL_PCIE_CFG_RDY, 0x1); } else { /* PCI - clear ACL bit of PBFR */ pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr); -- cgit v1.2.1