From 422cb08acb1bc9a05ffa68ba68b4e196dad1af5b Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 19 Mar 2015 09:20:43 -0700 Subject: armv8/fsl-lsch3: Add Freescale Debug Server driver The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma Reviewed-by: York Sun --- drivers/net/fsl-mc/mc.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/net/fsl-mc') diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 74b0085301..76581cbfda 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -9,6 +9,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; static int mc_boot_status; @@ -112,6 +113,9 @@ int mc_init(bd_t *bis) gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; } +#ifdef CONFIG_FSL_DEBUG_SERVER + mc_ram_addr -= debug_server_get_dram_block_size(); +#endif /* * Management Complex cores should be held at reset out of POR. * U-boot should be the first software to touch MC. To be safe, -- cgit v1.2.1