From 2aa8720257beadde8f798bd30096ca4c9007c8e0 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 28 Nov 2011 06:37:33 +0000 Subject: davinci_emac: fix for running with dcache enabled DaVinci EMAC is present on TI AM35xx SoCs (ARMv7) which run with D-Cache enabled by default. So we have to take care and flush/invalidate the cache before/after the DMA operations. Please note that the receive buffer alignment to 32 byte boundary comes from the old driver version I don't know if it is really needed or alignment to cache line size is enough. Signed-off-by: Ilya Yanok --- drivers/net/davinci_emac.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/net/davinci_emac.h') diff --git a/drivers/net/davinci_emac.h b/drivers/net/davinci_emac.h index a42c93aa60..37c841ca84 100644 --- a/drivers/net/davinci_emac.h +++ b/drivers/net/davinci_emac.h @@ -24,8 +24,9 @@ /* Ethernet Min/Max packet size */ #define EMAC_MIN_ETHERNET_PKT_SIZE 60 #define EMAC_MAX_ETHERNET_PKT_SIZE 1518 -/* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ -#define EMAC_PKT_ALIGN 18 +/* Buffer size (should be aligned on 32 byte and cache line) */ +#define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\ + ARCH_DMA_MINALIGN) /* Number of RX packet buffers * NOTE: Only 1 buffer supported as of now -- cgit v1.2.1