From a46b1852de967f8a7de26e0b46e864c794a18c16 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 20 Nov 2015 15:52:04 +0800 Subject: fsl/ddr: updated ddr errata-A008378 for arm and power SoCs DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- drivers/ddr/fsl/fsl_ddr_gen4.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers/ddr/fsl') diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 50f4671c8f..0755ff7c24 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -10,6 +10,7 @@ #include #include #include +#include #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) @@ -238,9 +239,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, /* Erratum applies when accumulated ECC is used, or DBI is enabled */ #define IS_ACC_ECC_EN(v) ((v) & 0x4) #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) - if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || - IS_DBI(regs->ddr_sdram_cfg_3)) - ddr_setbits32(ddr->debug[28], 0x9 << 20); + if (has_erratum_a008378()) { + if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || + IS_DBI(regs->ddr_sdram_cfg_3)) + ddr_setbits32(&ddr->debug[28], 0x9 << 20); + } #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 -- cgit v1.2.1