From 938bbb6013f051808c08204184e94d0cdcb6dbff Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 2 Dec 2014 11:18:09 -0800 Subject: driver/ddr/fsl: Fix MRC_CYC calculation for DDR3 For DDR controller version 4.7 or newer, MRC_CYC (mode register set cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD is max(12nCK, 15ns) according to JEDEC spec. DDR4 is not affected by this change. Signed-off-by: York Sun --- drivers/ddr/fsl/ctrl_regs.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) (limited to 'drivers/ddr/fsl') diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index fe8aa98e8e..03d7ff17dd 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -324,6 +324,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, #elif defined(CONFIG_SYS_FSL_DDR3) unsigned int data_rate = get_ddr_freq(0); int txp; + unsigned int ip_rev; int odt_overlap; /* * (tXARD and tXARDS). Empirical? @@ -336,7 +337,25 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, */ txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000)); - tmrd_mclk = 4; + ip_rev = fsl_ddr_get_version(); + if (ip_rev >= 0x40700) { + /* + * MRS_CYC = max(tMRD, tMOD) + * tMRD = 4nCK (8nCK for RDIMM) + * tMOD = max(12nCK, 15ns) + */ + tmrd_mclk = max((unsigned int)12, picos_to_mclk(15000)); + } else { + /* + * MRS_CYC = tMRD + * tMRD = 4nCK (8nCK for RDIMM) + */ + if (popts->registered_dimm_en) + tmrd_mclk = 8; + else + tmrd_mclk = 4; + } + /* set the turnaround time */ /* -- cgit v1.2.1