From 9db1bfa110ac411ab3468e817f7f74b2439eb8c8 Mon Sep 17 00:00:00 2001 From: David Jander Date: Wed, 13 Jul 2011 21:11:53 +0000 Subject: ARM: MX51: PLL errata workaround This is a port of the official PLL errata workaround from Freescale to mainline u-boot. The PLL's in the i.MX51 processor can go out of lock due to a metastable condition in an analog flip-flop when used at high frequencies. This workaround implements an undocumented feature in the PLL (dither mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. Signed-off-by: David Jander --- doc/README.imx5 | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 doc/README.imx5 (limited to 'doc') diff --git a/doc/README.imx5 b/doc/README.imx5 new file mode 100644 index 0000000000..f7eab7d4b2 --- /dev/null +++ b/doc/README.imx5 @@ -0,0 +1,17 @@ +U-Boot for Freescale i.MX5x + +This file contains information for the port of U-Boot to the Freescale +i.MX5x SoCs. + +1. CONFIGURATION OPTIONS/SETTINGS +--------------------------------- + +1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata. + This option should be enabled by all boards using the i.MX51 silicon + version up until (including) 3.0 running at 800MHz. + The PLL's in the i.MX51 processor can go out of lock due to a metastable + condition in an analog flip-flop when used at high frequencies. + This workaround implements an undocumented feature in the PLL (dither + mode), which causes the effect of this failure to be much lower (in terms + of frequency deviation), avoiding system failure, or at least decreasing + the likelihood of system failure. -- cgit v1.2.1