From 69366bf42f22d67efce8da3f8c40a43d4a3c2695 Mon Sep 17 00:00:00 2001 From: roy zang Date: Thu, 2 Nov 2006 18:34:47 +0800 Subject: Add README file for mpc7448hpc2 board. Signed-off-by: Roy Zang --- doc/README.mpc7448hpc2 | 193 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) create mode 100644 doc/README.mpc7448hpc2 (limited to 'doc') diff --git a/doc/README.mpc7448hpc2 b/doc/README.mpc7448hpc2 new file mode 100644 index 0000000000..5142a0f638 --- /dev/null +++ b/doc/README.mpc7448hpc2 @@ -0,0 +1,193 @@ +Freescale MPC7448hpc2 (Taiga) board +=================================== + +Created 08/11/2006 Roy Zang +-------------------------- +MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference +design, which is optimized for high speed throughput between the processor and +the memory, disk drive and Ethernet port subsystems. + +MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be +used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX +chassis. + +Building U-Boot +------------------ +The mpc7448hpc2 code base is known to compile using: + Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 + + $ make mpc7448hpc2_config + Configuring for mpc7448hpc2 board... + + $ make + +Memory Map +---------- + +The memory map is setup for Linux to operate properly. + +The mapping is: + + Range Start Range End Definition Size + + 0x0000_0000 0x7fff_ffff DDR 2G + 0xe000_0000 0xe7ff_ffff PCI Memory 128M + 0xfa00_0000 0xfaff_ffff PCI IO 16M + 0xfb00_0000 0xfbff_ffff PCI Config 16M + 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M + 0xfe00_0000 0xfeff_ffff PromJet 16M + 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M + 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M + + +Using Flash +----------- + +The MPC7448hpc2 board has two "banks" of flash, each 8MB in size +(2^23 = 0x00800000). + +Note: the "bank" here refers to half of the flash. In fact, there is only one +bank of flash, which is divided into low and high half. Each is controlled by +the most significant bit of the address bus. The so called "bank" is only for +convenience. + +There is a switch which allows the "bank" to be selected. The switch +settings for updating flash are given below. + +The u-boot commands for copying the boot-bank into the secondary bank are +as follows: + + erase ff800000 ff880000 + cp.b ff000000 ff800000 80000 + +U-boot commands for downloading an image via tftp and flashing +it into the secondary bank: + + tftp 10000 + erase ff000000 ff080000 + cp.b 10000 ff000000 80000 + + +After copying the image into the second bank of flash, be sure to toggle +SW3[4] on board before resetting the board in order to set the +secondary bank as the boot-bank. + + +Board Switches +---------------------- + + +Most switches on the board should not be changed. The most frequent +user-settable switches on the board are used to configure +the flash banks and determining the PCI frequency. + +SW1[1-5]: Processor core voltage + + 12345 Core Voltage + ----- + SW1=01111 1.000V. + SW1=01101 1.100V. + SW1=01011 1.200V. + SW1=01001 1.300V only for MPC7447A. + + +SW2[1-6]: CPU core frequency + + CPU Core Frequency (MHz) + Bus Frequency + 123456 100 133 167 200 Ratio + + ------ + SW2=101100 500 667 833 1000 5x + SW2=100100 550 733 917 1100 5.5x + SW2=110100 600 800 1000 1200 6x + SW2=010100 650 866 1083 1300 6.5x + SW2=001000 700 930 1167 1400 7x + SW2=000100 750 1000 1250 1500 7.5x + SW2=110000 800 1066 1333 1600 8x + SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A + SW2=011110 900 1200 1500 1800 9x + +This table shows only a subset of available frequency options; see the CPU +hardware specifications for more information. + + +SW2[7-8]: Bus Protocol and CPU Reset Option + + 7 + - + SW2=0 System bus uses MPX bus protocol + SW2=1 System bus uses 60x bus protocol + + 8 + - + SW2=0 TSI108 can cause CPU reset + SW2=1 TSI108 can not cause CPU reset + + +SW3[1-8] system options + + 123 + --- + SW3=xxx Connected to GPIO[0:2] on TSI108 + + 4 + - + SW3=0 CPU boots from low half of flash + SW3=1 CPU boots from high half of flash + + 5 + - + SW3=0 SATA and slot2 connected to PCI bus + SW3=1 Only slot1 connected to PCI bus + + 6 + - + SW3=0 USB connected to PCI bus + SW3=1 USB disconnected from PCI bus + + 7 + - + SW3=0 Flash is write protected + SW3=1 Flash is NOT write protected + + 8 + - + SW3=0 CPU will boot from flash + SW3=1 CPU will boot from PromJet + +SW4[1-3]: System bus frequency + + Bus Frequency (MHz) + --- + SW4=010 183 + SW4=011 100 + SW4=100 133 + SW4=101 166 only for MPC7447A + SW4=110 200 only for MPC7448 + others reserved + + +SW4[4-6]: DDR2 SDRAM frequency + + Bus Frequency (MHz) + --- + SW4=000 external clock + SW4=011 system clock + SW4=100 133 + SW4=101 166 + SW4=110 200 + others reserved + + +SW4[7-8]: PCI/PCI-X frequency control + 7 + - + SW4=0 PCI/PCI-X bus operates normally + SW4=1 PCI bus forced to PCI-33 mode + + 8 + - + SW4=0 PCI-X mode at 133 MHz allowed + SW4=1 PCI-X mode limited to 100 MHz + -- cgit v1.2.1 From ee311214e0d216f904feea269599d0934bf71f23 Mon Sep 17 00:00:00 2001 From: roy zang Date: Fri, 1 Dec 2006 11:47:36 +0800 Subject: Clean up the code according to codestyle: (1) remove some C++ comments. (2) remove trailing white space. (3) remove trailing empty line. (4) Indentation by table. (5) remove {} in one line condition. (6) add space before '(' in function call. Remove some weird printf () output. Add necessary comments. Modified Makefile to support building in a separate directory. --- doc/README.mpc7448hpc2 | 206 ++++++++++++++++++++++++------------------------- 1 file changed, 99 insertions(+), 107 deletions(-) (limited to 'doc') diff --git a/doc/README.mpc7448hpc2 b/doc/README.mpc7448hpc2 index 5142a0f638..0e40e39269 100644 --- a/doc/README.mpc7448hpc2 +++ b/doc/README.mpc7448hpc2 @@ -3,23 +3,23 @@ Freescale MPC7448hpc2 (Taiga) board Created 08/11/2006 Roy Zang -------------------------- -MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference -design, which is optimized for high speed throughput between the processor and +MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference +design, which is optimized for high speed throughput between the processor and the memory, disk drive and Ethernet port subsystems. -MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be -used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX +MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be +used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX chassis. Building U-Boot ------------------ The mpc7448hpc2 code base is known to compile using: - Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 + Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 - $ make mpc7448hpc2_config - Configuring for mpc7448hpc2 board... + $ make mpc7448hpc2_config + Configuring for mpc7448hpc2 board... - $ make + $ make Memory Map ---------- @@ -28,25 +28,24 @@ The memory map is setup for Linux to operate properly. The mapping is: - Range Start Range End Definition Size - - 0x0000_0000 0x7fff_ffff DDR 2G - 0xe000_0000 0xe7ff_ffff PCI Memory 128M - 0xfa00_0000 0xfaff_ffff PCI IO 16M - 0xfb00_0000 0xfbff_ffff PCI Config 16M - 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M - 0xfe00_0000 0xfeff_ffff PromJet 16M - 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M - 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M + Range Start Range End Definition Size + 0x0000_0000 0x7fff_ffff DDR 2G + 0xe000_0000 0xe7ff_ffff PCI Memory 128M + 0xfa00_0000 0xfaff_ffff PCI IO 16M + 0xfb00_0000 0xfbff_ffff PCI Config 16M + 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M + 0xfe00_0000 0xfeff_ffff PromJet 16M + 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M + 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M Using Flash ----------- -The MPC7448hpc2 board has two "banks" of flash, each 8MB in size -(2^23 = 0x00800000). +The MPC7448hpc2 board has two "banks" of flash, each 8MB in size +(2^23 = 0x00800000). -Note: the "bank" here refers to half of the flash. In fact, there is only one +Note: the "bank" here refers to half of the flash. In fact, there is only one bank of flash, which is divided into low and high half. Each is controlled by the most significant bit of the address bus. The so called "bank" is only for convenience. @@ -57,137 +56,130 @@ settings for updating flash are given below. The u-boot commands for copying the boot-bank into the secondary bank are as follows: - erase ff800000 ff880000 - cp.b ff000000 ff800000 80000 + erase ff800000 ff880000 + cp.b ff000000 ff800000 80000 U-boot commands for downloading an image via tftp and flashing it into the secondary bank: - tftp 10000 - erase ff000000 ff080000 - cp.b 10000 ff000000 80000 - + tftp 10000 + erase ff000000 ff080000 + cp.b 10000 ff000000 80000 After copying the image into the second bank of flash, be sure to toggle SW3[4] on board before resetting the board in order to set the secondary bank as the boot-bank. - Board Switches ---------------------- - Most switches on the board should not be changed. The most frequent user-settable switches on the board are used to configure the flash banks and determining the PCI frequency. SW1[1-5]: Processor core voltage - 12345 Core Voltage - ----- - SW1=01111 1.000V. - SW1=01101 1.100V. - SW1=01011 1.200V. - SW1=01001 1.300V only for MPC7447A. + 12345 Core Voltage + ----- + SW1=01111 1.000V. + SW1=01101 1.100V. + SW1=01011 1.200V. + SW1=01001 1.300V only for MPC7447A. SW2[1-6]: CPU core frequency - CPU Core Frequency (MHz) + CPU Core Frequency (MHz) Bus Frequency - 123456 100 133 167 200 Ratio + 123456 100 133 167 200 Ratio - ------ - SW2=101100 500 667 833 1000 5x - SW2=100100 550 733 917 1100 5.5x - SW2=110100 600 800 1000 1200 6x - SW2=010100 650 866 1083 1300 6.5x - SW2=001000 700 930 1167 1400 7x - SW2=000100 750 1000 1250 1500 7.5x - SW2=110000 800 1066 1333 1600 8x - SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A - SW2=011110 900 1200 1500 1800 9x - -This table shows only a subset of available frequency options; see the CPU + ------ + SW2=101100 500 667 833 1000 5x + SW2=100100 550 733 917 1100 5.5x + SW2=110100 600 800 1000 1200 6x + SW2=010100 650 866 1083 1300 6.5x + SW2=001000 700 930 1167 1400 7x + SW2=000100 750 1000 1250 1500 7.5x + SW2=110000 800 1066 1333 1600 8x + SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A + SW2=011110 900 1200 1500 1800 9x + +This table shows only a subset of available frequency options; see the CPU hardware specifications for more information. - SW2[7-8]: Bus Protocol and CPU Reset Option - 7 - - - SW2=0 System bus uses MPX bus protocol - SW2=1 System bus uses 60x bus protocol - - 8 - - - SW2=0 TSI108 can cause CPU reset - SW2=1 TSI108 can not cause CPU reset + 7 + - + SW2=0 System bus uses MPX bus protocol + SW2=1 System bus uses 60x bus protocol + 8 + - + SW2=0 TSI108 can cause CPU reset + SW2=1 TSI108 can not cause CPU reset SW3[1-8] system options - 123 - --- - SW3=xxx Connected to GPIO[0:2] on TSI108 + 123 + --- + SW3=xxx Connected to GPIO[0:2] on TSI108 - 4 - - - SW3=0 CPU boots from low half of flash - SW3=1 CPU boots from high half of flash + 4 + - + SW3=0 CPU boots from low half of flash + SW3=1 CPU boots from high half of flash - 5 - - - SW3=0 SATA and slot2 connected to PCI bus - SW3=1 Only slot1 connected to PCI bus + 5 + - + SW3=0 SATA and slot2 connected to PCI bus + SW3=1 Only slot1 connected to PCI bus - 6 - - - SW3=0 USB connected to PCI bus - SW3=1 USB disconnected from PCI bus + 6 + - + SW3=0 USB connected to PCI bus + SW3=1 USB disconnected from PCI bus - 7 - - - SW3=0 Flash is write protected - SW3=1 Flash is NOT write protected + 7 + - + SW3=0 Flash is write protected + SW3=1 Flash is NOT write protected - 8 - - - SW3=0 CPU will boot from flash - SW3=1 CPU will boot from PromJet + 8 + - + SW3=0 CPU will boot from flash + SW3=1 CPU will boot from PromJet SW4[1-3]: System bus frequency Bus Frequency (MHz) - --- - SW4=010 183 - SW4=011 100 - SW4=100 133 - SW4=101 166 only for MPC7447A - SW4=110 200 only for MPC7448 - others reserved - + --- + SW4=010 183 + SW4=011 100 + SW4=100 133 + SW4=101 166 only for MPC7447A + SW4=110 200 only for MPC7448 + others reserved SW4[4-6]: DDR2 SDRAM frequency Bus Frequency (MHz) - --- - SW4=000 external clock - SW4=011 system clock - SW4=100 133 - SW4=101 166 - SW4=110 200 - others reserved - + --- + SW4=000 external clock + SW4=011 system clock + SW4=100 133 + SW4=101 166 + SW4=110 200 + others reserved SW4[7-8]: PCI/PCI-X frequency control - 7 - - - SW4=0 PCI/PCI-X bus operates normally - SW4=1 PCI bus forced to PCI-33 mode - - 8 - - - SW4=0 PCI-X mode at 133 MHz allowed - SW4=1 PCI-X mode limited to 100 MHz + 7 + - + SW4=0 PCI/PCI-X bus operates normally + SW4=1 PCI bus forced to PCI-33 mode + + 8 + - + SW4=0 PCI-X mode at 133 MHz allowed + SW4=1 PCI-X mode limited to 100 MHz -- cgit v1.2.1 From 647d3c3eed0da1d1505eecabe0b0fab96f956e68 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 4 Mar 2007 01:36:05 +0100 Subject: Some code cleanup. --- doc/README.mpc7448hpc2 | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) (limited to 'doc') diff --git a/doc/README.mpc7448hpc2 b/doc/README.mpc7448hpc2 index 0e40e39269..8659e83673 100644 --- a/doc/README.mpc7448hpc2 +++ b/doc/README.mpc7448hpc2 @@ -92,7 +92,7 @@ SW2[1-6]: CPU core frequency CPU Core Frequency (MHz) Bus Frequency 123456 100 133 167 200 Ratio - + ------ SW2=101100 500 667 833 1000 5x SW2=100100 550 733 917 1100 5.5x @@ -109,43 +109,43 @@ hardware specifications for more information. SW2[7-8]: Bus Protocol and CPU Reset Option - 7 + 7 - SW2=0 System bus uses MPX bus protocol SW2=1 System bus uses 60x bus protocol - 8 + 8 - SW2=0 TSI108 can cause CPU reset SW2=1 TSI108 can not cause CPU reset SW3[1-8] system options - 123 + 123 --- SW3=xxx Connected to GPIO[0:2] on TSI108 - 4 + 4 - SW3=0 CPU boots from low half of flash SW3=1 CPU boots from high half of flash - 5 + 5 - SW3=0 SATA and slot2 connected to PCI bus SW3=1 Only slot1 connected to PCI bus - 6 + 6 - SW3=0 USB connected to PCI bus SW3=1 USB disconnected from PCI bus - 7 + 7 - SW3=0 Flash is write protected SW3=1 Flash is NOT write protected - 8 + 8 - SW3=0 CPU will boot from flash SW3=1 CPU will boot from PromJet @@ -166,20 +166,19 @@ SW4[4-6]: DDR2 SDRAM frequency Bus Frequency (MHz) --- SW4=000 external clock - SW4=011 system clock + SW4=011 system clock SW4=100 133 SW4=101 166 SW4=110 200 others reserved SW4[7-8]: PCI/PCI-X frequency control - 7 + 7 - SW4=0 PCI/PCI-X bus operates normally SW4=1 PCI bus forced to PCI-33 mode - 8 + 8 - SW4=0 PCI-X mode at 133 MHz allowed SW4=1 PCI-X mode limited to 100 MHz - -- cgit v1.2.1 From 443feb740584e406efa203af909fe2926608e8d5 Mon Sep 17 00:00:00 2001 From: Igor Marnat Date: Wed, 21 Mar 2007 09:55:01 +0300 Subject: Update usage of 'nc' in README.NetConsole Added information about usage of NetConsole on systems where the -l and -p switches are mutually exclusive. Signed-off-by: Igor Marnat Signed-off-by: Ben Warren --- doc/README.NetConsole | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'doc') diff --git a/doc/README.NetConsole b/doc/README.NetConsole index cc35a0a8ff..fea8e33646 100644 --- a/doc/README.NetConsole +++ b/doc/README.NetConsole @@ -38,6 +38,11 @@ The script expects exactly one argument, which is interpreted as the target IP address (or host name, assuming DNS is working). The script can be interrupted by pressing ^T (CTRL-T). +Be aware that in some distributives (Fedora Core 5 at least) +usage of nc has been changed and -l and -p options are considered +as mutually exclusive. If nc complains about options provided, +you can just remove the -p option from the script. + It turns out that 'netcat' cannot be used to listen to broadcast packets. We developed our own tool 'ncb' (see tools directory) that listens to broadcast packets on a given port and dumps them to the -- cgit v1.2.1 From 3d98b85800c80dc68227c8f10bf5c93456d6d054 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Mon, 22 Jan 2007 12:37:30 -0600 Subject: Add PIXIS FPGA support for MPC8641HPCN board. Move the 8641HPCN's PIXIS code to the new directory board/freescale/common/ as it will be shared by future boards not in the same processor family. Write a "pixis_reset" command that utilizes the FPGA reset sequencer to support alternate soft-reset options such as using the "alternate" flash bank, enabling the watch dog, or choosing different CPU frequencies. Add documentation for the pixis_reset to README.mpc8641hpcn. Signed-off-by: Haiying Wang Signed-off-by: Jon Loeliger --- doc/README.mpc8641hpcn | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'doc') diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn index 4a650ce43c..3b88f8bc72 100644 --- a/doc/README.mpc8641hpcn +++ b/doc/README.mpc8641hpcn @@ -121,3 +121,37 @@ To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF): 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 16M 0xfe00_0000 0xfeff_ffff Flash(alternate)16M 0xff00_0000 0xffff_ffff Flash(boot bank)16M + +5. pixis_reset command +-------------------- +A new command, "pixis_reset", is introduced to reset mpc8641hpcn board +using the FPGA sequencer. When the board restarts, it has the option +of using either the current or alternate flash bank as the boot +image, with or without the watchdog timer enabled, and finally with +or without frequency changes. + +Usage is; + + pixis_reset + pixis_reset altbank + pixis_reset altbank wd + pixis_reset altbank cf + pixis_reset cf + +Examples; + + /* reset to current bank, like "reset" command */ + pixis_reset + + /* reset board but use the to alternate flash bank */ + pixis_reset altbank + + /* reset board, use alternate flash bank with watchdog timer enabled*/ + pixis_reset altbank wd + + /* reset board to alternate bank with frequency changed. + * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio + */ + pixis-reset altbank cf 40 2.5 10 + +Valid clock choices are in the 8641 Reference Manuals. -- cgit v1.2.1 From 3747a3f010b2b1442dec3e871c69788b6017aaae Mon Sep 17 00:00:00 2001 From: Domen Puncer Date: Wed, 18 Apr 2007 12:11:05 +0200 Subject: [PATCH] icecube/lite5200b: document wakeup from low-power support Signed-off-by: Domen Puncer --- doc/README.Lite5200B_low_power | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 doc/README.Lite5200B_low_power (limited to 'doc') diff --git a/doc/README.Lite5200B_low_power b/doc/README.Lite5200B_low_power new file mode 100644 index 0000000000..5b04fbba72 --- /dev/null +++ b/doc/README.Lite5200B_low_power @@ -0,0 +1,22 @@ +Lite5200B wakeup from low-power mode (CONFIG_LITE5200B_PM) +---------------------------------------------------------- + +Low-power mode as described in Lite5200B User's Manual, means that +with support of MC68HLC908QT1 microcontroller (refered to as QT), +everything but the SDRAM can be powered down. This brings +maximum power saving, while one can still restore previous state +quickly. + +Quick overview where U-Boot comes into the picture: +- OS saves device states +- OS saves wakeup handler address to physical 0x0, puts SDRAM into + self-refresh and signals to QT, it should power down the board +- / board is sleeping here / +- someone presses SW4 (connected to QT) +- U-Boot checks PSC2_4 pin, if QT drives it down, then we woke up, + so get SDRAM out of self-refresh and transfer control to OS + wakeup handler +- OS restores device states + +This was tested on Linux with USB and Ethernet in use. Adding +support for other devices is an OS issue. -- cgit v1.2.1