From 7fd101c97b58dab7b0bd87f30c3dedb0db21d15f Mon Sep 17 00:00:00 2001 From: york Date: Fri, 2 Jul 2010 22:25:54 +0000 Subject: powerpc/8xxx: Enabled address hashing for 85xx For 85xx silicon which supports address hashing, it can be activated by hwconfig. Signed-off-by: York Sun --- doc/README.fsl-ddr | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'doc/README.fsl-ddr') diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 8c37bbead1..e108a0d50c 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -71,5 +71,16 @@ The ways to configure the ddr interleaving mode # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3" - The above memory controller interleaving and bank interleaving can be mixed. The syntax is - setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1" +Memory controller address hashing +================================== +If the DDR controller supports address hashing, it can be enabled by hwconfig. + +Syntax is: +hwconfig=fsl_ddr:addr_hash=true + +Combination of hwconfig +======================= +Hwconfig can be combined with multiple parameters, for example, on a supported +platform + +hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3 -- cgit v1.2.1