From 076bff8f4746baf7c83b96049d97e9dd4454dace Mon Sep 17 00:00:00 2001 From: york Date: Fri, 2 Jul 2010 22:25:52 +0000 Subject: powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual rank with 512MB each rank. Also check dimm size and rank size for memory controller interleaving Signed-off-by: York Sun --- doc/README.fsl-ddr | 3 +++ 1 file changed, 3 insertions(+) (limited to 'doc/README.fsl-ddr') diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 6e4f6e9244..8c37bbead1 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -27,6 +27,9 @@ Table of interleaving modes supported in cpu/8xxx/ddr/ from each controller. {CS2+CS3} on each controller are only rank interleaved on that controller. + For memory controller interleaving, identical DIMMs are suggested. Software + doesn't check the size or organization of interleaved DIMMs. + The ways to configure the ddr interleaving mode ============================================== 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting -- cgit v1.2.1