From 8564acf936726c5568d71e4fa93a0ae9814e0d07 Mon Sep 17 00:00:00 2001 From: wdenk Date: Mon, 14 Jul 2003 22:13:32 +0000 Subject: * Patches by Yuli Barcohen, 13 Jul 2003: - Correct flash and JFFS2 support for MPC8260ADS - fix PVR values and clock generation for PowerQUICC II family (8270/8275/8280) * Patch by Bernhard Kuhn, 08 Jul 2003: - add support for M68K targets * Patch by Ken Chou, 3 Jul: - Fix PCI config table for A3000 - Fix iobase for natsemi.c (PCI_BASE_ADDRESS_0 is the IO base register for DP83815) * Allow to enable "slow" POST routines by key press on power-on * Fix temperature dependend switching of LCD backlight on LWMON * Tweak output format for LWMON --- cpu/mpc8260/commproc.c | 11 ++-- cpu/mpc8260/cpu.c | 27 ++++++++-- cpu/mpc8260/speed.c | 16 +++--- cpu/mpc8xx/lcd.c | 19 +++++++ cpu/mpc8xx/video.c | 133 ++++++++++++++++++++++++++++++++++++++----------- 5 files changed, 163 insertions(+), 43 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc8260/commproc.c b/cpu/mpc8260/commproc.c index c523ee4dca..72cceb3cc4 100644 --- a/cpu/mpc8260/commproc.c +++ b/cpu/mpc8260/commproc.c @@ -111,9 +111,9 @@ m8260_cpm_hostalloc(uint size, uint align) * to port numbers). Documentation uses 1-based numbering. */ #define BRG_INT_CLK gd->brg_clk -#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16) +#define BRG_UART_CLK (BRG_INT_CLK / 16) -/* This function is used by UARTS, or anything else that uses a 16x +/* This function is used by UARTs, or anything else that uses a 16x * oversampled clock. */ void @@ -123,9 +123,10 @@ m8260_cpm_setbrg(uint brg, uint rate) volatile immap_t *immr = (immap_t *)CFG_IMMR; volatile uint *bp; + uint cd = BRG_UART_CLK / rate; - /* This is good enough to get SMCs running..... - */ + if ((BRG_UART_CLK % rate) < (rate / 2)) + cd--; if (brg < 4) { bp = (uint *)&immr->im_brgc1; } @@ -134,7 +135,7 @@ m8260_cpm_setbrg(uint brg, uint rate) brg -= 4; } bp += brg; - *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; + *bp = (cd << 1) | CPM_BRG_EN; } /* This function is used to set high speed synchronous baud rate diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c index 7662fc652a..2736702595 100644 --- a/cpu/mpc8260/cpu.c +++ b/cpu/mpc8260/cpu.c @@ -22,7 +22,7 @@ */ /* - * CPU specific code for the MPC8255 / MPC8260 CPUs + * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x * * written or collected and sometimes rewritten by * Magnus Damm @@ -35,6 +35,9 @@ * * added 8260 masks by * Marius Groeger + * + * added HiP7 (8270/8275/8280) processors support by + * Yuli Barcohen */ #include @@ -56,15 +59,27 @@ int checkcpu (void) puts ("CPU: "); - if (((pvr >> 16) & 0xff) != 0x81) + switch (pvr) { + case PVR_8260: + case PVR_8260_HIP3: + k = 3; + break; + case PVR_8260_HIP4: + k = 4; + break; + case PVR_8260_HIP7: + k = 7; + break; + default: return -1; /* whoops! not an MPC8260 */ + } rev = pvr & 0xff; immr = immap->im_memctl.memc_immr; if ((immr & IMMR_ISB_MSK) != CFG_IMMR) return -1; /* whoops! someone moved the IMMR */ - printf (CPU_ID_STR " (Rev %02x, Mask ", rev); + printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev); /* * the bottom 16 bits of the immr are the Part Number and Mask Number @@ -104,6 +119,12 @@ int checkcpu (void) case 0x0062: printf ("B.1 4K25A"); break; + case 0x0A00: + printf ("0.0 0K49M"); + break; + case 0x0A01: + printf ("0.1 1K49M"); + break; default: printf ("unknown [immr=0x%04x,k=0x%04x]", m, k); break; diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c index 1f53c4f4c8..6a3176a3a7 100644 --- a/cpu/mpc8260/speed.c +++ b/cpu/mpc8260/speed.c @@ -120,15 +120,19 @@ int get_clocks (void) scmr = immap->im_clkrst.car_scmr; corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT; - busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT; - cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; - plldf = (scmr & SCMR_PLLDF) ? 1 : 0; - pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; - cp = &corecnf_tab[corecnf]; - gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1); + busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT; + cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; + if (get_pvr () == PVR_8260_HIP7) { /* HiP7 */ + pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT; + gd->vco_out = clkin * (pllmf + 1); + } else { /* HiP3, HiP4 */ + pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; + plldf = (scmr & SCMR_PLLDF) ? 1 : 0; + gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1); + } #if 0 if (gd->vco_out / (busdf + 1) != clkin) { /* aaarrrggghhh!!! */ diff --git a/cpu/mpc8xx/lcd.c b/cpu/mpc8xx/lcd.c index 9f4b210820..ec9fbfce0d 100644 --- a/cpu/mpc8xx/lcd.c +++ b/cpu/mpc8xx/lcd.c @@ -25,6 +25,8 @@ /* ** HEADER FILES */ /************************************************************************/ +/* #define DEBUG */ + #include #include #include @@ -1057,6 +1059,23 @@ static void lcd_enable (void) /* Now turn on LCD_ON */ immr->im_cpm.cp_pbdat |= 0x00001000; #endif +#ifdef CONFIG_RRVISION + debug ("PC4->Output(1): enable LVDS\n"); + debug ("PC5->Output(0): disable PAL clock\n"); + immr->im_ioport.iop_pddir |= 0x1000; + immr->im_ioport.iop_pcpar &= ~(0x0C00); + immr->im_ioport.iop_pcdir |= 0x0C00 ; + immr->im_ioport.iop_pcdat |= 0x0800 ; + immr->im_ioport.iop_pcdat &= ~(0x0400); + debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n", + immr->im_ioport.iop_pdpar, + immr->im_ioport.iop_pddir, + immr->im_ioport.iop_pddat); + debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n", + immr->im_ioport.iop_pcpar, + immr->im_ioport.iop_pcdir, + immr->im_ioport.iop_pcdat); +#endif } /*----------------------------------------------------------------------*/ diff --git a/cpu/mpc8xx/video.c b/cpu/mpc8xx/video.c index 40e65d30bd..1887cfe8ab 100644 --- a/cpu/mpc8xx/video.c +++ b/cpu/mpc8xx/video.c @@ -23,7 +23,7 @@ * MA 02111-1307 USA */ -/* #define DEBUG */ +/* #define DEBUG */ /************************************************************************/ /* ** HEADER FILES */ @@ -86,6 +86,14 @@ #define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7177_ADDR #endif +#ifdef CONFIG_VIDEO_ENCODER_AD7179 + +#include /* Sets encoder data, mode, and visible and active area */ + +#define VIDEO_I2C 1 +#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7179_ADDR +#endif + /************************************************************************/ /* ** VIDEO MODE CONSTANTS */ /************************************************************************/ @@ -155,7 +163,7 @@ /* ** CONSOLE CONSTANTS */ /************************************************************************/ -#ifdef CONFIG_VIDEO_LOGO +#ifdef CONFIG_VIDEO_LOGO #define CONSOLE_ROWS ((VIDEO_ROWS - VIDEO_LOGO_HEIGHT) / VIDEO_FONT_HEIGHT) #define VIDEO_LOGO_SKIP (VIDEO_COLS - VIDEO_LOGO_WIDTH) #else @@ -163,11 +171,11 @@ #endif #define CONSOLE_COLS (VIDEO_COLS / VIDEO_FONT_WIDTH) -#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * VIDEO_LINE_LEN) +#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * VIDEO_LINE_LEN) #define CONSOLE_ROW_FIRST (video_console_address) -#define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE) +#define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE) #define CONSOLE_ROW_LAST (video_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE) -#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) +#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) #define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) /* @@ -287,8 +295,8 @@ static int video_maprgb (int r, int g, int b) /* Calculate YUV values (0-255) from RGB beetween 0-100 */ YUYV.Y1 = YUYV.Y2 = 209 * (pR + pG + pB) / 300 + 16; - YUYV.U = pR - (pG * 3 / 4) - (pB / 4) + 128; - YUYV.V = pB - (pR / 4) - (pG * 3 / 4) + 128; + YUYV.U = pR - (pG * 3 / 4) - (pB / 4) + 128; + YUYV.V = pB - (pR / 4) - (pG * 3 / 4) + 128; return *ret; #endif #ifdef VIDEO_MODE_RGB @@ -473,6 +481,7 @@ static inline void video_putstring (int xx, int yy, unsigned char *s) /* ** VIDEO CONTROLLER LOW-LEVEL FUNCTIONS */ /************************************************************************/ +#if !defined(CONFIG_RRVISION) static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries) { int i; @@ -485,6 +494,7 @@ static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries) dest[0].lcyc++; /* Add a cycle to the first entry */ dest[entries - 1].lst = 1; /* Set end of ram entries */ } +#endif static void inline video_mode_addentry (VRAM * vr, int Hx, int Vx, int Fx, int Bx, @@ -501,7 +511,7 @@ static void inline video_mode_addentry (VRAM * vr, vr->lst = LST; } -#define ADDENTRY(a,b,c,d,e,f,g,h,i) video_mode_addentry(&vr[entry++],a,b,c,d,e,f,g,h,i) +#define ADDENTRY(a,b,c,d,e,f,g,h,i) video_mode_addentry(&vr[entry++],a,b,c,d,e,f,g,h,i) static int video_mode_generate (void) { @@ -539,9 +549,12 @@ static int video_mode_generate (void) Y1 = video_panning_value_y & 0xfffe; Y2 = DY - Y1; + debug("X1=%d, X2=%d, Y1=%d, Y2=%d, DX=%d, DY=%d VIDEO_COLS=%d \n", + X1, X2, Y1, Y2, DX, DY, VIDEO_COLS); + #ifdef VIDEO_MODE_NTSC /* - * Hx Vx Fx Bx VDS INT LCYC LP LST + * Hx Vx Fx Bx VDS INT LCYC LP LST * * Retrace blanking */ @@ -641,6 +654,73 @@ static int video_mode_generate (void) #endif #ifdef VIDEO_MODE_PAL + +#if defined(CONFIG_RRVISION) + +#define HPW 160 /* horizontal pulse width (was 139) */ +#define VPW 2 /* vertical pulse width */ +#define HBP 104 /* horizontal back porch (was 112) */ +#define VBP 19 /* vertical back porch (was 19) */ +#define VID_R 240 /* number of rows */ + + debug ("[VIDEO CTRL] Starting to add controller entries..."); +/* + * Even field + */ + ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0); + ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0); + ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0); + + ADDENTRY (0, 0, 0, 3, 1, 0, VPW, 1, 0); + ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); + + ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0); + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); +/* + * Active area + */ + ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0); + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0); + ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1); + + ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0); + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0); +/* + * Odd field + */ + ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0); + ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0); + ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0); + + ADDENTRY (0, 0, 0, 3, 1, 0, VPW+1, 1, 0); + ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); + + ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0); + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); +/* + * Active area + */ + ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0); + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0); + ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1); + + ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0); + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0); + + debug ("done\n"); + +#else /* !CONFIG_RRVISION */ + /* * Hx Vx Fx Bx VDS INT LCYC LP LST * @@ -692,7 +772,9 @@ static int video_mode_generate (void) * one more cycle loop and a last identifier) */ video_mode_dupefield (vr, &vr[entry], entry); -#endif +#endif /* CONFIG_RRVISION */ + +#endif /* VIDEO_MODE_PAL */ /* See what FIFO are we using */ fifo = GETBIT (immap->im_vid.vid_vsr, VIDEO_VSR_CAS); @@ -829,26 +911,19 @@ static void video_ctrl_init (void *memptr) debug ("[VIDEO CTRL] Turning on video port led...\n"); SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 0); #endif - #ifdef CONFIG_RRVISION - /* enable clock: set PD3 to VCLK, PC5 to HIGH */ - { - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - debug ("PDPAR=%04X PDDIR=%04X PDDAT=%04X\n", - immr->im_ioport.iop_pdpar, - immr->im_ioport.iop_pddir, - immr->im_ioport.iop_pddat); - - debug ("[RRvision] PC5 -> Output (1): "); - immr->im_ioport.iop_pcpar &= ~(0x0400); - immr->im_ioport.iop_pcdir |= 0x0400 ; - immr->im_ioport.iop_pcdat |= 0x0400 ; - debug ("PCPAR=%04X PCDIR=%04X PCDAT=%04X\n", - immr->im_ioport.iop_pcpar, - immr->im_ioport.iop_pcdir, - immr->im_ioport.iop_pcdat); - } + debug ("PC5->Output(1): enable PAL clock"); + immap->im_ioport.iop_pcpar &= ~(0x0400); + immap->im_ioport.iop_pcdir |= 0x0400 ; + immap->im_ioport.iop_pcdat |= 0x0400 ; + debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n", + immap->im_ioport.iop_pdpar, + immap->im_ioport.iop_pddir, + immap->im_ioport.iop_pddat); + debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n", + immap->im_ioport.iop_pcpar, + immap->im_ioport.iop_pcdir, + immap->im_ioport.iop_pcdat); #endif /* CONFIG_RRVISION */ /* Blanking the screen. */ -- cgit v1.2.1