From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/mpc8260/commproc.c | 18 ++++---- cpu/mpc8260/cpu.c | 20 ++++---- cpu/mpc8260/cpu_init.c | 106 +++++++++++++++++++++--------------------- cpu/mpc8260/ether_fcc.c | 24 +++++----- cpu/mpc8260/ether_scc.c | 16 +++---- cpu/mpc8260/i2c.c | 36 +++++++-------- cpu/mpc8260/interrupts.c | 12 ++--- cpu/mpc8260/kgdb.S | 8 ++-- cpu/mpc8260/pci.c | 100 +++++++++++++++++++-------------------- cpu/mpc8260/serial_scc.c | 14 +++--- cpu/mpc8260/serial_smc.c | 14 +++--- cpu/mpc8260/speed.c | 4 +- cpu/mpc8260/spi.c | 20 ++++---- cpu/mpc8260/start.S | 118 +++++++++++++++++++++++------------------------ cpu/mpc8260/traps.c | 4 +- 15 files changed, 257 insertions(+), 257 deletions(-) (limited to 'cpu/mpc8260') diff --git a/cpu/mpc8260/commproc.c b/cpu/mpc8260/commproc.c index 8777e77369..94f6bc224f 100644 --- a/cpu/mpc8260/commproc.c +++ b/cpu/mpc8260/commproc.c @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; void m8260_cpm_reset(void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile ulong count; /* Reclaim the DP memory for our use. @@ -54,7 +54,7 @@ m8260_cpm_reset(void) uint m8260_cpm_dpalloc(uint size, uint align) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; uint retloc; uint align_mask, off; uint savebase; @@ -110,7 +110,7 @@ m8260_cpm_hostalloc(uint size, uint align) void m8260_cpm_setbrg(uint brg, uint rate) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile uint *bp; uint cd = BRG_UART_CLK / rate; @@ -133,7 +133,7 @@ m8260_cpm_setbrg(uint brg, uint rate) void m8260_cpm_fastbrg(uint brg, uint rate, int div16) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile uint *bp; /* This is good enough to get SMCs running..... @@ -158,7 +158,7 @@ m8260_cpm_fastbrg(uint brg, uint rate, int div16) void m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile uint *bp; if (brg < 4) { @@ -181,7 +181,7 @@ m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) void post_word_store (ulong a) { volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); + (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR); *save_addr = a; } @@ -189,7 +189,7 @@ void post_word_store (ulong a) ulong post_word_load (void) { volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); + (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR); return *save_addr; } @@ -201,7 +201,7 @@ ulong post_word_load (void) void bootcount_store (ulong a) { volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_BOOTCOUNT_ADDR); + (volatile ulong *)(CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR); save_addr[0] = a; save_addr[1] = BOOTCOUNT_MAGIC; @@ -210,7 +210,7 @@ void bootcount_store (ulong a) ulong bootcount_load (void) { volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_BOOTCOUNT_ADDR); + (volatile ulong *)(CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR); if (save_addr[1] != BOOTCOUNT_MAGIC) return 0; diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c index efb8ed6f4e..9f834d3e5a 100644 --- a/cpu/mpc8260/cpu.c +++ b/cpu/mpc8260/cpu.c @@ -61,7 +61,7 @@ extern int get_cpu_str_f (char *buf); int checkcpu (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; ulong clock = gd->cpu_clk; uint pvr = get_pvr (); uint immr, rev, m, k; @@ -88,7 +88,7 @@ int checkcpu (void) rev = pvr & 0xff; immr = immap->im_memctl.memc_immr; - if ((immr & IMMR_ISB_MSK) != CFG_IMMR) + if ((immr & IMMR_ISB_MSK) != CONFIG_SYS_IMMR) return -1; /* whoops! someone moved the IMMR */ #if defined(CONFIG_GET_CPU_STR_F) @@ -178,7 +178,7 @@ int checkcpu (void) void upmconfig (uint upm, uint * table, uint size) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */ uint i; @@ -241,7 +241,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { ulong msr, addr; - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */ @@ -255,15 +255,15 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * Trying to execute the next instruction at a non-existing address * should cause a machine check, resulting in reset */ -#ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; +#ifdef CONFIG_SYS_RESET_ADDRESS + addr = CONFIG_SYS_RESET_ADDRESS; #else /* - * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE + * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address - * known to be invalid on your system and assign it to CFG_RESET_ADDRESS. + * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. */ - addr = CFG_MONITOR_BASE - sizeof (ulong); + addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); #endif ((void (*)(void)) addr) (); return 1; @@ -293,7 +293,7 @@ void watchdog_reset (void) { int re_enable = disable_interrupts (); - reset_8260_watchdog ((immap_t *) CFG_IMMR); + reset_8260_watchdog ((immap_t *) CONFIG_SYS_IMMR); if (re_enable) enable_interrupts (); } diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c index 36fc1eba5f..1d52773445 100644 --- a/cpu/mpc8260/cpu_init.c +++ b/cpu/mpc8260/cpu_init.c @@ -114,7 +114,7 @@ void cpu_init_f (volatile immap_t * immr) extern void m8260_cpm_reset (void); /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); @@ -124,45 +124,45 @@ void cpu_init_f (volatile immap_t * immr) immr->im_clkrst.car_rsr = RSR_ALLBITS; /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */ - immr->im_clkrst.car_rmr = CFG_RMR; + immr->im_clkrst.car_rmr = CONFIG_SYS_RMR; /* BCR - Bus Configuration Register (4-25) */ -#if defined(CFG_BCR_60x) && (CFG_BCR_SINGLE) +#if defined(CONFIG_SYS_BCR_60x) && (CONFIG_SYS_BCR_SINGLE) if (immr->im_siu_conf.sc_bcr & BCR_EBM) { - immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_60x, 0x80000010); + immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_60x, 0x80000010); } else { - immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_SINGLE, 0x80000010); + immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_SINGLE, 0x80000010); } #else - immr->im_siu_conf.sc_bcr = CFG_BCR; + immr->im_siu_conf.sc_bcr = CONFIG_SYS_BCR; #endif /* SIUMCR - contains debug pin configuration (4-31) */ -#if defined(CFG_SIUMCR_LOW) && (CFG_SIUMCR_HIGH) +#if defined(CONFIG_SYS_SIUMCR_LOW) && (CONFIG_SYS_SIUMCR_HIGH) cpu_clk = board_get_cpu_clk_f (); if (cpu_clk >= 100000000) { - immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_HIGH, 0x9f3cc000); + immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_HIGH, 0x9f3cc000); } else { - immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_LOW, 0x9f3cc000); + immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_LOW, 0x9f3cc000); } #else - immr->im_siu_conf.sc_siumcr = CFG_SIUMCR; + immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR; #endif config_8260_ioports (immr); /* initialize time counter status and control register (4-40) */ - immr->im_sit.sit_tmcntsc = CFG_TMCNTSC; + immr->im_sit.sit_tmcntsc = CONFIG_SYS_TMCNTSC; /* initialize the PIT (4-42) */ - immr->im_sit.sit_piscr = CFG_PISCR; + immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; #if !defined(CONFIG_COGENT) /* done in start.S for the cogent */ /* System clock control register (9-8) */ sccr = immr->im_clkrst.car_sccr & (SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK); immr->im_clkrst.car_sccr = sccr | - (CFG_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) ); + (CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) ); #endif /* !CONFIG_COGENT */ /* @@ -174,71 +174,71 @@ void cpu_init_f (volatile immap_t * immr) * has been determined */ -#if defined(CFG_OR0_REMAP) - memctl->memc_or0 = CFG_OR0_REMAP; +#if defined(CONFIG_SYS_OR0_REMAP) + memctl->memc_or0 = CONFIG_SYS_OR0_REMAP; #endif -#if defined(CFG_OR1_REMAP) - memctl->memc_or1 = CFG_OR1_REMAP; +#if defined(CONFIG_SYS_OR1_REMAP) + memctl->memc_or1 = CONFIG_SYS_OR1_REMAP; #endif /* now restrict to preliminary range */ /* the PS came from the HRCW, donīt change it */ - memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CFG_BR0_PRELIM, BRx_PS_MSK); - memctl->memc_or0 = CFG_OR0_PRELIM; + memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CONFIG_SYS_BR0_PRELIM, BRx_PS_MSK); + memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; -#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; +#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; #endif -#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; +#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; #endif -#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; +#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; #endif -#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) - memctl->memc_or4 = CFG_OR4_PRELIM; - memctl->memc_br4 = CFG_BR4_PRELIM; +#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) + memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; + memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; #endif -#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) - memctl->memc_or5 = CFG_OR5_PRELIM; - memctl->memc_br5 = CFG_BR5_PRELIM; +#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) + memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; + memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; #endif -#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) - memctl->memc_or6 = CFG_OR6_PRELIM; - memctl->memc_br6 = CFG_BR6_PRELIM; +#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) + memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM; + memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM; #endif -#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) - memctl->memc_or7 = CFG_OR7_PRELIM; - memctl->memc_br7 = CFG_BR7_PRELIM; +#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) + memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM; + memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; #endif -#if defined(CFG_BR8_PRELIM) && defined(CFG_OR8_PRELIM) - memctl->memc_or8 = CFG_OR8_PRELIM; - memctl->memc_br8 = CFG_BR8_PRELIM; +#if defined(CONFIG_SYS_BR8_PRELIM) && defined(CONFIG_SYS_OR8_PRELIM) + memctl->memc_or8 = CONFIG_SYS_OR8_PRELIM; + memctl->memc_br8 = CONFIG_SYS_BR8_PRELIM; #endif -#if defined(CFG_BR9_PRELIM) && defined(CFG_OR9_PRELIM) - memctl->memc_or9 = CFG_OR9_PRELIM; - memctl->memc_br9 = CFG_BR9_PRELIM; +#if defined(CONFIG_SYS_BR9_PRELIM) && defined(CONFIG_SYS_OR9_PRELIM) + memctl->memc_or9 = CONFIG_SYS_OR9_PRELIM; + memctl->memc_br9 = CONFIG_SYS_BR9_PRELIM; #endif -#if defined(CFG_BR10_PRELIM) && defined(CFG_OR10_PRELIM) - memctl->memc_or10 = CFG_OR10_PRELIM; - memctl->memc_br10 = CFG_BR10_PRELIM; +#if defined(CONFIG_SYS_BR10_PRELIM) && defined(CONFIG_SYS_OR10_PRELIM) + memctl->memc_or10 = CONFIG_SYS_OR10_PRELIM; + memctl->memc_br10 = CONFIG_SYS_BR10_PRELIM; #endif -#if defined(CFG_BR11_PRELIM) && defined(CFG_OR11_PRELIM) - memctl->memc_or11 = CFG_OR11_PRELIM; - memctl->memc_br11 = CFG_BR11_PRELIM; +#if defined(CONFIG_SYS_BR11_PRELIM) && defined(CONFIG_SYS_OR11_PRELIM) + memctl->memc_or11 = CONFIG_SYS_OR11_PRELIM; + memctl->memc_br11 = CONFIG_SYS_BR11_PRELIM; #endif m8260_cpm_reset (); @@ -251,7 +251,7 @@ int cpu_init_r (void) { volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base; - immr->im_cpm.cp_rccr = CFG_RCCR; + immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR; return (0); } diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c index 37bf4456ed..3ab57eb5b4 100644 --- a/cpu/mpc8260/ether_fcc.c +++ b/cpu/mpc8260/ether_fcc.c @@ -73,8 +73,8 @@ static struct ether_fcc_info_s PROFF_FCC1, CPM_CR_FCC1_SBLOCK, CPM_CR_FCC1_PAGE, - CFG_CMXFCR_MASK1, - CFG_CMXFCR_VALUE1 + CONFIG_SYS_CMXFCR_MASK1, + CONFIG_SYS_CMXFCR_VALUE1 }, #endif @@ -84,8 +84,8 @@ static struct ether_fcc_info_s PROFF_FCC2, CPM_CR_FCC2_SBLOCK, CPM_CR_FCC2_PAGE, - CFG_CMXFCR_MASK2, - CFG_CMXFCR_VALUE2 + CONFIG_SYS_CMXFCR_MASK2, + CONFIG_SYS_CMXFCR_VALUE2 }, #endif @@ -95,8 +95,8 @@ static struct ether_fcc_info_s PROFF_FCC3, CPM_CR_FCC3_SBLOCK, CPM_CR_FCC3_PAGE, - CFG_CMXFCR_MASK3, - CFG_CMXFCR_VALUE3 + CONFIG_SYS_CMXFCR_MASK3, + CONFIG_SYS_CMXFCR_VALUE3 }, #endif }; @@ -225,7 +225,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) { struct ether_fcc_info_s * info = dev->priv; int i; - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8260_t *cp = &(immr->im_cpm); fcc_enet_t *pram_ptr; unsigned long mem_addr; @@ -246,7 +246,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */ - immr->im_fcc[info->ether_index].fcc_fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + immr->im_fcc[info->ether_index].fcc_fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; /* 28.9 - (6): FDSR: Ethernet Syn */ immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555; @@ -296,10 +296,10 @@ static int fec_init(struct eth_device* dev, bd_t *bis) */ pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | - CFG_CPMFCR_RAMTYPE) << 24; + CONFIG_SYS_CPMFCR_RAMTYPE) << 24; pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | - CFG_CPMFCR_RAMTYPE) << 24; + CONFIG_SYS_CPMFCR_RAMTYPE) << 24; pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); /* protocol-specific area */ @@ -366,7 +366,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) static void fec_halt(struct eth_device* dev) { struct ether_fcc_info_s * info = dev->priv; - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; /* write GFMR: disable tx/rx */ immr->im_fcc[info->ether_index].fcc_gfmr &= @@ -646,7 +646,7 @@ swap16 (unsigned short x) void eth_loopback_test (void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8260_t *cp = &(immr->im_cpm); int c, nclosed; ulong runtime, nmsec; diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c index 633d053914..c65f0e068f 100644 --- a/cpu/mpc8260/ether_scc.c +++ b/cpu/mpc8260/ether_scc.c @@ -77,8 +77,8 @@ #define TX_BUF_CNT 2 -#if !defined(CFG_SCC_TOUT_LOOP) - #define CFG_SCC_TOUT_LOOP 1000000 +#if !defined(CONFIG_SYS_SCC_TOUT_LOOP) + #define CONFIG_SYS_SCC_TOUT_LOOP 1000000 #endif static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ]; @@ -111,7 +111,7 @@ int eth_send(volatile void *packet, int length) } for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= CFG_SCC_TOUT_LOOP) { + if (i >= CONFIG_SYS_SCC_TOUT_LOOP) { puts ("scc: tx buffer not ready\n"); goto out; } @@ -123,7 +123,7 @@ int eth_send(volatile void *packet, int length) BD_ENET_TX_WRAP); for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= CFG_SCC_TOUT_LOOP) { + if (i >= CONFIG_SYS_SCC_TOUT_LOOP) { puts ("scc: tx error\n"); goto out; } @@ -187,7 +187,7 @@ int eth_rx(void) int eth_init(bd_t *bis) { int i; - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; scc_enet_t *pram_ptr; uint dpaddr; @@ -203,7 +203,7 @@ int eth_init(bd_t *bis) /* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */ immr->im_cpmux.cmx_uar = 0; immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) | - CFG_CMXSCR_VALUE); + CONFIG_SYS_CMXSCR_VALUE); /* 24.21 (6) write RBASE and TBASE to parameter RAM */ @@ -340,7 +340,7 @@ int eth_init(bd_t *bis) void eth_halt(void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); } @@ -348,7 +348,7 @@ void eth_halt(void) #if 0 void restart(void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); } diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c index a96fbf841e..a93419396f 100644 --- a/cpu/mpc8260/i2c.c +++ b/cpu/mpc8260/i2c.c @@ -54,12 +54,12 @@ static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; /*----------------------------------------------------------------------- * Set default values */ -#ifndef CFG_I2C_SPEED -#define CFG_I2C_SPEED 50000 +#ifndef CONFIG_SYS_I2C_SPEED +#define CONFIG_SYS_I2C_SPEED 50000 #endif -#ifndef CFG_I2C_SLAVE -#define CFG_I2C_SLAVE 0xFE +#ifndef CONFIG_SYS_I2C_SLAVE +#define CONFIG_SYS_I2C_SLAVE 0xFE #endif /*----------------------------------------------------------------------- */ @@ -176,7 +176,7 @@ i2c_roundrate(int hz, int speed, int filter, int modval, */ static int i2c_setrate(int hz, int speed) { - immap_t *immap = (immap_t *)CFG_IMMR ; + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; int brgval, modval, /* 0-3 */ @@ -219,7 +219,7 @@ static int i2c_setrate(int hz, int speed) void i2c_init(int speed, int slaveadd) { - volatile immap_t *immap = (immap_t *)CFG_IMMR ; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm; volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; volatile iic_t *iip; @@ -227,7 +227,7 @@ void i2c_init(int speed, int slaveadd) volatile I2C_BD *rxbd, *txbd; uint dpaddr; -#ifdef CFG_I2C_INIT_BOARD +#ifdef CONFIG_SYS_I2C_INIT_BOARD /* call board specific i2c bus reset routine before accessing the */ /* environment, which might be in a chip on that bus. For details */ /* about this problem see doc/I2C_Edge_Conditions. */ @@ -270,7 +270,7 @@ void i2c_init(int speed, int slaveadd) * divide BRGCLK by 1) */ PRINTD(("[I2C] Setting rate...\n")); - i2c_setrate (gd->brg_clk, CFG_I2C_SPEED) ; + i2c_setrate (gd->brg_clk, CONFIG_SYS_I2C_SPEED) ; /* Set I2C controller in master mode */ i2c->i2c_i2com = 0x01; @@ -309,7 +309,7 @@ void i2c_init(int speed, int slaveadd) static void i2c_newio(i2c_state_t *state) { - volatile immap_t *immap = (immap_t *)CFG_IMMR ; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; volatile iic_t *iip; uint dpaddr; @@ -494,7 +494,7 @@ int i2c_receive(i2c_state_t *state, static int i2c_doio(i2c_state_t *state) { - volatile immap_t *immap = (immap_t *)CFG_IMMR ; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; volatile iic_t *iip; volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; volatile I2C_BD *txbd, *rxbd; @@ -667,7 +667,7 @@ i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) xaddr[2] = (addr >> 8) & 0xFF; xaddr[3] = addr & 0xFF; -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address @@ -679,7 +679,7 @@ i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) * be one byte because the extra address bits are hidden in the * chip address. */ - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif i2c_newio(&state); @@ -716,7 +716,7 @@ i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) xaddr[2] = (addr >> 8) & 0xFF; xaddr[3] = addr & 0xFF; -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address @@ -728,7 +728,7 @@ i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) * be one byte because the extra address bits are hidden in the * chip address. */ - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif i2c_newio(&state); @@ -781,7 +781,7 @@ unsigned int i2c_get_bus_num(void) int i2c_set_bus_num(unsigned int bus) { #if defined(CONFIG_I2C_MUX) - if (bus < CFG_MAX_I2C_BUS) { + if (bus < CONFIG_SYS_MAX_I2C_BUS) { i2c_bus_num = bus; } else { int ret; @@ -793,7 +793,7 @@ int i2c_set_bus_num(unsigned int bus) return ret; } #else - if (bus >= CFG_MAX_I2C_BUS) + if (bus >= CONFIG_SYS_MAX_I2C_BUS) return -1; i2c_bus_num = bus; #endif @@ -802,12 +802,12 @@ int i2c_set_bus_num(unsigned int bus) /* TODO: add 100/400k switching */ unsigned int i2c_get_bus_speed(void) { - return CFG_I2C_SPEED; + return CONFIG_SYS_I2C_SPEED; } int i2c_set_bus_speed(unsigned int speed) { - if (speed != CFG_I2C_SPEED) + if (speed != CONFIG_SYS_I2C_SPEED) return -1; return 0; diff --git a/cpu/mpc8260/interrupts.c b/cpu/mpc8260/interrupts.c index bf0d4d0d59..a7700c4b65 100644 --- a/cpu/mpc8260/interrupts.c +++ b/cpu/mpc8260/interrupts.c @@ -82,7 +82,7 @@ static u_char irq_to_siubit[] = { static void m8260_mask_irq (unsigned int irq_nr) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; int bit, word; volatile uint *simr; @@ -96,7 +96,7 @@ static void m8260_mask_irq (unsigned int irq_nr) static void m8260_unmask_irq (unsigned int irq_nr) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; int bit, word; volatile uint *simr; @@ -110,7 +110,7 @@ static void m8260_unmask_irq (unsigned int irq_nr) static void m8260_mask_and_ack (unsigned int irq_nr) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; int bit, word; volatile uint *simr, *sipnr; @@ -126,7 +126,7 @@ static void m8260_mask_and_ack (unsigned int irq_nr) static int m8260_get_irq (struct pt_regs *regs) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; int irq; unsigned long bits; @@ -142,9 +142,9 @@ static int m8260_get_irq (struct pt_regs *regs) int interrupt_init_cpu (unsigned *decrementer_count) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - *decrementer_count = (gd->bus_clk / 4) / CFG_HZ; + *decrementer_count = (gd->bus_clk / 4) / CONFIG_SYS_HZ; /* Initialize the default interrupt mapping priorities */ immr->im_intctl.ic_sicr = 0; diff --git a/cpu/mpc8260/kgdb.S b/cpu/mpc8260/kgdb.S index dae87bb97c..c5936c7345 100644 --- a/cpu/mpc8260/kgdb.S +++ b/cpu/mpc8260/kgdb.S @@ -50,21 +50,21 @@ kgdb_flush_cache_all: .globl kgdb_flush_cache_range kgdb_flush_cache_range: - li r5,CFG_CACHELINE_SIZE-1 + li r5,CONFIG_SYS_CACHELINE_SIZE-1 andc r3,r3,r5 subf r4,r3,r4 add r4,r4,r5 - srwi. r4,r4,CFG_CACHELINE_SHIFT + srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT beqlr mtctr r4 mr r6,r3 1: dcbst 0,r3 - addi r3,r3,CFG_CACHELINE_SIZE + addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b sync /* wait for dcbst's to get to ram */ mtctr r4 2: icbi 0,r6 - addi r6,r6,CFG_CACHELINE_SIZE + addi r6,r6,CONFIG_SYS_CACHELINE_SIZE bdnz 2b SYNC blr diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c index 82303644b2..378d6c573a 100644 --- a/cpu/mpc8260/pci.c +++ b/cpu/mpc8260/pci.c @@ -70,23 +70,23 @@ DECLARE_GLOBAL_DATA_PTR; * This window is set up using the first set of Inbound ATU registers */ -#ifndef CFG_PCI_SLV_MEM_LOCAL -#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ +#ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL +#define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ #else -#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL +#define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL #endif -#ifndef CFG_PCI_SLV_MEM_BUS +#ifndef CONFIG_SYS_PCI_SLV_MEM_BUS #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ #else -#define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS +#define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS #endif -#ifndef CFG_PICMR0_MASK_ATTRIB +#ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB #define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ PICMR_PREFETCH_EN) #else -#define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB +#define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB #endif /* @@ -97,29 +97,29 @@ DECLARE_GLOBAL_DATA_PTR; */ /* PCIBR0 */ -#ifndef CFG_PCI_MSTR0_LOCAL +#ifndef CONFIG_SYS_PCI_MSTR0_LOCAL #define PCI_MSTR0_LOCAL 0x80000000 /* Local base */ #else -#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL +#define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL #endif -#ifndef CFG_PCIMSK0_MASK +#ifndef CONFIG_SYS_PCIMSK0_MASK #define PCIMSK0_MASK PCIMSK_1GB /* Size of window */ #else -#define PCIMSK0_MASK CFG_PCIMSK0_MASK +#define PCIMSK0_MASK CONFIG_SYS_PCIMSK0_MASK #endif /* PCIBR1 */ -#ifndef CFG_PCI_MSTR1_LOCAL +#ifndef CONFIG_SYS_PCI_MSTR1_LOCAL #define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ #else -#define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL +#define PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR1_LOCAL #endif -#ifndef CFG_PCIMSK1_MASK +#ifndef CONFIG_SYS_PCIMSK1_MASK #define PCIMSK1_MASK PCIMSK_64MB /* Size of window */ #else -#define PCIMSK1_MASK CFG_PCIMSK1_MASK +#define PCIMSK1_MASK CONFIG_SYS_PCIMSK1_MASK #endif /* @@ -128,34 +128,34 @@ DECLARE_GLOBAL_DATA_PTR; * in the bridge. */ -#ifndef CFG_PCI_MSTR_MEM_LOCAL +#ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ #else -#define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL +#define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL #endif -#ifndef CFG_PCI_MSTR_MEM_BUS +#ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ #else -#define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS +#define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS #endif -#ifndef CFG_CPU_PCI_MEM_START +#ifndef CONFIG_SYS_CPU_PCI_MEM_START #define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL #else -#define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START +#define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START #endif -#ifndef CFG_PCI_MSTR_MEM_SIZE +#ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE #define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */ #else -#define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE +#define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE #endif -#ifndef CFG_POCMR0_MASK_ATTRIB +#ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB #define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN) #else -#define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB +#define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB #endif /* @@ -164,34 +164,34 @@ DECLARE_GLOBAL_DATA_PTR; * in the bridge. */ -#ifndef CFG_PCI_MSTR_MEMIO_LOCAL +#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL #define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */ #else -#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL +#define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL #endif -#ifndef CFG_PCI_MSTR_MEMIO_BUS +#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS #define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */ #else -#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS +#define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS #endif -#ifndef CFG_CPU_PCI_MEMIO_START +#ifndef CONFIG_SYS_CPU_PCI_MEMIO_START #define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL #else -#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START +#define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START #endif -#ifndef CFG_PCI_MSTR_MEMIO_SIZE +#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE #define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */ #else -#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE +#define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE #endif -#ifndef CFG_POCMR1_MASK_ATTRIB +#ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB #define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) #else -#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB +#define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB #endif /* @@ -200,34 +200,34 @@ DECLARE_GLOBAL_DATA_PTR; * in the bridge. */ -#ifndef CFG_PCI_MSTR_IO_LOCAL +#ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL #define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */ #else -#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL +#define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL #endif -#ifndef CFG_PCI_MSTR_IO_BUS +#ifndef CONFIG_SYS_PCI_MSTR_IO_BUS #define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */ #else -#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS +#define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS #endif -#ifndef CFG_CPU_PCI_IO_START +#ifndef CONFIG_SYS_CPU_PCI_IO_START #define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL #else -#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START +#define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START #endif -#ifndef CFG_PCI_MSTR_IO_SIZE +#ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE #define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */ #else -#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE +#define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE #endif -#ifndef CFG_POCMR2_MASK_ATTRIB +#ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB #define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO) #else -#define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB +#define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB #endif /* PCI bus configuration registers. @@ -245,11 +245,11 @@ void pci_mpc8250_init (struct pci_controller *hose) { u16 tempShort; - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; pci_dev_t host_devno = PCI_BDF (0, 0, 0); - pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG, - CFG_IMMR + PCI_CFG_DATA_REG); + pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG, + CONFIG_SYS_IMMR + PCI_CFG_DATA_REG); /* * Setting required to enable local bus for PCI (SIUMCR [LBPC]). @@ -413,8 +413,8 @@ void pci_mpc8250_init (struct pci_controller *hose) gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); #else pci_set_region (hose->regions + 0, - CFG_SDRAM_BASE, - CFG_SDRAM_BASE, + CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_BASE, 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY); #endif diff --git a/cpu/mpc8260/serial_scc.c b/cpu/mpc8260/serial_scc.c index 3a6eaf0a67..4ab6a28640 100644 --- a/cpu/mpc8260/serial_scc.c +++ b/cpu/mpc8260/serial_scc.c @@ -84,7 +84,7 @@ DECLARE_GLOBAL_DATA_PTR; int serial_init (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile scc_t *sp; volatile scc_uart_t *up; volatile cbd_t *tbdf, *rbdf; @@ -201,7 +201,7 @@ serial_putc(const char c) if (c == '\n') serial_putc ('\r'); - im = (immap_t *)CFG_IMMR; + im = (immap_t *)CONFIG_SYS_IMMR; up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase]; @@ -233,7 +233,7 @@ serial_getc(void) volatile immap_t *im; unsigned char c; - im = (immap_t *)CFG_IMMR; + im = (immap_t *)CONFIG_SYS_IMMR; up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; @@ -257,7 +257,7 @@ serial_tstc() volatile scc_uart_t *up; volatile immap_t *im; - im = (immap_t *)CFG_IMMR; + im = (immap_t *)CONFIG_SYS_IMMR; up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; @@ -321,7 +321,7 @@ serial_tstc() void kgdb_serial_init (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile scc_t *sp; volatile scc_uart_t *up; volatile cbd_t *tbdf, *rbdf; @@ -440,7 +440,7 @@ putDebugChar(const char c) if (c == '\n') putDebugChar ('\r'); - im = (immap_t *)CFG_IMMR; + im = (immap_t *)CONFIG_SYS_IMMR; up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase]; @@ -472,7 +472,7 @@ getDebugChar(void) volatile immap_t *im; unsigned char c; - im = (immap_t *)CFG_IMMR; + im = (immap_t *)CONFIG_SYS_IMMR; up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; diff --git a/cpu/mpc8260/serial_smc.c b/cpu/mpc8260/serial_smc.c index f3dffeb119..a6efa66895 100644 --- a/cpu/mpc8260/serial_smc.c +++ b/cpu/mpc8260/serial_smc.c @@ -76,7 +76,7 @@ static unsigned char brg_map[] = { int serial_init (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile smc_t *sp; volatile smc_uart_t *up; volatile cbd_t *tbdf, *rbdf; @@ -186,7 +186,7 @@ serial_putc(const char c) volatile cbd_t *tbdf; volatile char *buf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; if (c == '\n') serial_putc ('\r'); @@ -220,7 +220,7 @@ serial_getc(void) volatile cbd_t *rbdf; volatile unsigned char *buf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; unsigned char c; up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); @@ -243,7 +243,7 @@ serial_tstc() { volatile cbd_t *rbdf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); @@ -289,7 +289,7 @@ serial_tstc() void kgdb_serial_init (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile smc_t *sp; volatile smc_uart_t *up; volatile cbd_t *tbdf, *rbdf; @@ -401,7 +401,7 @@ putDebugChar(const char c) volatile cbd_t *tbdf; volatile char *buf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; if (c == '\n') putDebugChar ('\r'); @@ -435,7 +435,7 @@ getDebugChar(void) volatile cbd_t *rbdf; volatile unsigned char *buf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; unsigned char c; up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]); diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c index 8d280fbb7b..0e1c2b0659 100644 --- a/cpu/mpc8260/speed.c +++ b/cpu/mpc8260/speed.c @@ -107,7 +107,7 @@ corecnf_t corecnf_tab[] = { int get_clocks (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; ulong clkin; ulong sccr, dfbrg; ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf; @@ -191,7 +191,7 @@ int get_clocks (void) int prt_8260_clks (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; ulong sccr, dfbrg; ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf, pcidf; corecnf_t *cp; diff --git a/cpu/mpc8260/spi.c b/cpu/mpc8260/spi.c index c1a607ca5d..f5d2ac35a6 100644 --- a/cpu/mpc8260/spi.c +++ b/cpu/mpc8260/spi.c @@ -63,8 +63,8 @@ * The value 0x2000 makes it far enough from the start of the data * area (as well as from the stack pointer). * --------------------------------------------------------------- */ -#ifndef CFG_SPI_INIT_OFFSET -#define CFG_SPI_INIT_OFFSET 0x2000 +#ifndef CONFIG_SYS_SPI_INIT_OFFSET +#define CONFIG_SYS_SPI_INIT_OFFSET 0x2000 #endif #define CPM_SPI_BASE 0x100 @@ -119,11 +119,11 @@ ssize_t spi_xfer (size_t); * Initially we place the RX and TX buffers at a fixed location in DPRAM! * ---------------------------------------------------------------------- */ static uchar *rxbuf = - (uchar *)&((immap_t *)CFG_IMMR)->im_dprambase - [CFG_SPI_INIT_OFFSET]; + (uchar *)&((immap_t *)CONFIG_SYS_IMMR)->im_dprambase + [CONFIG_SYS_SPI_INIT_OFFSET]; static uchar *txbuf = - (uchar *)&((immap_t *)CFG_IMMR)->im_dprambase - [CFG_SPI_INIT_OFFSET+MAX_BUFFER]; + (uchar *)&((immap_t *)CONFIG_SYS_IMMR)->im_dprambase + [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER]; /* ************************************************************************** * @@ -143,7 +143,7 @@ void spi_init_f (void) volatile cpm8260_t *cp; volatile cbd_t *tbdf, *rbdf; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; cp = (cpm8260_t *) &immr->im_cpm; *(ushort *)(&immr->im_dprambase[PROFF_SPI_BASE]) = PROFF_SPI; @@ -200,7 +200,7 @@ void spi_init_f (void) /* Allocate space for one transmit and one receive buffer * descriptor in the DP ram */ -#ifdef CFG_ALLOC_DPRAM +#ifdef CONFIG_SYS_ALLOC_DPRAM dpaddr = m8260_cpm_dpalloc (sizeof(cbd_t)*2, 8); #else dpaddr = CPM_SPI_BASE; @@ -279,7 +279,7 @@ void spi_init_r (void) volatile cpm8260_t *cp; volatile cbd_t *tbdf, *rbdf; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; cp = (cpm8260_t *) &immr->im_cpm; spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; @@ -365,7 +365,7 @@ ssize_t spi_xfer (size_t count) DPRINT (("*** spi_xfer entered ***\n")); - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; cp = (cpm8260_t *) &immr->im_cpm; spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index 7f5dc819cd..da0c5161fb 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -127,14 +127,14 @@ version_string: .text .globl _hrcw_table _hrcw_table: - _HRCW_TABLE_ENTRY(CFG_HRCW_MASTER) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE1) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE2) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE3) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE4) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE5) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE6) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE7) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_MASTER) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE1) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE2) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE3) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE4) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE5) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE6) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE7) /* * After configuration, a system reset exception is executed using the * vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP] @@ -172,8 +172,8 @@ _start_warm: b boot_warm boot_cold: -#if defined(CONFIG_MPC8260ADS) && defined(CFG_DEFAULT_IMMR) - lis r3, CFG_DEFAULT_IMMR@h +#if defined(CONFIG_MPC8260ADS) && defined(CONFIG_SYS_DEFAULT_IMMR) + lis r3, CONFIG_SYS_DEFAULT_IMMR@h nop lwz r4, 0(r3) nop @@ -183,7 +183,7 @@ boot_cold: nop stw r4, 0(r3) nop -#endif /* CONFIG_MPC8260ADS && CFG_DEFAULT_IMMR */ +#endif /* CONFIG_MPC8260ADS && CONFIG_SYS_DEFAULT_IMMR */ boot_warm: mfmsr r5 /* save msr contents */ @@ -195,24 +195,24 @@ boot_warm: bl cogent_init_8260 #endif /* CONFIG_COGENT */ -#if defined(CFG_DEFAULT_IMMR) - lis r3, CFG_IMMR@h - ori r3, r3, CFG_IMMR@l - lis r4, CFG_DEFAULT_IMMR@h +#if defined(CONFIG_SYS_DEFAULT_IMMR) + lis r3, CONFIG_SYS_IMMR@h + ori r3, r3, CONFIG_SYS_IMMR@l + lis r4, CONFIG_SYS_DEFAULT_IMMR@h stw r3, 0x1A8(r4) -#endif /* CFG_DEFAULT_IMMR */ +#endif /* CONFIG_SYS_DEFAULT_IMMR */ /* Initialise the MPC8260 processor core */ /*--------------------------------------------------------------*/ bl init_8260_core -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* When booting from ROM (Flash or EPROM), clear the */ /* Address Mask in OR0 so ROM appears everywhere */ /*--------------------------------------------------------------*/ - lis r3, (CFG_IMMR+IM_REGBASE)@h + lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h lwz r4, IM_OR0@l(r3) li r5, 0x7fff and r4, r4, r5 @@ -221,20 +221,20 @@ boot_warm: /* Calculate absolute address in FLASH and jump there */ /*--------------------------------------------------------------*/ - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l + lis r3, CONFIG_SYS_MONITOR_BASE@h + ori r3, r3, CONFIG_SYS_MONITOR_BASE@l addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET mtlr r3 blr in_flash: -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* initialize some things that are hard to access from C */ /*--------------------------------------------------------------*/ - lis r3, CFG_IMMR@h /* set up stack in internal DPRAM */ - ori r1, r3, CFG_INIT_SP_OFFSET + lis r3, CONFIG_SYS_IMMR@h /* set up stack in internal DPRAM */ + ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ stwu r0, -4(r1) /* stack backtraces terminate cleanly */ @@ -458,18 +458,18 @@ cogent_init_8260: /* Taken from page 14 of CMA282 manual */ /*--------------------------------------------------------------*/ - lis r4, (CFG_IMMR+IM_REGBASE)@h - lis r3, CFG_IMMR@h + lis r4, (CONFIG_SYS_IMMR+IM_REGBASE)@h + lis r3, CONFIG_SYS_IMMR@h stw r3, IM_IMMR@l(r4) lwz r3, IM_IMMR@l(r4) stw r3, 0(r0) - lis r3, CFG_SYPCR@h - ori r3, r3, CFG_SYPCR@l + lis r3, CONFIG_SYS_SYPCR@h + ori r3, r3, CONFIG_SYS_SYPCR@l stw r3, IM_SYPCR@l(r4) lwz r3, IM_SYPCR@l(r4) stw r3, 4(r0) - lis r3, CFG_SCCR@h - ori r3, r3, CFG_SCCR@l + lis r3, CONFIG_SYS_SCCR@h + ori r3, r3, CONFIG_SYS_SCCR@l stw r3, IM_SCCR@l(r4) lwz r3, IM_SCCR@l(r4) stw r3, 8(r0) @@ -521,10 +521,10 @@ init_8260_core: /* Initialise the SYPCR early, and reset the watchdog (if req) */ /*--------------------------------------------------------------*/ - lis r3, (CFG_IMMR+IM_REGBASE)@h + lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h #if !defined(CONFIG_COGENT) - lis r4, CFG_SYPCR@h - ori r4, r4, CFG_SYPCR@l + lis r4, CONFIG_SYS_SYPCR@h + ori r4, r4, CONFIG_SYS_SYPCR@l stw r4, IM_SYPCR@l(r3) #endif /* !CONFIG_COGENT */ #if defined(CONFIG_WATCHDOG) @@ -538,18 +538,18 @@ init_8260_core: /* HID0 also contains cache control */ /*--------------------------------------------------------------*/ - lis r3, CFG_HID0_INIT@h - ori r3, r3, CFG_HID0_INIT@l + lis r3, CONFIG_SYS_HID0_INIT@h + ori r3, r3, CONFIG_SYS_HID0_INIT@l SYNC mtspr HID0, r3 - lis r3, CFG_HID0_FINAL@h - ori r3, r3, CFG_HID0_FINAL@l + lis r3, CONFIG_SYS_HID0_FINAL@h + ori r3, r3, CONFIG_SYS_HID0_FINAL@l SYNC mtspr HID0, r3 - lis r3, CFG_HID2@h - ori r3, r3, CFG_HID2@l + lis r3, CONFIG_SYS_HID2@h + ori r3, r3, CONFIG_SYS_HID2@l mtspr HID2, r3 /* clear all BAT's */ @@ -619,29 +619,29 @@ init_8260_core: .globl init_debug init_debug: - lis r3, (CFG_IMMR+IM_REGBASE)@h + lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h /* Quick and dirty hack to enable the RAM and copy the */ /* vectors so that we can take exceptions. */ /*--------------------------------------------------------------*/ /* write Memory Refresh Prescaler */ - li r4, CFG_MPTPR + li r4, CONFIG_SYS_MPTPR sth r4, IM_MPTPR@l(r3) /* write 60x Refresh Timer */ - li r4, CFG_PSRT + li r4, CONFIG_SYS_PSRT stb r4, IM_PSRT@l(r3) /* init the 60x SDRAM Mode Register */ - lis r4, (CFG_PSDMR|PSDMR_OP_NORM)@h - ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM)@l + lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@h + ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@l stw r4, IM_PSDMR@l(r3) /* write Precharge All Banks command */ - lis r4, (CFG_PSDMR|PSDMR_OP_PREA)@h - ori r4, r4, (CFG_PSDMR|PSDMR_OP_PREA)@l + lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@h + ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@l stw r4, IM_PSDMR@l(r3) stb r0, 0(0) /* write eight CBR Refresh commands */ - lis r4, (CFG_PSDMR|PSDMR_OP_CBRR)@h - ori r4, r4, (CFG_PSDMR|PSDMR_OP_CBRR)@l + lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@h + ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@l stw r4, IM_PSDMR@l(r3) stb r0, 0(0) stb r0, 0(0) @@ -652,13 +652,13 @@ init_debug: stb r0, 0(0) stb r0, 0(0) /* write Mode Register Write command */ - lis r4, (CFG_PSDMR|PSDMR_OP_MRW)@h - ori r4, r4, (CFG_PSDMR|PSDMR_OP_MRW)@l + lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@h + ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@l stw r4, IM_PSDMR@l(r3) stb r0, 0(0) /* write Normal Operation command and enable Refresh */ - lis r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h - ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l + lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h + ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l stw r4, IM_PSDMR@l(r3) stb r0, 0(0) /* RAM should now be operational */ @@ -687,7 +687,7 @@ init_debug: /* an exception is generated (before the instruction at that */ /* location completes). The vector for this exception is 0x1300 */ /*--------------------------------------------------------------*/ - lis r3, CFG_IMMR@h + lis r3, CONFIG_SYS_IMMR@h lwz r3, 0(r3) mtspr IABR, r3 @@ -695,9 +695,9 @@ init_debug: /* resides) to a known value - makes it easier to see where */ /* the stack has been written */ /*--------------------------------------------------------------*/ - lis r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@h - ori r3, r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@l - li r4, ((CFG_INIT_SP_OFFSET - 4) / 4) + lis r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@h + ori r3, r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@l + li r4, ((CONFIG_SYS_INIT_SP_OFFSET - 4) / 4) mtctr r4 lis r4, 0xdeadbeaf@h ori r4, r4, 0xdeadbeaf@l @@ -807,16 +807,16 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address * * Offset: */ diff --git a/cpu/mpc8260/traps.c b/cpu/mpc8260/traps.c index b5d416c974..6624544eac 100644 --- a/cpu/mpc8260/traps.c +++ b/cpu/mpc8260/traps.c @@ -111,7 +111,7 @@ _exception(int signr, struct pt_regs *regs) void dump_pci (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; printf ("PCI: err status %x err mask %x err ctrl %x\n", le32_to_cpu (immap->im_pci.pci_esr), @@ -135,7 +135,7 @@ MachineCheckException(struct pt_regs *regs) * the PCI exception handler. */ #ifdef CONFIG_PCI - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; #ifdef DEBUG dump_pci(); #endif -- cgit v1.2.1