From fe1a1da038c7ba7919ab187ba4c2a797cb0853aa Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Fri, 4 Feb 2011 13:42:45 -0600 Subject: powerpc/85xx: Add networking support to P1023RDS The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang Signed-off-by: Haiying Wang Signed-off-by: Lei Xu Signed-off-by: Ioana Radulescu Signed-off-by: Shaohui Xie Signed-off-by: Kumar Gala --- board/freescale/p1023rds/p1023rds.c | 40 +++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'board') diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c index 8cfd199d65..546819cb59 100644 --- a/board/freescale/p1023rds/p1023rds.c +++ b/board/freescale/p1023rds/p1023rds.c @@ -38,6 +38,11 @@ #include #include #include +#include +#include +#include +#include +#include #include "bcsr.h" @@ -143,6 +148,39 @@ unsigned long get_board_ddr_clk(ulong dummy) int board_eth_init(bd_t *bis) { + u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR; + ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + struct fsl_pq_mdio_info dtsec_mdio_info; + + /* + * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting + * is not correct. + */ + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1); + + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); + + fm_info_set_mdio(FM1_DTSEC1, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + fm_info_set_mdio(FM1_DTSEC2, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + + /* Make SERDES connected to SGMII by cleaing bcsr19[7] */ + if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII) + clrbits_8(&bcsr[19], BCSR19_SGMII_SEL_L); + +#ifdef CONFIG_FMAN_ENET + cpu_eth_init(bis); +#endif + return pci_eth_init(bis); } @@ -158,5 +196,7 @@ void ft_board_setup(void *blob, bd_t *bd) size = getenv_bootm_size(); fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_fman_ethernet(blob); } #endif -- cgit v1.2.1