From f84e6ea275353b8fea772ec7553ff7e4b1f642e0 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 24 Oct 2008 10:32:14 +0900 Subject: sh: ap325rxa: Moved ap325rxa board to board/renesas Signed-off-by: Nobuhiro Iwamatsu --- board/ap325rxa/Makefile | 51 ------- board/ap325rxa/ap325rxa.c | 162 ---------------------- board/ap325rxa/config.mk | 26 ---- board/ap325rxa/cpld-ap325rxa.c | 206 ---------------------------- board/ap325rxa/lowlevel_init.S | 243 --------------------------------- board/ap325rxa/u-boot.lds | 105 -------------- board/renesas/ap325rxa/Makefile | 51 +++++++ board/renesas/ap325rxa/ap325rxa.c | 162 ++++++++++++++++++++++ board/renesas/ap325rxa/config.mk | 26 ++++ board/renesas/ap325rxa/cpld-ap325rxa.c | 206 ++++++++++++++++++++++++++++ board/renesas/ap325rxa/lowlevel_init.S | 243 +++++++++++++++++++++++++++++++++ board/renesas/ap325rxa/u-boot.lds | 105 ++++++++++++++ 12 files changed, 793 insertions(+), 793 deletions(-) delete mode 100644 board/ap325rxa/Makefile delete mode 100644 board/ap325rxa/ap325rxa.c delete mode 100644 board/ap325rxa/config.mk delete mode 100644 board/ap325rxa/cpld-ap325rxa.c delete mode 100644 board/ap325rxa/lowlevel_init.S delete mode 100644 board/ap325rxa/u-boot.lds create mode 100644 board/renesas/ap325rxa/Makefile create mode 100644 board/renesas/ap325rxa/ap325rxa.c create mode 100644 board/renesas/ap325rxa/config.mk create mode 100644 board/renesas/ap325rxa/cpld-ap325rxa.c create mode 100644 board/renesas/ap325rxa/lowlevel_init.S create mode 100644 board/renesas/ap325rxa/u-boot.lds (limited to 'board') diff --git a/board/ap325rxa/Makefile b/board/ap325rxa/Makefile deleted file mode 100644 index 21f3e6e29c..0000000000 --- a/board/ap325rxa/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -######################################################################### -# -# Copyright (C) 2008 Renesas Solutions Corp. -# Copyright (C) 2008 Nobuhiro Iwamatsu -# -# board/ap325rxa/Makefile -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := ap325rxa.o cpld-ap325rxa.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ap325rxa/ap325rxa.c b/board/ap325rxa/ap325rxa.c deleted file mode 100644 index 9f1112a436..0000000000 --- a/board/ap325rxa/ap325rxa.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* PRI control register */ -#define PRPRICR5 0xFF800048 /* LMB */ -#define PRPRICR5_D 0x2a - -/* FPGA control */ -#define FPGA_NAND_CTL 0xB410020C -#define FPGA_NAND_RST 0x0008 -#define FPGA_NAND_INIT 0x0000 -#define FPGA_NAND_RST_WAIT 10000 - -/* I/O port data */ -#define PACR_D 0x0000 -#define PBCR_D 0x0000 -#define PCCR_D 0x1000 -#define PDCR_D 0x0000 -#define PECR_D 0x0410 -#define PFCR_D 0xffff -#define PGCR_D 0x0000 -#define PHCR_D 0x5011 -#define PJCR_D 0x4400 -#define PKCR_D 0x7c00 -#define PLCR_D 0x0000 -#define PMCR_D 0x0000 -#define PNCR_D 0x0000 -#define PQCR_D 0x0000 -#define PRCR_D 0x0000 -#define PSCR_D 0x0000 -#define PTCR_D 0x0010 -#define PUCR_D 0x0fff -#define PVCR_D 0xffff -#define PWCR_D 0x0000 -#define PXCR_D 0x7500 -#define PYCR_D 0x0000 -#define PZCR_D 0x5540 - -/* Pin Function Controler data */ -#define PSELA_D 0x1410 -#define PSELB_D 0x0140 -#define PSELC_D 0x0000 -#define PSELD_D 0x0400 - -/* I/O Buffer Hi-Z data */ -#define HIZCRA_D 0x0000 -#define HIZCRB_D 0x1000 -#define HIZCRC_D 0x0000 -#define HIZCRD_D 0x0000 - -/* Module select reg data */ -#define MSELCRA_D 0x0014 -#define MSELCRB_D 0x0018 - -/* Module Stop reg Data */ -#define MSTPCR2_D 0xFFD9F280 - -/* CPLD loader */ -extern void init_cpld(void); - -int checkboard(void) -{ - puts("BOARD: AP325RXA\n"); - return 0; -} - -int board_init(void) -{ - /* Pin Function Controler Init */ - outw(PSELA_D, PSELA); - outw(PSELB_D, PSELB); - outw(PSELC_D, PSELC); - outw(PSELD_D, PSELD); - - /* I/O Buffer Hi-Z Init */ - outw(HIZCRA_D, HIZCRA); - outw(HIZCRB_D, HIZCRB); - outw(HIZCRC_D, HIZCRC); - outw(HIZCRD_D, HIZCRD); - - /* Module select reg Init */ - outw(MSELCRA_D, MSELCRA); - outw(MSELCRB_D, MSELCRB); - - /* Module Stop reg Init */ - outl(MSTPCR2_D, MSTPCR2); - - /* I/O ports */ - outw(PACR_D, PACR); - outw(PBCR_D, PBCR); - outw(PCCR_D, PCCR); - outw(PDCR_D, PDCR); - outw(PECR_D, PECR); - outw(PFCR_D, PFCR); - outw(PGCR_D, PGCR); - outw(PHCR_D, PHCR); - outw(PJCR_D, PJCR); - outw(PKCR_D, PKCR); - outw(PLCR_D, PLCR); - outw(PMCR_D, PMCR); - outw(PNCR_D, PNCR); - outw(PQCR_D, PQCR); - outw(PRCR_D, PRCR); - outw(PSCR_D, PSCR); - outw(PTCR_D, PTCR); - outw(PUCR_D, PUCR); - outw(PVCR_D, PVCR); - outw(PWCR_D, PWCR); - outw(PXCR_D, PXCR); - outw(PYCR_D, PYCR); - outw(PZCR_D, PZCR); - - /* PRI control register Init */ - outl(PRPRICR5_D, PRPRICR5); - - /* cpld init */ - init_cpld(); - - return 0; -} - -int dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -void led_set_state(unsigned short value) -{ -} - -void ide_set_reset(int idereset) -{ - outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */ - udelay(FPGA_NAND_RST_WAIT); - outw(FPGA_NAND_INIT, FPGA_NAND_CTL); -} diff --git a/board/ap325rxa/config.mk b/board/ap325rxa/config.mk deleted file mode 100644 index b52a5e5cb6..0000000000 --- a/board/ap325rxa/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright (C) 2007 -# Nobuhiro Iwamatsu -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -# -# TEXT_BASE refers to image _after_ relocation. -# -# NOTE: Must match value used in u-boot.lds (in this directory). -# - -TEXT_BASE = 0x8FFC0000 diff --git a/board/ap325rxa/cpld-ap325rxa.c b/board/ap325rxa/cpld-ap325rxa.c deleted file mode 100644 index 16fadcbca7..0000000000 --- a/board/ap325rxa/cpld-ap325rxa.c +++ /dev/null @@ -1,206 +0,0 @@ -/*************************************************************** - * Project: - * CPLD SlaveSerial Configuration via embedded microprocessor. - * - * Copyright info: - * - * This is free software; you can redistribute it and/or modify - * it as you like. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * Description: - * - * This is the main source file that will allow a microprocessor - * to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II, - * and Spartan-II devices via the SlaveSerial Configuration Mode. - * This code is discussed in Xilinx Application Note, XAPP502. - * - * History: - * 3-October-2001 MN/MP - Created - * 20-August-2008 Renesas Solutions - Modified to SH7723 - ****************************************************************/ - -#include - -/* Serial */ -#define SCIF_BASE 0xffe00000 /* SCIF0 */ -#define SCSMR (vu_short *)(SCIF_BASE + 0x00) -#define SCBRR (vu_char *)(SCIF_BASE + 0x04) -#define SCSCR (vu_short *)(SCIF_BASE + 0x08) -#define SC_TDR (vu_char *)(SCIF_BASE + 0x0C) -#define SC_SR (vu_short *)(SCIF_BASE + 0x10) -#define SCFCR (vu_short *)(SCIF_BASE + 0x18) -#define RFCR (vu_long *)0xFE400020 - -#define SCSCR_INIT 0x0038 -#define SCSCR_CLR 0x0000 -#define SCFCR_INIT 0x0006 -#define SCSMR_INIT 0x0080 -#define RFCR_CLR 0xA400 -#define SCI_TD_E 0x0020 -#define SCI_TDRE_CLEAR 0x00df - -#define BPS_SETTING_VALUE 1 /* 12.5MHz */ -#define WAIT_RFCR_COUNTER 500 - -/* CPLD data size */ -#define CPLD_DATA_SIZE 169216 - -/* out */ -#define CPLD_PFC_ADR ((vu_short *)0xA4050112) - -#define CPLD_PROG_ADR ((vu_char *)0xA4050132) -#define CPLD_PROG_DAT 0x80 - -/* in */ -#define CPLD_INIT_ADR ((vu_char *)0xA4050132) -#define CPLD_INIT_DAT 0x40 -#define CPLD_DONE_ADR ((vu_char *)0xA4050132) -#define CPLD_DONE_DAT 0x20 - -#define HIZCRB ((vu_short *)0xA405015A) - -/* data */ -#define CPLD_NOMAL_START 0xA0A80000 -#define CPLD_SAFE_START 0xA0AC0000 -#define MODE_SW (vu_char *)0xA405012A - -static void init_cpld_loader(void) -{ - - *SCSCR = SCSCR_CLR; - *SCFCR = SCFCR_INIT; - *SCSMR = SCSMR_INIT; - - *SCBRR = BPS_SETTING_VALUE; - - *RFCR = RFCR_CLR; /* Refresh counter clear */ - - while (*RFCR < WAIT_RFCR_COUNTER) - ; - - *SCFCR = 0x0; /* RTRG=00, TTRG=00 */ - /* MCE=0,TFRST=0,RFRST=0,LOOP=0 */ - *SCSCR = SCSCR_INIT; -} - -static int check_write_ready(void) -{ - u16 status = *SC_SR; - return status & SCI_TD_E; -} - -static void write_cpld_data(char ch) -{ - while (!check_write_ready()) - ; - - *SC_TDR = ch; - *SC_SR; - *SC_SR = SCI_TDRE_CLEAR; -} - -static int delay(void) -{ - int i; - int c = 0; - for (i = 0; i < 200; i++) { - c = *(volatile int *)0xa0000000; - } - return c; -} - -/*********************************************************************** - * - * Function: slave_serial - * - * Description: Initiates SlaveSerial Configuration. - * Calls ShiftDataOut() to output serial data - * - ***********************************************************************/ -static void slave_serial(void) -{ - int i; - unsigned char *flash; - - *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */ - delay(); - - /* - * Toggle Program Pin by Toggling Program_OE bit - * This is accomplished by writing to the Program Register in the CPLD - * - * NOTE: The Program_OE bit should be driven high to bring the Virtex - * Program Pin low. Likewise, it should be driven low - * to bring the Virtex Program Pin to High-Z - */ - - *CPLD_PROG_ADR &= ~CPLD_PROG_DAT; /* PROGRAM_OE LOW */ - delay(); - - /* - * Bring Program High-Z - * (Drive Program_OE bit low to bring Virtex Program Pin to High-Z - */ - - /* Program_OE bit Low brings the Virtex Program Pin to High Z: */ - *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */ - - while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0) - delay(); - - /* Begin Slave-Serial Configuration */ - flash = (unsigned char *)CPLD_NOMAL_START; - - for (i = 0; i < CPLD_DATA_SIZE; i++) - write_cpld_data(*flash++); -} - -/*********************************************************************** - * - * Function: check_done_bit - * - * Description: This function takes monitors the CPLD Input Register - * by checking the status of the DONE bit in that Register. - * By doing so, it monitors the Xilinx Virtex device's DONE - * Pin to see if configuration bitstream has been properly - * loaded - * - ***********************************************************************/ -static void check_done_bit(void) -{ - while (!(*CPLD_DONE_ADR & CPLD_DONE_DAT)) - ; -} - -/*********************************************************************** - * - * Function: init_cpld - * - * Description: Begins Slave Serial configuration of Xilinx FPGA - * - ***********************************************************************/ -void init_cpld(void) -{ - /* Init serial device */ - init_cpld_loader(); - - if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */ - return; - - *HIZCRB = 0x0000; - *CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */ - - /* write CPLD data from NOR flash to device */ - slave_serial(); - - /* - * Monitor the DONE bit in the CPLD Input Register to see if - * configuration successful - */ - - check_done_bit(); -} diff --git a/board/ap325rxa/lowlevel_init.S b/board/ap325rxa/lowlevel_init.S deleted file mode 100644 index 4f6658879c..0000000000 --- a/board/ap325rxa/lowlevel_init.S +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * - * board/ap325rxa/lowlevel_init.S - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. - * - * (Note: As no stack is available, no subroutines can be called...). - */ - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - mov.l DRVCRA_A, r1 - mov.l DRVCRA_D, r0 - mov.w r0, @r1 - - mov.l DRVCRB_A, r1 - mov.l DRVCRB_D, r0 - mov.w r0, @r1 - - mov.l RWTCSR_A, r1 - mov.l RWTCSR_D1, r0 - mov.w r0, @r1 - - mov.l RWTCNT_A, r1 - mov.l RWTCNT_D, r0 - mov.w r0, @r1 - - mov.l RWTCSR_A, r1 - mov.l RWTCSR_D2, r0 - mov.w r0, @r1 - - mov.l FRQCR_A, r1 - mov.l FRQCR_D, r0 - mov.l r0, @r1 - - mov.l CMNCR_A, r1 - mov.l CMNCR_D, r0 - mov.l r0, @r1 - - mov.l CS0BCR_A ,r1 - mov.l CS0BCR_D ,r0 - mov.l r0, @r1 - - mov.l CS4BCR_A ,r1 - mov.l CS4BCR_D ,r0 - mov.l r0, @r1 - - mov.l CS5ABCR_A ,r1 - mov.l CS5ABCR_D ,r0 - mov.l r0, @r1 - - mov.l CS5BBCR_A ,r1 - mov.l CS5BBCR_D ,r0 - mov.l r0, @r1 - - mov.l CS6ABCR_A ,r1 - mov.l CS6ABCR_D ,r0 - mov.l r0, @r1 - - mov.l CS6BBCR_A ,r1 - mov.l CS6BBCR_D ,r0 - mov.l r0, @r1 - - mov.l CS0WCR_A ,r1 - mov.l CS0WCR_D ,r0 - mov.l r0, @r1 - - mov.l CS4WCR_A ,r1 - mov.l CS4WCR_D ,r0 - mov.l r0, @r1 - - mov.l CS5AWCR_A ,r1 - mov.l CS5AWCR_D ,r0 - mov.l r0, @r1 - - mov.l CS5BWCR_A ,r1 - mov.l CS5BWCR_D ,r0 - mov.l r0, @r1 - - mov.l CS6AWCR_A ,r1 - mov.l CS6AWCR_D ,r0 - mov.l r0, @r1 - - mov.l CS6BWCR_A ,r1 - mov.l CS6BWCR_D ,r0 - mov.l r0, @r1 - - mov.l SBSC_SDCR_A, r1 - mov.l SBSC_SDCR_D1, r0 - mov.l r0, @r1 - - mov.l SBSC_SDWCR_A, r1 - mov.l SBSC_SDWCR_D, r0 - mov.l r0, @r1 - - mov.l SBSC_SDPCR_A, r1 - mov.l SBSC_SDPCR_D, r0 - mov.l r0, @r1 - - mov.l SBSC_RTCSR_A, r1 - mov.l SBSC_RTCSR_D, r0 - mov.l r0, @r1 - - mov.l SBSC_RTCNT_A, r1 - mov.l SBSC_RTCNT_D, r0 - mov.l r0, @r1 - - mov.l SBSC_RTCOR_A, r1 - mov.l SBSC_RTCOR_D, r0 - mov.l r0, @r1 - - mov.l SBSC_SDMR3_A1, r1 - mov.l SBSC_SDMR3_D, r0 - mov.b r0, @r1 - - mov.l SBSC_SDMR3_A2, r1 - mov.l SBSC_SDMR3_D, r0 - mov.b r0, @r1 - - mov.l SLEEP_CNT, r1 -2: tst r1, r1 - nop - bf/s 2b - dt r1 - - mov.l SBSC_SDMR3_A3, r1 - mov.l SBSC_SDMR3_D, r0 - mov.b r0, @r1 - - mov.l SBSC_SDCR_A, r1 - mov.l SBSC_SDCR_D2, r0 - mov.l r0, @r1 - - mov.l CCR_A, r1 - mov.l CCR_D, r0 - mov.l r0, @r1 - - ! BL bit off (init = ON) (?!?) - - stc sr, r0 ! BL bit off(init=ON) - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - mov #0, r0 - - .align 2 - -DRVCRA_A: .long DRVCRA -DRVCRB_A: .long DRVCRB -DRVCRA_D: .long 0x4555 -DRVCRB_D: .long 0x0005 - -RWTCSR_A: .long RWTCSR -RWTCNT_A: .long RWTCNT -FRQCR_A: .long FRQCR -RWTCSR_D1: .long 0xa507 -RWTCSR_D2: .long 0xa504 -RWTCNT_D: .long 0x5a00 -FRQCR_D: .long 0x0b04474a - -SBSC_SDCR_A: .long SBSC_SDCR -SBSC_SDWCR_A: .long SBSC_SDWCR -SBSC_SDPCR_A: .long SBSC_SDPCR -SBSC_RTCSR_A: .long SBSC_RTCSR -SBSC_RTCNT_A: .long SBSC_RTCNT -SBSC_RTCOR_A: .long SBSC_RTCOR -SBSC_SDMR3_A1: .long 0xfe510000 -SBSC_SDMR3_A2: .long 0xfe500242 -SBSC_SDMR3_A3: .long 0xfe5c0042 - -SBSC_SDCR_D1: .long 0x92810112 -SBSC_SDCR_D2: .long 0x92810912 -SBSC_SDWCR_D: .long 0x05162482 -SBSC_SDPCR_D: .long 0x00300087 -SBSC_RTCSR_D: .long 0xa55a0212 -SBSC_RTCNT_D: .long 0xa55a0000 -SBSC_RTCOR_D: .long 0xa55a0040 -SBSC_SDMR3_D: .long 0x00 - -CMNCR_A: .long CMNCR -CS0BCR_A: .long CS0BCR -CS4BCR_A: .long CS4BCR -CS5ABCR_A: .long CS5ABCR -CS5BBCR_A: .long CS5BBCR -CS6ABCR_A: .long CS6ABCR -CS6BBCR_A: .long CS6BBCR -CS0WCR_A: .long CS0WCR -CS4WCR_A: .long CS4WCR -CS5AWCR_A: .long CS5AWCR -CS5BWCR_A: .long CS5BWCR -CS6AWCR_A: .long CS6AWCR -CS6BWCR_A: .long CS6BWCR - -CMNCR_D: .long 0x00000013 -CS0BCR_D: .long 0x24920400 -CS4BCR_D: .long 0x24920400 -CS5ABCR_D: .long 0x24920400 -CS5BBCR_D: .long 0x7fff0600 -CS6ABCR_D: .long 0x24920400 -CS6BBCR_D: .long 0x24920600 -CS0WCR_D: .long 0x00000480 -CS4WCR_D: .long 0x00000480 -CS5AWCR_D: .long 0x00000380 -CS5BWCR_D: .long 0x00000600 -CS6AWCR_D: .long 0x00000300 -CS6BWCR_D: .long 0x00000540 - -CCR_A: .long 0xff00001c -CCR_D: .long 0x0000090d - -SLEEP_CNT: .long 0x00000800 -SR_MASK_D: .long 0xEFFFFF0F diff --git a/board/ap325rxa/u-boot.lds b/board/ap325rxa/u-boot.lds deleted file mode 100644 index e9f8dc0def..0000000000 --- a/board/ap325rxa/u-boot.lds +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyrigth (c) 2007 - * Nobuhiro Iwamatsu - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - Base address of internal SDRAM is 0x88000000. - Although size of SDRAM can be either 16 or 32 MBytes, - we assume 16 MBytes (ie ignore upper half if the full - 32 MBytes is present). - - NOTE: This address must match with the definition of - TEXT_BASE in config.mk (in this directory). - - */ - . = 0x88000000 + (128*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - cpu/sh4/start.o (.text) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(.rodata) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); - } - PROVIDE (__u_boot_cmd_end = .); - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (_end = .); -} diff --git a/board/renesas/ap325rxa/Makefile b/board/renesas/ap325rxa/Makefile new file mode 100644 index 0000000000..21f3e6e29c --- /dev/null +++ b/board/renesas/ap325rxa/Makefile @@ -0,0 +1,51 @@ +######################################################################### +# +# Copyright (C) 2008 Renesas Solutions Corp. +# Copyright (C) 2008 Nobuhiro Iwamatsu +# +# board/ap325rxa/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := ap325rxa.o cpld-ap325rxa.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/renesas/ap325rxa/ap325rxa.c b/board/renesas/ap325rxa/ap325rxa.c new file mode 100644 index 0000000000..9f1112a436 --- /dev/null +++ b/board/renesas/ap325rxa/ap325rxa.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* PRI control register */ +#define PRPRICR5 0xFF800048 /* LMB */ +#define PRPRICR5_D 0x2a + +/* FPGA control */ +#define FPGA_NAND_CTL 0xB410020C +#define FPGA_NAND_RST 0x0008 +#define FPGA_NAND_INIT 0x0000 +#define FPGA_NAND_RST_WAIT 10000 + +/* I/O port data */ +#define PACR_D 0x0000 +#define PBCR_D 0x0000 +#define PCCR_D 0x1000 +#define PDCR_D 0x0000 +#define PECR_D 0x0410 +#define PFCR_D 0xffff +#define PGCR_D 0x0000 +#define PHCR_D 0x5011 +#define PJCR_D 0x4400 +#define PKCR_D 0x7c00 +#define PLCR_D 0x0000 +#define PMCR_D 0x0000 +#define PNCR_D 0x0000 +#define PQCR_D 0x0000 +#define PRCR_D 0x0000 +#define PSCR_D 0x0000 +#define PTCR_D 0x0010 +#define PUCR_D 0x0fff +#define PVCR_D 0xffff +#define PWCR_D 0x0000 +#define PXCR_D 0x7500 +#define PYCR_D 0x0000 +#define PZCR_D 0x5540 + +/* Pin Function Controler data */ +#define PSELA_D 0x1410 +#define PSELB_D 0x0140 +#define PSELC_D 0x0000 +#define PSELD_D 0x0400 + +/* I/O Buffer Hi-Z data */ +#define HIZCRA_D 0x0000 +#define HIZCRB_D 0x1000 +#define HIZCRC_D 0x0000 +#define HIZCRD_D 0x0000 + +/* Module select reg data */ +#define MSELCRA_D 0x0014 +#define MSELCRB_D 0x0018 + +/* Module Stop reg Data */ +#define MSTPCR2_D 0xFFD9F280 + +/* CPLD loader */ +extern void init_cpld(void); + +int checkboard(void) +{ + puts("BOARD: AP325RXA\n"); + return 0; +} + +int board_init(void) +{ + /* Pin Function Controler Init */ + outw(PSELA_D, PSELA); + outw(PSELB_D, PSELB); + outw(PSELC_D, PSELC); + outw(PSELD_D, PSELD); + + /* I/O Buffer Hi-Z Init */ + outw(HIZCRA_D, HIZCRA); + outw(HIZCRB_D, HIZCRB); + outw(HIZCRC_D, HIZCRC); + outw(HIZCRD_D, HIZCRD); + + /* Module select reg Init */ + outw(MSELCRA_D, MSELCRA); + outw(MSELCRB_D, MSELCRB); + + /* Module Stop reg Init */ + outl(MSTPCR2_D, MSTPCR2); + + /* I/O ports */ + outw(PACR_D, PACR); + outw(PBCR_D, PBCR); + outw(PCCR_D, PCCR); + outw(PDCR_D, PDCR); + outw(PECR_D, PECR); + outw(PFCR_D, PFCR); + outw(PGCR_D, PGCR); + outw(PHCR_D, PHCR); + outw(PJCR_D, PJCR); + outw(PKCR_D, PKCR); + outw(PLCR_D, PLCR); + outw(PMCR_D, PMCR); + outw(PNCR_D, PNCR); + outw(PQCR_D, PQCR); + outw(PRCR_D, PRCR); + outw(PSCR_D, PSCR); + outw(PTCR_D, PTCR); + outw(PUCR_D, PUCR); + outw(PVCR_D, PVCR); + outw(PWCR_D, PWCR); + outw(PXCR_D, PXCR); + outw(PYCR_D, PYCR); + outw(PZCR_D, PZCR); + + /* PRI control register Init */ + outl(PRPRICR5_D, PRPRICR5); + + /* cpld init */ + init_cpld(); + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state(unsigned short value) +{ +} + +void ide_set_reset(int idereset) +{ + outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */ + udelay(FPGA_NAND_RST_WAIT); + outw(FPGA_NAND_INIT, FPGA_NAND_CTL); +} diff --git a/board/renesas/ap325rxa/config.mk b/board/renesas/ap325rxa/config.mk new file mode 100644 index 0000000000..b52a5e5cb6 --- /dev/null +++ b/board/renesas/ap325rxa/config.mk @@ -0,0 +1,26 @@ +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# + +TEXT_BASE = 0x8FFC0000 diff --git a/board/renesas/ap325rxa/cpld-ap325rxa.c b/board/renesas/ap325rxa/cpld-ap325rxa.c new file mode 100644 index 0000000000..16fadcbca7 --- /dev/null +++ b/board/renesas/ap325rxa/cpld-ap325rxa.c @@ -0,0 +1,206 @@ +/*************************************************************** + * Project: + * CPLD SlaveSerial Configuration via embedded microprocessor. + * + * Copyright info: + * + * This is free software; you can redistribute it and/or modify + * it as you like. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Description: + * + * This is the main source file that will allow a microprocessor + * to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II, + * and Spartan-II devices via the SlaveSerial Configuration Mode. + * This code is discussed in Xilinx Application Note, XAPP502. + * + * History: + * 3-October-2001 MN/MP - Created + * 20-August-2008 Renesas Solutions - Modified to SH7723 + ****************************************************************/ + +#include + +/* Serial */ +#define SCIF_BASE 0xffe00000 /* SCIF0 */ +#define SCSMR (vu_short *)(SCIF_BASE + 0x00) +#define SCBRR (vu_char *)(SCIF_BASE + 0x04) +#define SCSCR (vu_short *)(SCIF_BASE + 0x08) +#define SC_TDR (vu_char *)(SCIF_BASE + 0x0C) +#define SC_SR (vu_short *)(SCIF_BASE + 0x10) +#define SCFCR (vu_short *)(SCIF_BASE + 0x18) +#define RFCR (vu_long *)0xFE400020 + +#define SCSCR_INIT 0x0038 +#define SCSCR_CLR 0x0000 +#define SCFCR_INIT 0x0006 +#define SCSMR_INIT 0x0080 +#define RFCR_CLR 0xA400 +#define SCI_TD_E 0x0020 +#define SCI_TDRE_CLEAR 0x00df + +#define BPS_SETTING_VALUE 1 /* 12.5MHz */ +#define WAIT_RFCR_COUNTER 500 + +/* CPLD data size */ +#define CPLD_DATA_SIZE 169216 + +/* out */ +#define CPLD_PFC_ADR ((vu_short *)0xA4050112) + +#define CPLD_PROG_ADR ((vu_char *)0xA4050132) +#define CPLD_PROG_DAT 0x80 + +/* in */ +#define CPLD_INIT_ADR ((vu_char *)0xA4050132) +#define CPLD_INIT_DAT 0x40 +#define CPLD_DONE_ADR ((vu_char *)0xA4050132) +#define CPLD_DONE_DAT 0x20 + +#define HIZCRB ((vu_short *)0xA405015A) + +/* data */ +#define CPLD_NOMAL_START 0xA0A80000 +#define CPLD_SAFE_START 0xA0AC0000 +#define MODE_SW (vu_char *)0xA405012A + +static void init_cpld_loader(void) +{ + + *SCSCR = SCSCR_CLR; + *SCFCR = SCFCR_INIT; + *SCSMR = SCSMR_INIT; + + *SCBRR = BPS_SETTING_VALUE; + + *RFCR = RFCR_CLR; /* Refresh counter clear */ + + while (*RFCR < WAIT_RFCR_COUNTER) + ; + + *SCFCR = 0x0; /* RTRG=00, TTRG=00 */ + /* MCE=0,TFRST=0,RFRST=0,LOOP=0 */ + *SCSCR = SCSCR_INIT; +} + +static int check_write_ready(void) +{ + u16 status = *SC_SR; + return status & SCI_TD_E; +} + +static void write_cpld_data(char ch) +{ + while (!check_write_ready()) + ; + + *SC_TDR = ch; + *SC_SR; + *SC_SR = SCI_TDRE_CLEAR; +} + +static int delay(void) +{ + int i; + int c = 0; + for (i = 0; i < 200; i++) { + c = *(volatile int *)0xa0000000; + } + return c; +} + +/*********************************************************************** + * + * Function: slave_serial + * + * Description: Initiates SlaveSerial Configuration. + * Calls ShiftDataOut() to output serial data + * + ***********************************************************************/ +static void slave_serial(void) +{ + int i; + unsigned char *flash; + + *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */ + delay(); + + /* + * Toggle Program Pin by Toggling Program_OE bit + * This is accomplished by writing to the Program Register in the CPLD + * + * NOTE: The Program_OE bit should be driven high to bring the Virtex + * Program Pin low. Likewise, it should be driven low + * to bring the Virtex Program Pin to High-Z + */ + + *CPLD_PROG_ADR &= ~CPLD_PROG_DAT; /* PROGRAM_OE LOW */ + delay(); + + /* + * Bring Program High-Z + * (Drive Program_OE bit low to bring Virtex Program Pin to High-Z + */ + + /* Program_OE bit Low brings the Virtex Program Pin to High Z: */ + *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */ + + while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0) + delay(); + + /* Begin Slave-Serial Configuration */ + flash = (unsigned char *)CPLD_NOMAL_START; + + for (i = 0; i < CPLD_DATA_SIZE; i++) + write_cpld_data(*flash++); +} + +/*********************************************************************** + * + * Function: check_done_bit + * + * Description: This function takes monitors the CPLD Input Register + * by checking the status of the DONE bit in that Register. + * By doing so, it monitors the Xilinx Virtex device's DONE + * Pin to see if configuration bitstream has been properly + * loaded + * + ***********************************************************************/ +static void check_done_bit(void) +{ + while (!(*CPLD_DONE_ADR & CPLD_DONE_DAT)) + ; +} + +/*********************************************************************** + * + * Function: init_cpld + * + * Description: Begins Slave Serial configuration of Xilinx FPGA + * + ***********************************************************************/ +void init_cpld(void) +{ + /* Init serial device */ + init_cpld_loader(); + + if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */ + return; + + *HIZCRB = 0x0000; + *CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */ + + /* write CPLD data from NOR flash to device */ + slave_serial(); + + /* + * Monitor the DONE bit in the CPLD Input Register to see if + * configuration successful + */ + + check_done_bit(); +} diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S new file mode 100644 index 0000000000..4f6658879c --- /dev/null +++ b/board/renesas/ap325rxa/lowlevel_init.S @@ -0,0 +1,243 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu + * + * board/ap325rxa/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. + * + * (Note: As no stack is available, no subroutines can be called...). + */ + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + mov.l DRVCRA_A, r1 + mov.l DRVCRA_D, r0 + mov.w r0, @r1 + + mov.l DRVCRB_A, r1 + mov.l DRVCRB_D, r0 + mov.w r0, @r1 + + mov.l RWTCSR_A, r1 + mov.l RWTCSR_D1, r0 + mov.w r0, @r1 + + mov.l RWTCNT_A, r1 + mov.l RWTCNT_D, r0 + mov.w r0, @r1 + + mov.l RWTCSR_A, r1 + mov.l RWTCSR_D2, r0 + mov.w r0, @r1 + + mov.l FRQCR_A, r1 + mov.l FRQCR_D, r0 + mov.l r0, @r1 + + mov.l CMNCR_A, r1 + mov.l CMNCR_D, r0 + mov.l r0, @r1 + + mov.l CS0BCR_A ,r1 + mov.l CS0BCR_D ,r0 + mov.l r0, @r1 + + mov.l CS4BCR_A ,r1 + mov.l CS4BCR_D ,r0 + mov.l r0, @r1 + + mov.l CS5ABCR_A ,r1 + mov.l CS5ABCR_D ,r0 + mov.l r0, @r1 + + mov.l CS5BBCR_A ,r1 + mov.l CS5BBCR_D ,r0 + mov.l r0, @r1 + + mov.l CS6ABCR_A ,r1 + mov.l CS6ABCR_D ,r0 + mov.l r0, @r1 + + mov.l CS6BBCR_A ,r1 + mov.l CS6BBCR_D ,r0 + mov.l r0, @r1 + + mov.l CS0WCR_A ,r1 + mov.l CS0WCR_D ,r0 + mov.l r0, @r1 + + mov.l CS4WCR_A ,r1 + mov.l CS4WCR_D ,r0 + mov.l r0, @r1 + + mov.l CS5AWCR_A ,r1 + mov.l CS5AWCR_D ,r0 + mov.l r0, @r1 + + mov.l CS5BWCR_A ,r1 + mov.l CS5BWCR_D ,r0 + mov.l r0, @r1 + + mov.l CS6AWCR_A ,r1 + mov.l CS6AWCR_D ,r0 + mov.l r0, @r1 + + mov.l CS6BWCR_A ,r1 + mov.l CS6BWCR_D ,r0 + mov.l r0, @r1 + + mov.l SBSC_SDCR_A, r1 + mov.l SBSC_SDCR_D1, r0 + mov.l r0, @r1 + + mov.l SBSC_SDWCR_A, r1 + mov.l SBSC_SDWCR_D, r0 + mov.l r0, @r1 + + mov.l SBSC_SDPCR_A, r1 + mov.l SBSC_SDPCR_D, r0 + mov.l r0, @r1 + + mov.l SBSC_RTCSR_A, r1 + mov.l SBSC_RTCSR_D, r0 + mov.l r0, @r1 + + mov.l SBSC_RTCNT_A, r1 + mov.l SBSC_RTCNT_D, r0 + mov.l r0, @r1 + + mov.l SBSC_RTCOR_A, r1 + mov.l SBSC_RTCOR_D, r0 + mov.l r0, @r1 + + mov.l SBSC_SDMR3_A1, r1 + mov.l SBSC_SDMR3_D, r0 + mov.b r0, @r1 + + mov.l SBSC_SDMR3_A2, r1 + mov.l SBSC_SDMR3_D, r0 + mov.b r0, @r1 + + mov.l SLEEP_CNT, r1 +2: tst r1, r1 + nop + bf/s 2b + dt r1 + + mov.l SBSC_SDMR3_A3, r1 + mov.l SBSC_SDMR3_D, r0 + mov.b r0, @r1 + + mov.l SBSC_SDCR_A, r1 + mov.l SBSC_SDCR_D2, r0 + mov.l r0, @r1 + + mov.l CCR_A, r1 + mov.l CCR_D, r0 + mov.l r0, @r1 + + ! BL bit off (init = ON) (?!?) + + stc sr, r0 ! BL bit off(init=ON) + mov.l SR_MASK_D, r1 + and r1, r0 + ldc r0, sr + + rts + mov #0, r0 + + .align 2 + +DRVCRA_A: .long DRVCRA +DRVCRB_A: .long DRVCRB +DRVCRA_D: .long 0x4555 +DRVCRB_D: .long 0x0005 + +RWTCSR_A: .long RWTCSR +RWTCNT_A: .long RWTCNT +FRQCR_A: .long FRQCR +RWTCSR_D1: .long 0xa507 +RWTCSR_D2: .long 0xa504 +RWTCNT_D: .long 0x5a00 +FRQCR_D: .long 0x0b04474a + +SBSC_SDCR_A: .long SBSC_SDCR +SBSC_SDWCR_A: .long SBSC_SDWCR +SBSC_SDPCR_A: .long SBSC_SDPCR +SBSC_RTCSR_A: .long SBSC_RTCSR +SBSC_RTCNT_A: .long SBSC_RTCNT +SBSC_RTCOR_A: .long SBSC_RTCOR +SBSC_SDMR3_A1: .long 0xfe510000 +SBSC_SDMR3_A2: .long 0xfe500242 +SBSC_SDMR3_A3: .long 0xfe5c0042 + +SBSC_SDCR_D1: .long 0x92810112 +SBSC_SDCR_D2: .long 0x92810912 +SBSC_SDWCR_D: .long 0x05162482 +SBSC_SDPCR_D: .long 0x00300087 +SBSC_RTCSR_D: .long 0xa55a0212 +SBSC_RTCNT_D: .long 0xa55a0000 +SBSC_RTCOR_D: .long 0xa55a0040 +SBSC_SDMR3_D: .long 0x00 + +CMNCR_A: .long CMNCR +CS0BCR_A: .long CS0BCR +CS4BCR_A: .long CS4BCR +CS5ABCR_A: .long CS5ABCR +CS5BBCR_A: .long CS5BBCR +CS6ABCR_A: .long CS6ABCR +CS6BBCR_A: .long CS6BBCR +CS0WCR_A: .long CS0WCR +CS4WCR_A: .long CS4WCR +CS5AWCR_A: .long CS5AWCR +CS5BWCR_A: .long CS5BWCR +CS6AWCR_A: .long CS6AWCR +CS6BWCR_A: .long CS6BWCR + +CMNCR_D: .long 0x00000013 +CS0BCR_D: .long 0x24920400 +CS4BCR_D: .long 0x24920400 +CS5ABCR_D: .long 0x24920400 +CS5BBCR_D: .long 0x7fff0600 +CS6ABCR_D: .long 0x24920400 +CS6BBCR_D: .long 0x24920600 +CS0WCR_D: .long 0x00000480 +CS4WCR_D: .long 0x00000480 +CS5AWCR_D: .long 0x00000380 +CS5BWCR_D: .long 0x00000600 +CS6AWCR_D: .long 0x00000300 +CS6BWCR_D: .long 0x00000540 + +CCR_A: .long 0xff00001c +CCR_D: .long 0x0000090d + +SLEEP_CNT: .long 0x00000800 +SR_MASK_D: .long 0xEFFFFF0F diff --git a/board/renesas/ap325rxa/u-boot.lds b/board/renesas/ap325rxa/u-boot.lds new file mode 100644 index 0000000000..e9f8dc0def --- /dev/null +++ b/board/renesas/ap325rxa/u-boot.lds @@ -0,0 +1,105 @@ +/* + * Copyrigth (c) 2007 + * Nobuhiro Iwamatsu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x88000000. + Although size of SDRAM can be either 16 or 32 MBytes, + we assume 16 MBytes (ie ignore upper half if the full + 32 MBytes is present). + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x88000000 + (128*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} -- cgit v1.2.1 From acd3e30d09a73f876222f0d496c4f52ee9d0771d Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 24 Oct 2008 10:34:21 +0900 Subject: sh: r7780mp: Moved r7780mp board to board/renesas Signed-off-by: Nobuhiro Iwamatsu --- board/r7780mp/Makefile | 48 ---- board/r7780mp/config.mk | 27 --- board/r7780mp/lowlevel_init.S | 429 ---------------------------------- board/r7780mp/r7780mp.c | 85 ------- board/r7780mp/r7780mp.h | 54 ----- board/r7780mp/u-boot.lds | 105 --------- board/renesas/r7780mp/Makefile | 48 ++++ board/renesas/r7780mp/config.mk | 27 +++ board/renesas/r7780mp/lowlevel_init.S | 429 ++++++++++++++++++++++++++++++++++ board/renesas/r7780mp/r7780mp.c | 85 +++++++ board/renesas/r7780mp/r7780mp.h | 54 +++++ board/renesas/r7780mp/u-boot.lds | 105 +++++++++ 12 files changed, 748 insertions(+), 748 deletions(-) delete mode 100644 board/r7780mp/Makefile delete mode 100644 board/r7780mp/config.mk delete mode 100644 board/r7780mp/lowlevel_init.S delete mode 100644 board/r7780mp/r7780mp.c delete mode 100644 board/r7780mp/r7780mp.h delete mode 100644 board/r7780mp/u-boot.lds create mode 100644 board/renesas/r7780mp/Makefile create mode 100644 board/renesas/r7780mp/config.mk create mode 100644 board/renesas/r7780mp/lowlevel_init.S create mode 100644 board/renesas/r7780mp/r7780mp.c create mode 100644 board/renesas/r7780mp/r7780mp.h create mode 100644 board/renesas/r7780mp/u-boot.lds (limited to 'board') diff --git a/board/r7780mp/Makefile b/board/r7780mp/Makefile deleted file mode 100644 index c100e7e2ad..0000000000 --- a/board/r7780mp/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# Copyright (C) 2007,2008 Nobuhiro Iwamatsu -# -# board/r7780mp/Makefile -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := r7780mp.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/r7780mp/config.mk b/board/r7780mp/config.mk deleted file mode 100644 index 6a045a15c2..0000000000 --- a/board/r7780mp/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright (C) 2007,2008 Nobuhiro Iwamatsu -# -# board/r77870mp/config.mk -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -# -# TEXT_BASE refers to image _after_ relocation. -# -# NOTE: Must match value used in u-boot.lds (in this directory). -# - -TEXT_BASE = 0x0FFC0000 diff --git a/board/r7780mp/lowlevel_init.S b/board/r7780mp/lowlevel_init.S deleted file mode 100644 index ab0499a3a2..0000000000 --- a/board/r7780mp/lowlevel_init.S +++ /dev/null @@ -1,429 +0,0 @@ -/* - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu - * - * u-boot/board/r7780mp/lowlevel_init.S - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. - * - * (Note: As no stack is available, no subroutines can be called...). - */ - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - mov.l CCR_A, r1 /* Address of Cache Control Register */ - mov.l CCR_D, r0 /* Instruction Cache Invalidate */ - mov.l r0, @r1 - - mov.l FRQCR_A, r1 /* Frequency control register */ - mov.l FRQCR_D, r0 - mov.l r0, @r1 - - /* pin_multi_setting */ - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR1,r0 - mov.l r0,@r1 - - mov.l BBG_PMSR1_A,r1 - mov.l BBG_PMSR1_D,r0 - mov.l r0,@r1 - - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR2,r0 - mov.l r0,@r1 - - mov.l BBG_PMSR2_A,r1 - mov.l BBG_PMSR2_D,r0 - mov.l r0,@r1 - - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR3,r0 - mov.l r0,@r1 - - mov.l BBG_PMSR3_A,r1 - mov.l BBG_PMSR3_D,r0 - mov.l r0,@r1 - - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR4,r0 - mov.l r0,@r1 - - mov.l BBG_PMSR4_A,r1 - mov.l BBG_PMSR4_D,r0 - mov.l r0,@r1 - - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSRG,r0 - mov.l r0,@r1 - - mov.l BBG_PMSRG_A,r1 - mov.l BBG_PMSRG_D,r0 - mov.l r0,@r1 - - /* cpg_setting */ - mov.l FRQCR_A,r1 - mov.l FRQCR_D,r0 - mov.l r0,@r1 - - mov.l DLLCSR_A,r1 - mov.l DLLCSR_D,r0 - mov.l r0,@r1 - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - /* wait 200us */ - mov.l REPEAT0_R3,r3 - mov #0,r2 -repeat0: - add #1,r2 - cmp/hs r3,r2 - bf repeat0 - nop - - /* bsc_setting */ - mov.l MMSELR_A,r1 - mov.l MMSELR_D,r0 - mov.l r0,@r1 - - mov.l BCR_A,r1 - mov.l BCR_D,r0 - mov.l r0,@r1 - - mov.l CS0BCR_A,r1 - mov.l CS0BCR_D,r0 - mov.l r0,@r1 - - mov.l CS1BCR_A,r1 - mov.l CS1BCR_D,r0 - mov.l r0,@r1 - - mov.l CS2BCR_A,r1 - mov.l CS2BCR_D,r0 - mov.l r0,@r1 - - mov.l CS4BCR_A,r1 - mov.l CS4BCR_D,r0 - mov.l r0,@r1 - - mov.l CS5BCR_A,r1 - mov.l CS5BCR_D,r0 - mov.l r0,@r1 - - mov.l CS6BCR_A,r1 - mov.l CS6BCR_D,r0 - mov.l r0,@r1 - - mov.l CS0WCR_A,r1 - mov.l CS0WCR_D,r0 - mov.l r0,@r1 - - mov.l CS1WCR_A,r1 - mov.l CS1WCR_D,r0 - mov.l r0,@r1 - - mov.l CS2WCR_A,r1 - mov.l CS2WCR_D,r0 - mov.l r0,@r1 - - mov.l CS4WCR_A,r1 - mov.l CS4WCR_D,r0 - mov.l r0,@r1 - - mov.l CS5WCR_A,r1 - mov.l CS5WCR_D,r0 - mov.l r0,@r1 - - mov.l CS6WCR_A,r1 - mov.l CS6WCR_D,r0 - mov.l r0,@r1 - - mov.l CS5PCR_A,r1 - mov.l CS5PCR_D,r0 - mov.l r0,@r1 - - mov.l CS6PCR_A,r1 - mov.l CS6PCR_D,r0 - mov.l r0,@r1 - - /* ddr_setting */ - /* wait 200us */ - mov.l REPEAT0_R3,r3 - mov #0,r2 -repeat1: - add #1,r2 - cmp/hs r3,r2 - bf repeat1 - nop - - mov.l MIM_U_A,r0 - mov.l MIM_U_D,r1 - synco - mov.l r1,@r0 - synco - - mov.l MIM_L_A,r0 - mov.l MIM_L_D0,r1 - synco - mov.l r1,@r0 - synco - - mov.l STR_L_A,r0 - mov.l STR_L_D,r1 - synco - mov.l r1,@r0 - synco - - mov.l SDR_L_A,r0 - mov.l SDR_L_D,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - nop - - mov.l SCR_L_A,r0 - mov.l SCR_L_D0,r1 - synco - mov.l r1,@r0 - synco - - mov.l SCR_L_A,r0 - mov.l SCR_L_D1,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - - mov.l EMRS_A,r0 - mov.l EMRS_D,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - - mov.l MRS1_A,r0 - mov.l MRS1_D,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - - mov.l SCR_L_A,r0 - mov.l SCR_L_D2,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - - mov.l SCR_L_A,r0 - mov.l SCR_L_D3,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - - mov.l SCR_L_A,r0 - mov.l SCR_L_D4,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - - mov.l MRS2_A,r0 - mov.l MRS2_D,r1 - synco - mov.l r1,@r0 - synco - - nop - nop - nop - - mov.l SCR_L_A,r0 - mov.l SCR_L_D5,r1 - synco - mov.l r1,@r0 - synco - - /* wait 200us */ - mov.l REPEAT0_R1,r3 - mov #0,r2 -repeat2: - add #1,r2 - cmp/hs r3,r2 - bf repeat2 - - synco - - mov.l MIM_L_A,r0 - mov.l MIM_L_D1,r1 - synco - mov.l r1,@r0 - synco - - rts - nop - .align 4 - -RWTCSR_D_1: .word 0xA507 -RWTCSR_D_2: .word 0xA507 -RWTCNT_D: .word 0x5A00 - .align 2 - -BBG_PMMR_A: .long 0xFF800010 -BBG_PMSR1_A: .long 0xFF800014 -BBG_PMSR2_A: .long 0xFF800018 -BBG_PMSR3_A: .long 0xFF80001C -BBG_PMSR4_A: .long 0xFF800020 -BBG_PMSRG_A: .long 0xFF800024 - -BBG_PMMR_D_PMSR1: .long 0xffffbffd -BBG_PMSR1_D: .long 0x00004002 -BBG_PMMR_D_PMSR2: .long 0xfc21a7ff -BBG_PMSR2_D: .long 0x03de5800 -BBG_PMMR_D_PMSR3: .long 0xfffffff8 -BBG_PMSR3_D: .long 0x00000007 -BBG_PMMR_D_PMSR4: .long 0xdffdfff9 -BBG_PMSR4_D: .long 0x20020006 -BBG_PMMR_D_PMSRG: .long 0xffffffff -BBG_PMSRG_D: .long 0x00000000 - -FRQCR_A: .long FRQCR -DLLCSR_A: .long 0xffc40010 -FRQCR_D: .long 0x40233035 -DLLCSR_D: .long 0x00000000 - -/* for DDR-SDRAM */ -MIM_U_A: .long MIM_1 -MIM_L_A: .long MIM_2 -SCR_U_A: .long SCR_1 -SCR_L_A: .long SCR_2 -STR_U_A: .long STR_1 -STR_L_A: .long STR_2 -SDR_U_A: .long SDR_1 -SDR_L_A: .long SDR_2 - -EMRS_A: .long 0xFEC02000 -MRS1_A: .long 0xFEC00B08 -MRS2_A: .long 0xFEC00308 - -MIM_U_D: .long 0x00004000 -MIM_L_D0: .long 0x03e80009 -MIM_L_D1: .long 0x03e80209 -SCR_L_D0: .long 0x3 -SCR_L_D1: .long 0x2 -SCR_L_D2: .long 0x2 -SCR_L_D3: .long 0x4 -SCR_L_D4: .long 0x4 -SCR_L_D5: .long 0x0 -STR_L_D: .long 0x000f0000 -SDR_L_D: .long 0x00000400 -EMRS_D: .long 0x0 -MRS1_D: .long 0x0 -MRS2_D: .long 0x0 - -/* Cache Controller */ -CCR_A: .long CCR -MMUCR_A: .long MMUCR -RWTCNT_A: .long WTCNT - -CCR_D: .long 0x0000090b -CCR_D_2: .long 0x00000103 -MMUCR_D: .long 0x00000004 -MSTPCR0_D: .long 0x00001001 -MSTPCR2_D: .long 0xffffffff - -/* local Bus State Controller */ -MMSELR_A: .long MMSELR -BCR_A: .long BCR -CS0BCR_A: .long CS0BCR -CS1BCR_A: .long CS1BCR -CS2BCR_A: .long CS2BCR -CS4BCR_A: .long CS4BCR -CS5BCR_A: .long CS5BCR -CS6BCR_A: .long CS6BCR -CS0WCR_A: .long CS0WCR -CS1WCR_A: .long CS1WCR -CS2WCR_A: .long CS2WCR -CS4WCR_A: .long CS4WCR -CS5WCR_A: .long CS5WCR -CS6WCR_A: .long CS6WCR -CS5PCR_A: .long CS5PCR -CS6PCR_A: .long CS6PCR - -MMSELR_D: .long 0xA5A50003 -BCR_D: .long 0x00000000 -CS0BCR_D: .long 0x77777770 -CS1BCR_D: .long 0x77777670 -CS2BCR_D: .long 0x77777770 -CS4BCR_D: .long 0x77777770 -CS5BCR_D: .long 0x77777670 -CS6BCR_D: .long 0x77777770 -CS0WCR_D: .long 0x00020006 -CS1WCR_D: .long 0x00232304 -CS2WCR_D: .long 0x7777770F -CS4WCR_D: .long 0x7777770F -CS5WCR_D: .long 0x00101006 -CS6WCR_D: .long 0x77777703 -CS5PCR_D: .long 0x77000000 -CS6PCR_D: .long 0x77000000 - -REPEAT0_R3: .long 0x00002000 -REPEAT0_R1: .long 0x0000200 diff --git a/board/r7780mp/r7780mp.c b/board/r7780mp/r7780mp.c deleted file mode 100644 index 396e4b6db3..0000000000 --- a/board/r7780mp/r7780mp.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Yusuke Goda - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include "r7780mp.h" - -int checkboard(void) -{ -#if defined(CONFIG_R7780MP) - puts("BOARD: Renesas Solutions R7780MP\n"); -#else - puts("BOARD: Renesas Solutions R7780RP\n"); -#endif - return 0; -} - -int board_init(void) -{ - /* SCIF Enable */ - writew(0x0, PHCR); - - return 0; -} - -int dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -void led_set_state(unsigned short value) -{ - -} - -void ide_set_reset(int idereset) -{ - /* if reset = 1 IDE reset will be asserted */ - if (idereset) { - writew(0x432, FPGA_CFCTL); -#if defined(CONFIG_R7780MP) - writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW); -#else - writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW); -#endif - writew(0x01, FPGA_CFCDINTCLR); - } -} - -static struct pci_controller hose; -void pci_init_board(void) -{ - pci_sh7780_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/r7780mp/r7780mp.h b/board/r7780mp/r7780mp.h deleted file mode 100644 index 476a41354f..0000000000 --- a/board/r7780mp/r7780mp.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (C) 2007 Nobuhiro Iwamatsu - * Copyright (C) 2008 Yusuke Goda - * - * u-boot/board/r7780mp/r7780mp.h - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BOARD_R7780MP_R7780MP_H_ -#define _BOARD_R7780MP_R7780MP_H_ - -/* R7780MP's FPGA register map */ -#define FPGA_BASE 0xa4000000 -#define FPGA_IRLMSK (FPGA_BASE + 0x00) -#define FPGA_IRLMON (FPGA_BASE + 0x02) -#define FPGA_IRLPRI1 (FPGA_BASE + 0x04) -#define FPGA_IRLPRI2 (FPGA_BASE + 0x06) -#define FPGA_IRLPRI3 (FPGA_BASE + 0x08) -#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A) -#define FPGA_RSTCTL (FPGA_BASE + 0x0C) -#define FPGA_PCIBD (FPGA_BASE + 0x0E) -#define FPGA_PCICD (FPGA_BASE + 0x10) -#define FPGA_EXTGIO (FPGA_BASE + 0x16) -#define FPGA_IVDRMON (FPGA_BASE + 0x18) -#define FPGA_IVDRCR (FPGA_BASE + 0x1A) -#define FPGA_OBLED (FPGA_BASE + 0x1C) -#define FPGA_OBSW (FPGA_BASE + 0x1E) -#define FPGA_TPCTL (FPGA_BASE + 0x100) -#define FPGA_TPDCKCTL (FPGA_BASE + 0x102) -#define FPGA_TPCLR (FPGA_BASE + 0x104) -#define FPGA_TPXPOS (FPGA_BASE + 0x106) -#define FPGA_TPYPOS (FPGA_BASE + 0x108) -#define FPGA_DBSW (FPGA_BASE + 0x200) -#define FPGA_VERSION (FPGA_BASE + 0x700) -#define FPGA_CFCTL (FPGA_BASE + 0x300) -#define FPGA_CFPOW (FPGA_BASE + 0x302) -#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304) -#define FPGA_PMR (FPGA_BASE + 0x900) - -#endif /* _BOARD_R7780RP_R7780RP_H_ */ diff --git a/board/r7780mp/u-boot.lds b/board/r7780mp/u-boot.lds deleted file mode 100644 index eaa05d0d58..0000000000 --- a/board/r7780mp/u-boot.lds +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyrigth (c) 2007,2008 - * Nobuhiro Iwamatsu - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - Base address of internal SDRAM is 0x0C000000. - Although size of SDRAM can be either 16 or 32 MBytes, - we assume 16 MBytes (ie ignore upper half if the full - 32 MBytes is present). - - NOTE: This address must match with the definition of - TEXT_BASE in config.mk (in this directory). - - */ - . = 0x08000000 + (128*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - cpu/sh4/start.o (.text) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(.rodata) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); - } - PROVIDE (__u_boot_cmd_end = .); - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (_end = .); -} diff --git a/board/renesas/r7780mp/Makefile b/board/renesas/r7780mp/Makefile new file mode 100644 index 0000000000..c100e7e2ad --- /dev/null +++ b/board/renesas/r7780mp/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) 2007,2008 Nobuhiro Iwamatsu +# +# board/r7780mp/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := r7780mp.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/renesas/r7780mp/config.mk b/board/renesas/r7780mp/config.mk new file mode 100644 index 0000000000..6a045a15c2 --- /dev/null +++ b/board/renesas/r7780mp/config.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2007,2008 Nobuhiro Iwamatsu +# +# board/r77870mp/config.mk +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# + +TEXT_BASE = 0x0FFC0000 diff --git a/board/renesas/r7780mp/lowlevel_init.S b/board/renesas/r7780mp/lowlevel_init.S new file mode 100644 index 0000000000..ab0499a3a2 --- /dev/null +++ b/board/renesas/r7780mp/lowlevel_init.S @@ -0,0 +1,429 @@ +/* + * Copyright (C) 2007,2008 Nobuhiro Iwamatsu + * + * u-boot/board/r7780mp/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. + * + * (Note: As no stack is available, no subroutines can be called...). + */ + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + + mov.l CCR_A, r1 /* Address of Cache Control Register */ + mov.l CCR_D, r0 /* Instruction Cache Invalidate */ + mov.l r0, @r1 + + mov.l FRQCR_A, r1 /* Frequency control register */ + mov.l FRQCR_D, r0 + mov.l r0, @r1 + + /* pin_multi_setting */ + mov.l BBG_PMMR_A,r1 + mov.l BBG_PMMR_D_PMSR1,r0 + mov.l r0,@r1 + + mov.l BBG_PMSR1_A,r1 + mov.l BBG_PMSR1_D,r0 + mov.l r0,@r1 + + mov.l BBG_PMMR_A,r1 + mov.l BBG_PMMR_D_PMSR2,r0 + mov.l r0,@r1 + + mov.l BBG_PMSR2_A,r1 + mov.l BBG_PMSR2_D,r0 + mov.l r0,@r1 + + mov.l BBG_PMMR_A,r1 + mov.l BBG_PMMR_D_PMSR3,r0 + mov.l r0,@r1 + + mov.l BBG_PMSR3_A,r1 + mov.l BBG_PMSR3_D,r0 + mov.l r0,@r1 + + mov.l BBG_PMMR_A,r1 + mov.l BBG_PMMR_D_PMSR4,r0 + mov.l r0,@r1 + + mov.l BBG_PMSR4_A,r1 + mov.l BBG_PMSR4_D,r0 + mov.l r0,@r1 + + mov.l BBG_PMMR_A,r1 + mov.l BBG_PMMR_D_PMSRG,r0 + mov.l r0,@r1 + + mov.l BBG_PMSRG_A,r1 + mov.l BBG_PMSRG_D,r0 + mov.l r0,@r1 + + /* cpg_setting */ + mov.l FRQCR_A,r1 + mov.l FRQCR_D,r0 + mov.l r0,@r1 + + mov.l DLLCSR_A,r1 + mov.l DLLCSR_D,r0 + mov.l r0,@r1 + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + /* wait 200us */ + mov.l REPEAT0_R3,r3 + mov #0,r2 +repeat0: + add #1,r2 + cmp/hs r3,r2 + bf repeat0 + nop + + /* bsc_setting */ + mov.l MMSELR_A,r1 + mov.l MMSELR_D,r0 + mov.l r0,@r1 + + mov.l BCR_A,r1 + mov.l BCR_D,r0 + mov.l r0,@r1 + + mov.l CS0BCR_A,r1 + mov.l CS0BCR_D,r0 + mov.l r0,@r1 + + mov.l CS1BCR_A,r1 + mov.l CS1BCR_D,r0 + mov.l r0,@r1 + + mov.l CS2BCR_A,r1 + mov.l CS2BCR_D,r0 + mov.l r0,@r1 + + mov.l CS4BCR_A,r1 + mov.l CS4BCR_D,r0 + mov.l r0,@r1 + + mov.l CS5BCR_A,r1 + mov.l CS5BCR_D,r0 + mov.l r0,@r1 + + mov.l CS6BCR_A,r1 + mov.l CS6BCR_D,r0 + mov.l r0,@r1 + + mov.l CS0WCR_A,r1 + mov.l CS0WCR_D,r0 + mov.l r0,@r1 + + mov.l CS1WCR_A,r1 + mov.l CS1WCR_D,r0 + mov.l r0,@r1 + + mov.l CS2WCR_A,r1 + mov.l CS2WCR_D,r0 + mov.l r0,@r1 + + mov.l CS4WCR_A,r1 + mov.l CS4WCR_D,r0 + mov.l r0,@r1 + + mov.l CS5WCR_A,r1 + mov.l CS5WCR_D,r0 + mov.l r0,@r1 + + mov.l CS6WCR_A,r1 + mov.l CS6WCR_D,r0 + mov.l r0,@r1 + + mov.l CS5PCR_A,r1 + mov.l CS5PCR_D,r0 + mov.l r0,@r1 + + mov.l CS6PCR_A,r1 + mov.l CS6PCR_D,r0 + mov.l r0,@r1 + + /* ddr_setting */ + /* wait 200us */ + mov.l REPEAT0_R3,r3 + mov #0,r2 +repeat1: + add #1,r2 + cmp/hs r3,r2 + bf repeat1 + nop + + mov.l MIM_U_A,r0 + mov.l MIM_U_D,r1 + synco + mov.l r1,@r0 + synco + + mov.l MIM_L_A,r0 + mov.l MIM_L_D0,r1 + synco + mov.l r1,@r0 + synco + + mov.l STR_L_A,r0 + mov.l STR_L_D,r1 + synco + mov.l r1,@r0 + synco + + mov.l SDR_L_A,r0 + mov.l SDR_L_D,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + nop + + mov.l SCR_L_A,r0 + mov.l SCR_L_D0,r1 + synco + mov.l r1,@r0 + synco + + mov.l SCR_L_A,r0 + mov.l SCR_L_D1,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + + mov.l EMRS_A,r0 + mov.l EMRS_D,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + + mov.l MRS1_A,r0 + mov.l MRS1_D,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + + mov.l SCR_L_A,r0 + mov.l SCR_L_D2,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + + mov.l SCR_L_A,r0 + mov.l SCR_L_D3,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + + mov.l SCR_L_A,r0 + mov.l SCR_L_D4,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + + mov.l MRS2_A,r0 + mov.l MRS2_D,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + + mov.l SCR_L_A,r0 + mov.l SCR_L_D5,r1 + synco + mov.l r1,@r0 + synco + + /* wait 200us */ + mov.l REPEAT0_R1,r3 + mov #0,r2 +repeat2: + add #1,r2 + cmp/hs r3,r2 + bf repeat2 + + synco + + mov.l MIM_L_A,r0 + mov.l MIM_L_D1,r1 + synco + mov.l r1,@r0 + synco + + rts + nop + .align 4 + +RWTCSR_D_1: .word 0xA507 +RWTCSR_D_2: .word 0xA507 +RWTCNT_D: .word 0x5A00 + .align 2 + +BBG_PMMR_A: .long 0xFF800010 +BBG_PMSR1_A: .long 0xFF800014 +BBG_PMSR2_A: .long 0xFF800018 +BBG_PMSR3_A: .long 0xFF80001C +BBG_PMSR4_A: .long 0xFF800020 +BBG_PMSRG_A: .long 0xFF800024 + +BBG_PMMR_D_PMSR1: .long 0xffffbffd +BBG_PMSR1_D: .long 0x00004002 +BBG_PMMR_D_PMSR2: .long 0xfc21a7ff +BBG_PMSR2_D: .long 0x03de5800 +BBG_PMMR_D_PMSR3: .long 0xfffffff8 +BBG_PMSR3_D: .long 0x00000007 +BBG_PMMR_D_PMSR4: .long 0xdffdfff9 +BBG_PMSR4_D: .long 0x20020006 +BBG_PMMR_D_PMSRG: .long 0xffffffff +BBG_PMSRG_D: .long 0x00000000 + +FRQCR_A: .long FRQCR +DLLCSR_A: .long 0xffc40010 +FRQCR_D: .long 0x40233035 +DLLCSR_D: .long 0x00000000 + +/* for DDR-SDRAM */ +MIM_U_A: .long MIM_1 +MIM_L_A: .long MIM_2 +SCR_U_A: .long SCR_1 +SCR_L_A: .long SCR_2 +STR_U_A: .long STR_1 +STR_L_A: .long STR_2 +SDR_U_A: .long SDR_1 +SDR_L_A: .long SDR_2 + +EMRS_A: .long 0xFEC02000 +MRS1_A: .long 0xFEC00B08 +MRS2_A: .long 0xFEC00308 + +MIM_U_D: .long 0x00004000 +MIM_L_D0: .long 0x03e80009 +MIM_L_D1: .long 0x03e80209 +SCR_L_D0: .long 0x3 +SCR_L_D1: .long 0x2 +SCR_L_D2: .long 0x2 +SCR_L_D3: .long 0x4 +SCR_L_D4: .long 0x4 +SCR_L_D5: .long 0x0 +STR_L_D: .long 0x000f0000 +SDR_L_D: .long 0x00000400 +EMRS_D: .long 0x0 +MRS1_D: .long 0x0 +MRS2_D: .long 0x0 + +/* Cache Controller */ +CCR_A: .long CCR +MMUCR_A: .long MMUCR +RWTCNT_A: .long WTCNT + +CCR_D: .long 0x0000090b +CCR_D_2: .long 0x00000103 +MMUCR_D: .long 0x00000004 +MSTPCR0_D: .long 0x00001001 +MSTPCR2_D: .long 0xffffffff + +/* local Bus State Controller */ +MMSELR_A: .long MMSELR +BCR_A: .long BCR +CS0BCR_A: .long CS0BCR +CS1BCR_A: .long CS1BCR +CS2BCR_A: .long CS2BCR +CS4BCR_A: .long CS4BCR +CS5BCR_A: .long CS5BCR +CS6BCR_A: .long CS6BCR +CS0WCR_A: .long CS0WCR +CS1WCR_A: .long CS1WCR +CS2WCR_A: .long CS2WCR +CS4WCR_A: .long CS4WCR +CS5WCR_A: .long CS5WCR +CS6WCR_A: .long CS6WCR +CS5PCR_A: .long CS5PCR +CS6PCR_A: .long CS6PCR + +MMSELR_D: .long 0xA5A50003 +BCR_D: .long 0x00000000 +CS0BCR_D: .long 0x77777770 +CS1BCR_D: .long 0x77777670 +CS2BCR_D: .long 0x77777770 +CS4BCR_D: .long 0x77777770 +CS5BCR_D: .long 0x77777670 +CS6BCR_D: .long 0x77777770 +CS0WCR_D: .long 0x00020006 +CS1WCR_D: .long 0x00232304 +CS2WCR_D: .long 0x7777770F +CS4WCR_D: .long 0x7777770F +CS5WCR_D: .long 0x00101006 +CS6WCR_D: .long 0x77777703 +CS5PCR_D: .long 0x77000000 +CS6PCR_D: .long 0x77000000 + +REPEAT0_R3: .long 0x00002000 +REPEAT0_R1: .long 0x0000200 diff --git a/board/renesas/r7780mp/r7780mp.c b/board/renesas/r7780mp/r7780mp.c new file mode 100644 index 0000000000..396e4b6db3 --- /dev/null +++ b/board/renesas/r7780mp/r7780mp.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2007,2008 Nobuhiro Iwamatsu + * Copyright (C) 2008 Yusuke Goda + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include "r7780mp.h" + +int checkboard(void) +{ +#if defined(CONFIG_R7780MP) + puts("BOARD: Renesas Solutions R7780MP\n"); +#else + puts("BOARD: Renesas Solutions R7780RP\n"); +#endif + return 0; +} + +int board_init(void) +{ + /* SCIF Enable */ + writew(0x0, PHCR); + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state(unsigned short value) +{ + +} + +void ide_set_reset(int idereset) +{ + /* if reset = 1 IDE reset will be asserted */ + if (idereset) { + writew(0x432, FPGA_CFCTL); +#if defined(CONFIG_R7780MP) + writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW); +#else + writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW); +#endif + writew(0x01, FPGA_CFCDINTCLR); + } +} + +static struct pci_controller hose; +void pci_init_board(void) +{ + pci_sh7780_init(&hose); +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/renesas/r7780mp/r7780mp.h b/board/renesas/r7780mp/r7780mp.h new file mode 100644 index 0000000000..476a41354f --- /dev/null +++ b/board/renesas/r7780mp/r7780mp.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2007 Nobuhiro Iwamatsu + * Copyright (C) 2008 Yusuke Goda + * + * u-boot/board/r7780mp/r7780mp.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BOARD_R7780MP_R7780MP_H_ +#define _BOARD_R7780MP_R7780MP_H_ + +/* R7780MP's FPGA register map */ +#define FPGA_BASE 0xa4000000 +#define FPGA_IRLMSK (FPGA_BASE + 0x00) +#define FPGA_IRLMON (FPGA_BASE + 0x02) +#define FPGA_IRLPRI1 (FPGA_BASE + 0x04) +#define FPGA_IRLPRI2 (FPGA_BASE + 0x06) +#define FPGA_IRLPRI3 (FPGA_BASE + 0x08) +#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A) +#define FPGA_RSTCTL (FPGA_BASE + 0x0C) +#define FPGA_PCIBD (FPGA_BASE + 0x0E) +#define FPGA_PCICD (FPGA_BASE + 0x10) +#define FPGA_EXTGIO (FPGA_BASE + 0x16) +#define FPGA_IVDRMON (FPGA_BASE + 0x18) +#define FPGA_IVDRCR (FPGA_BASE + 0x1A) +#define FPGA_OBLED (FPGA_BASE + 0x1C) +#define FPGA_OBSW (FPGA_BASE + 0x1E) +#define FPGA_TPCTL (FPGA_BASE + 0x100) +#define FPGA_TPDCKCTL (FPGA_BASE + 0x102) +#define FPGA_TPCLR (FPGA_BASE + 0x104) +#define FPGA_TPXPOS (FPGA_BASE + 0x106) +#define FPGA_TPYPOS (FPGA_BASE + 0x108) +#define FPGA_DBSW (FPGA_BASE + 0x200) +#define FPGA_VERSION (FPGA_BASE + 0x700) +#define FPGA_CFCTL (FPGA_BASE + 0x300) +#define FPGA_CFPOW (FPGA_BASE + 0x302) +#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304) +#define FPGA_PMR (FPGA_BASE + 0x900) + +#endif /* _BOARD_R7780RP_R7780RP_H_ */ diff --git a/board/renesas/r7780mp/u-boot.lds b/board/renesas/r7780mp/u-boot.lds new file mode 100644 index 0000000000..eaa05d0d58 --- /dev/null +++ b/board/renesas/r7780mp/u-boot.lds @@ -0,0 +1,105 @@ +/* + * Copyrigth (c) 2007,2008 + * Nobuhiro Iwamatsu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x0C000000. + Although size of SDRAM can be either 16 or 32 MBytes, + we assume 16 MBytes (ie ignore upper half if the full + 32 MBytes is present). + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x08000000 + (128*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} -- cgit v1.2.1 From c6525d459c350bfc246ea7826456af77e1e314eb Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 24 Oct 2008 10:35:19 +0900 Subject: sh: sh7785lcr: Moved sh7785lcr board to board/renesas Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/sh7785lcr/Makefile | 42 ++++ board/renesas/sh7785lcr/config.mk | 25 +++ board/renesas/sh7785lcr/lowlevel_init.S | 317 +++++++++++++++++++++++++++++ board/renesas/sh7785lcr/rtl8169.h | 57 ++++++ board/renesas/sh7785lcr/rtl8169_mac.c | 348 ++++++++++++++++++++++++++++++++ board/renesas/sh7785lcr/selfcheck.c | 172 ++++++++++++++++ board/renesas/sh7785lcr/sh7785lcr.c | 56 +++++ board/renesas/sh7785lcr/u-boot.lds | 96 +++++++++ board/sh7785lcr/Makefile | 42 ---- board/sh7785lcr/config.mk | 25 --- board/sh7785lcr/lowlevel_init.S | 317 ----------------------------- board/sh7785lcr/rtl8169.h | 57 ------ board/sh7785lcr/rtl8169_mac.c | 348 -------------------------------- board/sh7785lcr/selfcheck.c | 172 ---------------- board/sh7785lcr/sh7785lcr.c | 56 ----- board/sh7785lcr/u-boot.lds | 96 --------- 16 files changed, 1113 insertions(+), 1113 deletions(-) create mode 100644 board/renesas/sh7785lcr/Makefile create mode 100644 board/renesas/sh7785lcr/config.mk create mode 100644 board/renesas/sh7785lcr/lowlevel_init.S create mode 100644 board/renesas/sh7785lcr/rtl8169.h create mode 100644 board/renesas/sh7785lcr/rtl8169_mac.c create mode 100644 board/renesas/sh7785lcr/selfcheck.c create mode 100644 board/renesas/sh7785lcr/sh7785lcr.c create mode 100644 board/renesas/sh7785lcr/u-boot.lds delete mode 100644 board/sh7785lcr/Makefile delete mode 100644 board/sh7785lcr/config.mk delete mode 100644 board/sh7785lcr/lowlevel_init.S delete mode 100644 board/sh7785lcr/rtl8169.h delete mode 100644 board/sh7785lcr/rtl8169_mac.c delete mode 100644 board/sh7785lcr/selfcheck.c delete mode 100644 board/sh7785lcr/sh7785lcr.c delete mode 100644 board/sh7785lcr/u-boot.lds (limited to 'board') diff --git a/board/renesas/sh7785lcr/Makefile b/board/renesas/sh7785lcr/Makefile new file mode 100644 index 0000000000..b1b538c9d8 --- /dev/null +++ b/board/renesas/sh7785lcr/Makefile @@ -0,0 +1,42 @@ +# +# Copyright (C) 2008 Yoshihiro Shimoda +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +COBJS := sh7785lcr.o selfcheck.o rtl8169_mac.o +SOBJS := lowlevel_init.o + +$(LIB): $(obj).depend $(COBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(COBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/renesas/sh7785lcr/config.mk b/board/renesas/sh7785lcr/config.mk new file mode 100644 index 0000000000..20807dfc52 --- /dev/null +++ b/board/renesas/sh7785lcr/config.mk @@ -0,0 +1,25 @@ +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# +TEXT_BASE = 0x0ff80000 diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S new file mode 100644 index 0000000000..50e1789cc5 --- /dev/null +++ b/board/renesas/sh7785lcr/lowlevel_init.S @@ -0,0 +1,317 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include + +.macro write32, addr, data + mov.l \addr ,r1 + mov.l \data ,r0 + mov.l r0, @r1 +.endm + +.macro write16, addr, data + mov.l \addr ,r1 + mov.l \data ,r0 + mov.w r0, @r1 +.endm + +.macro write8, addr, data + mov.l \addr ,r1 + mov.l \data ,r0 + mov.b r0, @r1 +.endm + +.macro wait_timer, time + mov.l \time ,r3 +1: + nop + tst r3, r3 + bf/s 1b + dt r3 +.endm + +#include + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + wait_timer WAIT_200US + wait_timer WAIT_200US + + /*------- LBSC -------*/ + write32 MMSELR_A, MMSELR_D + + /*------- DBSC2 -------*/ + write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D + write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D + write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D + write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D + write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1 + write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2 + wait_timer WAIT_200US + + write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D + write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H + wait_timer WAIT_200US + write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2 + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3 + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1 + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1 + write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL + write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF + write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2 + wait_timer WAIT_200US + + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2 + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1 + + write32 DBSC2_DBEN_A, DBSC2_DBEN_D + write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D + write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D + write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D + wait_timer WAIT_200US + + /*------- GPIO -------*/ + write16 PACR_A, PACR_D + write16 PBCR_A, PBCR_D + write16 PCCR_A, PCCR_D + write16 PDCR_A, PDCR_D + write16 PECR_A, PECR_D + write16 PFCR_A, PFCR_D + write16 PGCR_A, PGCR_D + write16 PHCR_A, PHCR_D + write16 PJCR_A, PJCR_D + write16 PKCR_A, PKCR_D + write16 PLCR_A, PLCR_D + write16 PMCR_A, PMCR_D + write16 PNCR_A, PNCR_D + write16 PPCR_A, PPCR_D + write16 PQCR_A, PQCR_D + write16 PRCR_A, PRCR_D + + write8 PEPUPR_A, PEPUPR_D + write8 PHPUPR_A, PHPUPR_D + write8 PJPUPR_A, PJPUPR_D + write8 PKPUPR_A, PKPUPR_D + write8 PLPUPR_A, PLPUPR_D + write8 PMPUPR_A, PMPUPR_D + write8 PNPUPR_A, PNPUPR_D + write16 PPUPR1_A, PPUPR1_D + write16 PPUPR2_A, PPUPR2_D + write16 P1MSELR_A, P1MSELR_D + write16 P2MSELR_A, P2MSELR_D + + /*------- LBSC -------*/ + write32 BCR_A, BCR_D + write32 CS0BCR_A, CS0BCR_D + write32 CS0WCR_A, CS0WCR_D + write32 CS1BCR_A, CS1BCR_D + write32 CS1WCR_A, CS1WCR_D + write32 CS4BCR_A, CS4BCR_D + write32 CS4WCR_A, CS4WCR_D + + mov.l PASCR_A, r0 + mov.l @r0, r2 + mov.l PASCR_32BIT_MODE, r1 + tst r1, r2 + bt lbsc_29bit + + write32 CS2BCR_A, CS_USB_BCR_D + write32 CS2WCR_A, CS_USB_WCR_D + write32 CS3BCR_A, CS_SD_BCR_D + write32 CS3WCR_A, CS_SD_WCR_D + write32 CS5BCR_A, CS_I2C_BCR_D + write32 CS5WCR_A, CS_I2C_WCR_D + write32 CS6BCR_A, CS0BCR_D + write32 CS6WCR_A, CS0WCR_D + bra lbsc_end + nop + +lbsc_29bit: + write32 CS5BCR_A, CS_USB_BCR_D + write32 CS5WCR_A, CS_USB_WCR_D + write32 CS6BCR_A, CS_SD_BCR_D + write32 CS6WCR_A, CS_SD_WCR_D + +lbsc_end: + + write32 CCR_A, CCR_D + + rts + nop + + .align 4 + +/*------- LBSC -------*/ +MMSELR_A: .long 0xfc400020 +MMSELR_D: .long 0xa5a50002 + +/*------- DBSC2 -------*/ +#define DBSC2_BASE 0xfe800000 +DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c +DBSC2_DBEN_A: .long DBSC2_BASE + 0x10 +DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14 +DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20 +DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30 +DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34 +DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38 +DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40 +DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44 +DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48 +DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c +DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50 +DBSC2_DBDICODTOCD_A: .long DBSC2_BASE + 0x54 +DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60 +DDR_DUMMY_ACCESS_A: .long 0x40000000 + +DBSC2_DBCONF_D: .long 0x00630002 +DBSC2_DBTR0_D: .long 0x050b1f04 +DBSC2_DBTR1_D: .long 0x00040204 +DBSC2_DBTR2_D: .long 0x02100308 +DBSC2_DBFREQ_D1: .long 0x00000000 +DBSC2_DBFREQ_D2: .long 0x00000100 +DBSC2_DBDICODTOCD_D: .long 0x000f0907 + +DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003 +DBSC2_DBCMDCNT_D_PALL: .long 0x00000002 +DBSC2_DBCMDCNT_D_REF: .long 0x00000004 + +DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000 +DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000 +DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006 +DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386 +DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952 +DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852 + +DBSC2_DBEN_D: .long 0x00000001 + +DBSC2_DBPDCNT0_D3: .long 0x00000080 +DBSC2_DBRFCNT1_D: .long 0x00000926 +DBSC2_DBRFCNT2_D: .long 0x00fe00fe +DBSC2_DBRFCNT0_D: .long 0x00010000 + +WAIT_200US: .long 33333 + +/*------- GPIO -------*/ +#define GPIO_BASE 0xffe70000 +PACR_A: .long GPIO_BASE + 0x00 +PBCR_A: .long GPIO_BASE + 0x02 +PCCR_A: .long GPIO_BASE + 0x04 +PDCR_A: .long GPIO_BASE + 0x06 +PECR_A: .long GPIO_BASE + 0x08 +PFCR_A: .long GPIO_BASE + 0x0a +PGCR_A: .long GPIO_BASE + 0x0c +PHCR_A: .long GPIO_BASE + 0x0e +PJCR_A: .long GPIO_BASE + 0x10 +PKCR_A: .long GPIO_BASE + 0x12 +PLCR_A: .long GPIO_BASE + 0x14 +PMCR_A: .long GPIO_BASE + 0x16 +PNCR_A: .long GPIO_BASE + 0x18 +PPCR_A: .long GPIO_BASE + 0x1a +PQCR_A: .long GPIO_BASE + 0x1c +PRCR_A: .long GPIO_BASE + 0x1e +PEPUPR_A: .long GPIO_BASE + 0x48 +PHPUPR_A: .long GPIO_BASE + 0x4e +PJPUPR_A: .long GPIO_BASE + 0x50 +PKPUPR_A: .long GPIO_BASE + 0x52 +PLPUPR_A: .long GPIO_BASE + 0x54 +PMPUPR_A: .long GPIO_BASE + 0x56 +PNPUPR_A: .long GPIO_BASE + 0x58 +PPUPR1_A: .long GPIO_BASE + 0x60 +PPUPR2_A: .long GPIO_BASE + 0x62 +P1MSELR_A: .long GPIO_BASE + 0x80 +P2MSELR_A: .long GPIO_BASE + 0x82 + +PACR_D: .long 0x0000 +PBCR_D: .long 0x0000 +PCCR_D: .long 0x0000 +PDCR_D: .long 0x0000 +PECR_D: .long 0x0000 +PFCR_D: .long 0x0000 +PGCR_D: .long 0x0000 +PHCR_D: .long 0x00c0 +PJCR_D: .long 0xc3fc +PKCR_D: .long 0x03ff +PLCR_D: .long 0x0000 +PMCR_D: .long 0xffff +PNCR_D: .long 0xf0c3 +PPCR_D: .long 0x0000 +PQCR_D: .long 0x0000 +PRCR_D: .long 0x0000 + +PEPUPR_D: .long 0xff +PHPUPR_D: .long 0x00 +PJPUPR_D: .long 0x00 +PKPUPR_D: .long 0x00 +PLPUPR_D: .long 0x00 +PMPUPR_D: .long 0xfc +PNPUPR_D: .long 0x00 +PPUPR1_D: .long 0xffbf +PPUPR2_D: .long 0xff00 +P1MSELR_D: .long 0x3780 +P2MSELR_D: .long 0x0000 + +/*------- LBSC -------*/ +PASCR_A: .long 0xff000070 +PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */ + +BCR_A: .long BCR +CS0BCR_A: .long CS0BCR +CS0WCR_A: .long CS0WCR +CS1BCR_A: .long CS1BCR +CS1WCR_A: .long CS1WCR +CS2BCR_A: .long CS2BCR +CS2WCR_A: .long CS2WCR +CS3BCR_A: .long CS3BCR +CS3WCR_A: .long CS3WCR +CS4BCR_A: .long CS4BCR +CS4WCR_A: .long CS4WCR +CS5BCR_A: .long CS5BCR +CS5WCR_A: .long CS5WCR +CS6BCR_A: .long CS6BCR +CS6WCR_A: .long CS6WCR + +BCR_D: .long 0x80000003 +CS0BCR_D: .long 0x22222340 +CS0WCR_D: .long 0x00111118 +CS1BCR_D: .long 0x11111100 +CS1WCR_D: .long 0x33333303 +CS4BCR_D: .long 0x11111300 +CS4WCR_D: .long 0x00101012 + +/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */ +CS_USB_BCR_D: .long 0x11111200 +CS_USB_WCR_D: .long 0x00020004 + +/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */ +CS_SD_BCR_D: .long 0x00000300 +CS_SD_WCR_D: .long 0x00030108 + +/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */ +CS_I2C_BCR_D: .long 0x11111100 +CS_I2C_WCR_D: .long 0x00000003 + +CCR_A: .long 0xff00001c +CCR_D: .long 0x0000090b diff --git a/board/renesas/sh7785lcr/rtl8169.h b/board/renesas/sh7785lcr/rtl8169.h new file mode 100644 index 0000000000..ca9c0bd94c --- /dev/null +++ b/board/renesas/sh7785lcr/rtl8169.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define PCIREG_8(_adr) (*(volatile unsigned char *)(_adr)) +#define PCIREG_32(_adr) (*(volatile unsigned long *)(_adr)) +#define PCI_PAR PCIREG_32(0xfe0401c0) +#define PCI_PDR PCIREG_32(0xfe040220) +#define PCI_CR PCIREG_32(0xfe040100) +#define PCI_CONF1 PCIREG_32(0xfe040004) + +#define HIGH 1 +#define LOW 0 + +#define PCI_PROG 0x80 +#define PCI_EEP_ADDRESS (unsigned short)0x0007 +#define PCI_MAC_ADDRESS_SIZE 3 + +#define TIME1 100 +#define TIME2 20000 + +#define BIT_DUMMY 0 +#define MAC_EEP_READ 1 +#define MAC_EEP_WRITE 2 +#define MAC_EEP_ERACE 3 +#define MAC_EEP_EWEN 4 +#define MAC_EEP_EWDS 5 + +/* RTL8169 */ +const unsigned short EEPROM_W_Data_8169_A[] = { + 0x8129, 0x10ec, 0x8169, 0x1154, 0x032b, + 0x4020, 0xa101 +}; +const unsigned short EEPROM_W_Data_8169_B[] = { + 0x4d15, 0xf7c2, 0x8000, 0x0000, 0x0000, 0x1300, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 +}; diff --git a/board/renesas/sh7785lcr/rtl8169_mac.c b/board/renesas/sh7785lcr/rtl8169_mac.c new file mode 100644 index 0000000000..bf0ba145d2 --- /dev/null +++ b/board/renesas/sh7785lcr/rtl8169_mac.c @@ -0,0 +1,348 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "rtl8169.h" + +static unsigned char *PCI_MEMR; + +static void mac_delay(unsigned int cnt) +{ + udelay(cnt); +} + +static void mac_pci_setup(void) +{ + unsigned long pci_data; + + PCI_PAR = 0x00000010; + PCI_PDR = 0x00001000; + PCI_PAR = 0x00000004; + pci_data = PCI_PDR; + PCI_PDR = pci_data | 0x00000007; + PCI_PAR = 0x00000010; + + PCI_MEMR = (unsigned char *)((PCI_PDR | 0xFE240050) & 0xFFFFFFF0); +} + +static void EECS(int level) +{ + unsigned char data = *PCI_MEMR; + + if (level) + *PCI_MEMR = data | 0x08; + else + *PCI_MEMR = data & 0xf7; +} + +static void EECLK(int level) +{ + unsigned char data = *PCI_MEMR; + + if (level) + *PCI_MEMR = data | 0x04; + else + *PCI_MEMR = data & 0xfb; +} + +static void EEDI(int level) +{ + unsigned char data = *PCI_MEMR; + + if (level) + *PCI_MEMR = data | 0x02; + else + *PCI_MEMR = data & 0xfd; +} + +static inline void sh7785lcr_bitset(unsigned short bit) +{ + if (bit) + EEDI(HIGH); + else + EEDI(LOW); + + EECLK(LOW); + mac_delay(TIME1); + EECLK(HIGH); + mac_delay(TIME1); + EEDI(LOW); +} + +static inline unsigned char sh7785lcr_bitget(void) +{ + unsigned char bit; + + EECLK(LOW); + mac_delay(TIME1); + bit = *PCI_MEMR & 0x01; + EECLK(HIGH); + mac_delay(TIME1); + + return bit; +} + +static inline void sh7785lcr_setcmd(unsigned char command) +{ + sh7785lcr_bitset(BIT_DUMMY); + switch (command) { + case MAC_EEP_READ: + sh7785lcr_bitset(1); + sh7785lcr_bitset(1); + sh7785lcr_bitset(0); + break; + case MAC_EEP_WRITE: + sh7785lcr_bitset(1); + sh7785lcr_bitset(0); + sh7785lcr_bitset(1); + break; + case MAC_EEP_ERACE: + sh7785lcr_bitset(1); + sh7785lcr_bitset(1); + sh7785lcr_bitset(1); + break; + case MAC_EEP_EWEN: + sh7785lcr_bitset(1); + sh7785lcr_bitset(0); + sh7785lcr_bitset(0); + break; + case MAC_EEP_EWDS: + sh7785lcr_bitset(1); + sh7785lcr_bitset(0); + sh7785lcr_bitset(0); + break; + default: + break; + } +} + +static inline unsigned short sh7785lcr_getdt(void) +{ + unsigned short data = 0; + int i; + + sh7785lcr_bitget(); /* DUMMY */ + for (i = 0 ; i < 16 ; i++) { + data <<= 1; + data |= sh7785lcr_bitget(); + } + return data; +} + +static inline void sh7785lcr_setadd(unsigned short address) +{ + sh7785lcr_bitset(address & 0x0020); /* A5 */ + sh7785lcr_bitset(address & 0x0010); /* A4 */ + sh7785lcr_bitset(address & 0x0008); /* A3 */ + sh7785lcr_bitset(address & 0x0004); /* A2 */ + sh7785lcr_bitset(address & 0x0002); /* A1 */ + sh7785lcr_bitset(address & 0x0001); /* A0 */ +} + +static inline void sh7785lcr_setdata(unsigned short data) +{ + sh7785lcr_bitset(data & 0x8000); + sh7785lcr_bitset(data & 0x4000); + sh7785lcr_bitset(data & 0x2000); + sh7785lcr_bitset(data & 0x1000); + sh7785lcr_bitset(data & 0x0800); + sh7785lcr_bitset(data & 0x0400); + sh7785lcr_bitset(data & 0x0200); + sh7785lcr_bitset(data & 0x0100); + sh7785lcr_bitset(data & 0x0080); + sh7785lcr_bitset(data & 0x0040); + sh7785lcr_bitset(data & 0x0020); + sh7785lcr_bitset(data & 0x0010); + sh7785lcr_bitset(data & 0x0008); + sh7785lcr_bitset(data & 0x0004); + sh7785lcr_bitset(data & 0x0002); + sh7785lcr_bitset(data & 0x0001); +} + +static void sh7785lcr_datawrite(const unsigned short *data, unsigned short address, + unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) { + EECS(HIGH); + EEDI(LOW); + mac_delay(TIME1); + + sh7785lcr_setcmd(MAC_EEP_WRITE); + sh7785lcr_setadd(address++); + sh7785lcr_setdata(*(data + i)); + + EECLK(LOW); + EEDI(LOW); + EECS(LOW); + mac_delay(TIME2); + } +} + +static void sh7785lcr_macerase(void) +{ + unsigned int i; + unsigned short pci_address = 7; + + for (i = 0; i < 3; i++) { + EECS(HIGH); + EEDI(LOW); + mac_delay(TIME1); + sh7785lcr_setcmd(MAC_EEP_ERACE); + sh7785lcr_setadd(pci_address++); + mac_delay(TIME1); + EECLK(LOW); + EEDI(LOW); + EECS(LOW); + } + + mac_delay(TIME2); + + printf("\n\nErace End\n"); + for (i = 0; i < 10; i++) + mac_delay(TIME2); +} + +static void sh7785lcr_macwrite(unsigned short *data) +{ + sh7785lcr_macerase(); + + sh7785lcr_datawrite(EEPROM_W_Data_8169_A, 0x0000, 7); + sh7785lcr_datawrite(data, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE); + sh7785lcr_datawrite(EEPROM_W_Data_8169_B, 0x000a, 54); +} + +void sh7785lcr_macdtrd(unsigned char *buf, unsigned short address, unsigned int count) +{ + unsigned int i; + unsigned short wk; + + for (i = 0 ; i < count; i++) { + EECS(HIGH); + EEDI(LOW); + mac_delay(TIME1); + sh7785lcr_setcmd(MAC_EEP_READ); + sh7785lcr_setadd(address++); + wk = sh7785lcr_getdt(); + + *buf++ = (unsigned char)(wk & 0xff); + *buf++ = (unsigned char)((wk >> 8) & 0xff); + EECLK(LOW); + EEDI(LOW); + EECS(LOW); + } +} + +static void sh7785lcr_macadrd(unsigned char *buf) +{ + *PCI_MEMR = PCI_PROG; + + sh7785lcr_macdtrd(buf, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE); +} + +static void sh7785lcr_eepewen(void) +{ + *PCI_MEMR = PCI_PROG; + mac_delay(TIME1); + EECS(LOW); + EECLK(LOW); + EEDI(LOW); + EECS(HIGH); + mac_delay(TIME1); + + sh7785lcr_setcmd(MAC_EEP_EWEN); + sh7785lcr_bitset(1); + sh7785lcr_bitset(1); + sh7785lcr_bitset(BIT_DUMMY); + sh7785lcr_bitset(BIT_DUMMY); + sh7785lcr_bitset(BIT_DUMMY); + sh7785lcr_bitset(BIT_DUMMY); + + EECLK(LOW); + EEDI(LOW); + EECS(LOW); + mac_delay(TIME1); +} + +void mac_write(unsigned short *data) +{ + mac_pci_setup(); + sh7785lcr_eepewen(); + sh7785lcr_macwrite(data); +} + +void mac_read(void) +{ + unsigned char data[6]; + + mac_pci_setup(); + sh7785lcr_macadrd(data); + printf("Mac = %02x:%02x:%02x:%02x:%02x:%02x\n", + data[0], data[1], data[2], data[3], data[4], data[5]); +} + +int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + unsigned char mac[6]; + char *s, *e; + + if (argc != 2) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + s = argv[1]; + + for (i = 0; i < 6; i++) { + mac[i] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + mac_write((unsigned short *)mac); + + return 0; +} + +U_BOOT_CMD( + setmac, 2, 1, do_set_mac, + "setmac - write MAC address for RTL8110SCL\n", + "\n" + "setmac - write MAC address for RTL8110SCL\n" +); + +int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc != 1) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + mac_read(); + + return 0; +} + +U_BOOT_CMD( + printmac, 1, 1, do_print_mac, + "printmac - print MAC address for RTL8110\n", + "\n" + " - print MAC address for RTL8110\n" +); diff --git a/board/renesas/sh7785lcr/selfcheck.c b/board/renesas/sh7785lcr/selfcheck.c new file mode 100644 index 0000000000..ce0620f687 --- /dev/null +++ b/board/renesas/sh7785lcr/selfcheck.c @@ -0,0 +1,172 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#if defined(CONFIG_CPU_32BIT) +#define NOCACHE_OFFSET 0x00000000 +#else +#define NOCACHE_OFFSET 0xa0000000 +#endif +#define PLD_LEDCR (0x04000008 + NOCACHE_OFFSET) +#define PLD_SWSR (0x0400000a + NOCACHE_OFFSET) +#define PLD_VERSR (0x0400000c + NOCACHE_OFFSET) + +#define SM107_DEVICEID (0x13e00060 + NOCACHE_OFFSET) + +static void wait_ms(unsigned long time) +{ + while (time--) + udelay(1000); +} + +static void test_pld(void) +{ + printf("PLD version = %04x\n", readb(PLD_VERSR)); +} + +static void test_sm107(void) +{ + printf("SM107 device ID = %04x\n", readl(SM107_DEVICEID)); +} + +static void test_led(void) +{ + printf("turn on LEDs 3, 5, 7, 9\n"); + writeb(0x55, PLD_LEDCR); + wait_ms(2000); + printf("turn on LEDs 4, 6, 8, 10\n"); + writeb(0xaa, PLD_LEDCR); + wait_ms(2000); + writeb(0x00, PLD_LEDCR); +} + +static void test_dipsw(void) +{ + printf("Please DIPSW set = B'0101\n"); + while (readb(PLD_SWSR) != 0x05) { + if (ctrlc()) + return; + } + printf("Please DIPSW set = B'1010\n"); + while (readb(PLD_SWSR) != 0x0A) { + if (ctrlc()) + return; + } + printf("DIPSW OK\n"); +} + +static void test_net(void) +{ + unsigned long data; + + writel(0x80000000, 0xfe0401c0); + data = readl(0xfe040220); + if (data == 0x816910ec) + printf("Ethernet OK\n"); + else + printf("Ethernet NG, data = %08x\n", (unsigned int)data); +} + +static void test_sata(void) +{ + unsigned long data; + + writel(0x80000800, 0xfe0401c0); + data = readl(0xfe040220); + if (data == 0x35121095) + printf("SATA OK\n"); + else + printf("SATA NG, data = %08x\n", (unsigned int)data); +} + +static void test_pci(void) +{ + writel(0x80001800, 0xfe0401c0); + printf("PCI CN1 ID = %08x\n", readl(0xfe040220)); + + writel(0x80001000, 0xfe0401c0); + printf("PCI CN2 ID = %08x\n", readl(0xfe040220)); +} + +int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *cmd; + + if (argc != 2) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + cmd = argv[1]; + switch (cmd[0]) { + case 'a': /* all */ + test_pld(); + test_led(); + test_dipsw(); + test_sm107(); + test_net(); + test_sata(); + test_pci(); + break; + case 'p': /* pld or pci */ + if (cmd[1] == 'l') + test_pld(); + else + test_pci(); + break; + case 'l': /* led */ + test_led(); + break; + case 'd': /* dipsw */ + test_dipsw(); + break; + case 's': /* sm107 or sata */ + if (cmd[1] == 'm') + test_sm107(); + else + test_sata(); + break; + case 'n': /* net */ + test_net(); + break; + default: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + return 0; +} + +U_BOOT_CMD( + hwtest, 2, 1, do_hw_test, + "hwtest - hardware test for R0P7785LC0011RL board\n", + "\n" + "hwtest all - test all hardware\n" + "hwtest pld - output PLD version\n" + "hwtest led - turn on LEDs\n" + "hwtest dipsw - test DIP switch\n" + "hwtest sm107 - output SM107 version\n" + "hwtest net - check RTL8110 ID\n" + "hwtest sata - check SiI3512 ID\n" + "hwtest pci - output PCI slot device ID\n" +); diff --git a/board/renesas/sh7785lcr/sh7785lcr.c b/board/renesas/sh7785lcr/sh7785lcr.c new file mode 100644 index 0000000000..786c758a92 --- /dev/null +++ b/board/renesas/sh7785lcr/sh7785lcr.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +int checkboard(void) +{ + puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n"); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +static struct pci_controller hose; +void pci_init_board(void) +{ + pci_sh7780_init(&hose); +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/renesas/sh7785lcr/u-boot.lds b/board/renesas/sh7785lcr/u-boot.lds new file mode 100644 index 0000000000..231769f3b3 --- /dev/null +++ b/board/renesas/sh7785lcr/u-boot.lds @@ -0,0 +1,96 @@ +/* + * Copyrigth (c) 2007 + * Nobuhiro Iwamatsu + * Copyrigth (c) 2008 Yoshihiro Shimoda + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + . = 0x08000000 + (128 * 1024 * 1024) - (512 * 1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/board/sh7785lcr/Makefile b/board/sh7785lcr/Makefile deleted file mode 100644 index b1b538c9d8..0000000000 --- a/board/sh7785lcr/Makefile +++ /dev/null @@ -1,42 +0,0 @@ -# -# Copyright (C) 2008 Yoshihiro Shimoda -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -COBJS := sh7785lcr.o selfcheck.o rtl8169_mac.o -SOBJS := lowlevel_init.o - -$(LIB): $(obj).depend $(COBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(COBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/sh7785lcr/config.mk b/board/sh7785lcr/config.mk deleted file mode 100644 index 20807dfc52..0000000000 --- a/board/sh7785lcr/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright (C) 2007 -# Nobuhiro Iwamatsu -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -# -# TEXT_BASE refers to image _after_ relocation. -# -# NOTE: Must match value used in u-boot.lds (in this directory). -# -TEXT_BASE = 0x0ff80000 diff --git a/board/sh7785lcr/lowlevel_init.S b/board/sh7785lcr/lowlevel_init.S deleted file mode 100644 index 50e1789cc5..0000000000 --- a/board/sh7785lcr/lowlevel_init.S +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Copyright (C) 2008 Yoshihiro Shimoda - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include - -.macro write32, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.l r0, @r1 -.endm - -.macro write16, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.w r0, @r1 -.endm - -.macro write8, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.b r0, @r1 -.endm - -.macro wait_timer, time - mov.l \time ,r3 -1: - nop - tst r3, r3 - bf/s 1b - dt r3 -.endm - -#include - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - wait_timer WAIT_200US - wait_timer WAIT_200US - - /*------- LBSC -------*/ - write32 MMSELR_A, MMSELR_D - - /*------- DBSC2 -------*/ - write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D - write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D - write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D - write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D - write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1 - write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2 - wait_timer WAIT_200US - - write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H - wait_timer WAIT_200US - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1 - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2 - wait_timer WAIT_200US - - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1 - - write32 DBSC2_DBEN_A, DBSC2_DBEN_D - write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D - write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D - write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D - wait_timer WAIT_200US - - /*------- GPIO -------*/ - write16 PACR_A, PACR_D - write16 PBCR_A, PBCR_D - write16 PCCR_A, PCCR_D - write16 PDCR_A, PDCR_D - write16 PECR_A, PECR_D - write16 PFCR_A, PFCR_D - write16 PGCR_A, PGCR_D - write16 PHCR_A, PHCR_D - write16 PJCR_A, PJCR_D - write16 PKCR_A, PKCR_D - write16 PLCR_A, PLCR_D - write16 PMCR_A, PMCR_D - write16 PNCR_A, PNCR_D - write16 PPCR_A, PPCR_D - write16 PQCR_A, PQCR_D - write16 PRCR_A, PRCR_D - - write8 PEPUPR_A, PEPUPR_D - write8 PHPUPR_A, PHPUPR_D - write8 PJPUPR_A, PJPUPR_D - write8 PKPUPR_A, PKPUPR_D - write8 PLPUPR_A, PLPUPR_D - write8 PMPUPR_A, PMPUPR_D - write8 PNPUPR_A, PNPUPR_D - write16 PPUPR1_A, PPUPR1_D - write16 PPUPR2_A, PPUPR2_D - write16 P1MSELR_A, P1MSELR_D - write16 P2MSELR_A, P2MSELR_D - - /*------- LBSC -------*/ - write32 BCR_A, BCR_D - write32 CS0BCR_A, CS0BCR_D - write32 CS0WCR_A, CS0WCR_D - write32 CS1BCR_A, CS1BCR_D - write32 CS1WCR_A, CS1WCR_D - write32 CS4BCR_A, CS4BCR_D - write32 CS4WCR_A, CS4WCR_D - - mov.l PASCR_A, r0 - mov.l @r0, r2 - mov.l PASCR_32BIT_MODE, r1 - tst r1, r2 - bt lbsc_29bit - - write32 CS2BCR_A, CS_USB_BCR_D - write32 CS2WCR_A, CS_USB_WCR_D - write32 CS3BCR_A, CS_SD_BCR_D - write32 CS3WCR_A, CS_SD_WCR_D - write32 CS5BCR_A, CS_I2C_BCR_D - write32 CS5WCR_A, CS_I2C_WCR_D - write32 CS6BCR_A, CS0BCR_D - write32 CS6WCR_A, CS0WCR_D - bra lbsc_end - nop - -lbsc_29bit: - write32 CS5BCR_A, CS_USB_BCR_D - write32 CS5WCR_A, CS_USB_WCR_D - write32 CS6BCR_A, CS_SD_BCR_D - write32 CS6WCR_A, CS_SD_WCR_D - -lbsc_end: - - write32 CCR_A, CCR_D - - rts - nop - - .align 4 - -/*------- LBSC -------*/ -MMSELR_A: .long 0xfc400020 -MMSELR_D: .long 0xa5a50002 - -/*------- DBSC2 -------*/ -#define DBSC2_BASE 0xfe800000 -DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c -DBSC2_DBEN_A: .long DBSC2_BASE + 0x10 -DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14 -DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20 -DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30 -DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34 -DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38 -DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40 -DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44 -DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48 -DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c -DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50 -DBSC2_DBDICODTOCD_A: .long DBSC2_BASE + 0x54 -DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60 -DDR_DUMMY_ACCESS_A: .long 0x40000000 - -DBSC2_DBCONF_D: .long 0x00630002 -DBSC2_DBTR0_D: .long 0x050b1f04 -DBSC2_DBTR1_D: .long 0x00040204 -DBSC2_DBTR2_D: .long 0x02100308 -DBSC2_DBFREQ_D1: .long 0x00000000 -DBSC2_DBFREQ_D2: .long 0x00000100 -DBSC2_DBDICODTOCD_D: .long 0x000f0907 - -DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003 -DBSC2_DBCMDCNT_D_PALL: .long 0x00000002 -DBSC2_DBCMDCNT_D_REF: .long 0x00000004 - -DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000 -DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000 -DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006 -DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386 -DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952 -DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852 - -DBSC2_DBEN_D: .long 0x00000001 - -DBSC2_DBPDCNT0_D3: .long 0x00000080 -DBSC2_DBRFCNT1_D: .long 0x00000926 -DBSC2_DBRFCNT2_D: .long 0x00fe00fe -DBSC2_DBRFCNT0_D: .long 0x00010000 - -WAIT_200US: .long 33333 - -/*------- GPIO -------*/ -#define GPIO_BASE 0xffe70000 -PACR_A: .long GPIO_BASE + 0x00 -PBCR_A: .long GPIO_BASE + 0x02 -PCCR_A: .long GPIO_BASE + 0x04 -PDCR_A: .long GPIO_BASE + 0x06 -PECR_A: .long GPIO_BASE + 0x08 -PFCR_A: .long GPIO_BASE + 0x0a -PGCR_A: .long GPIO_BASE + 0x0c -PHCR_A: .long GPIO_BASE + 0x0e -PJCR_A: .long GPIO_BASE + 0x10 -PKCR_A: .long GPIO_BASE + 0x12 -PLCR_A: .long GPIO_BASE + 0x14 -PMCR_A: .long GPIO_BASE + 0x16 -PNCR_A: .long GPIO_BASE + 0x18 -PPCR_A: .long GPIO_BASE + 0x1a -PQCR_A: .long GPIO_BASE + 0x1c -PRCR_A: .long GPIO_BASE + 0x1e -PEPUPR_A: .long GPIO_BASE + 0x48 -PHPUPR_A: .long GPIO_BASE + 0x4e -PJPUPR_A: .long GPIO_BASE + 0x50 -PKPUPR_A: .long GPIO_BASE + 0x52 -PLPUPR_A: .long GPIO_BASE + 0x54 -PMPUPR_A: .long GPIO_BASE + 0x56 -PNPUPR_A: .long GPIO_BASE + 0x58 -PPUPR1_A: .long GPIO_BASE + 0x60 -PPUPR2_A: .long GPIO_BASE + 0x62 -P1MSELR_A: .long GPIO_BASE + 0x80 -P2MSELR_A: .long GPIO_BASE + 0x82 - -PACR_D: .long 0x0000 -PBCR_D: .long 0x0000 -PCCR_D: .long 0x0000 -PDCR_D: .long 0x0000 -PECR_D: .long 0x0000 -PFCR_D: .long 0x0000 -PGCR_D: .long 0x0000 -PHCR_D: .long 0x00c0 -PJCR_D: .long 0xc3fc -PKCR_D: .long 0x03ff -PLCR_D: .long 0x0000 -PMCR_D: .long 0xffff -PNCR_D: .long 0xf0c3 -PPCR_D: .long 0x0000 -PQCR_D: .long 0x0000 -PRCR_D: .long 0x0000 - -PEPUPR_D: .long 0xff -PHPUPR_D: .long 0x00 -PJPUPR_D: .long 0x00 -PKPUPR_D: .long 0x00 -PLPUPR_D: .long 0x00 -PMPUPR_D: .long 0xfc -PNPUPR_D: .long 0x00 -PPUPR1_D: .long 0xffbf -PPUPR2_D: .long 0xff00 -P1MSELR_D: .long 0x3780 -P2MSELR_D: .long 0x0000 - -/*------- LBSC -------*/ -PASCR_A: .long 0xff000070 -PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */ - -BCR_A: .long BCR -CS0BCR_A: .long CS0BCR -CS0WCR_A: .long CS0WCR -CS1BCR_A: .long CS1BCR -CS1WCR_A: .long CS1WCR -CS2BCR_A: .long CS2BCR -CS2WCR_A: .long CS2WCR -CS3BCR_A: .long CS3BCR -CS3WCR_A: .long CS3WCR -CS4BCR_A: .long CS4BCR -CS4WCR_A: .long CS4WCR -CS5BCR_A: .long CS5BCR -CS5WCR_A: .long CS5WCR -CS6BCR_A: .long CS6BCR -CS6WCR_A: .long CS6WCR - -BCR_D: .long 0x80000003 -CS0BCR_D: .long 0x22222340 -CS0WCR_D: .long 0x00111118 -CS1BCR_D: .long 0x11111100 -CS1WCR_D: .long 0x33333303 -CS4BCR_D: .long 0x11111300 -CS4WCR_D: .long 0x00101012 - -/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */ -CS_USB_BCR_D: .long 0x11111200 -CS_USB_WCR_D: .long 0x00020004 - -/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */ -CS_SD_BCR_D: .long 0x00000300 -CS_SD_WCR_D: .long 0x00030108 - -/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */ -CS_I2C_BCR_D: .long 0x11111100 -CS_I2C_WCR_D: .long 0x00000003 - -CCR_A: .long 0xff00001c -CCR_D: .long 0x0000090b diff --git a/board/sh7785lcr/rtl8169.h b/board/sh7785lcr/rtl8169.h deleted file mode 100644 index ca9c0bd94c..0000000000 --- a/board/sh7785lcr/rtl8169.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (C) 2008 Yoshihiro Shimoda - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define PCIREG_8(_adr) (*(volatile unsigned char *)(_adr)) -#define PCIREG_32(_adr) (*(volatile unsigned long *)(_adr)) -#define PCI_PAR PCIREG_32(0xfe0401c0) -#define PCI_PDR PCIREG_32(0xfe040220) -#define PCI_CR PCIREG_32(0xfe040100) -#define PCI_CONF1 PCIREG_32(0xfe040004) - -#define HIGH 1 -#define LOW 0 - -#define PCI_PROG 0x80 -#define PCI_EEP_ADDRESS (unsigned short)0x0007 -#define PCI_MAC_ADDRESS_SIZE 3 - -#define TIME1 100 -#define TIME2 20000 - -#define BIT_DUMMY 0 -#define MAC_EEP_READ 1 -#define MAC_EEP_WRITE 2 -#define MAC_EEP_ERACE 3 -#define MAC_EEP_EWEN 4 -#define MAC_EEP_EWDS 5 - -/* RTL8169 */ -const unsigned short EEPROM_W_Data_8169_A[] = { - 0x8129, 0x10ec, 0x8169, 0x1154, 0x032b, - 0x4020, 0xa101 -}; -const unsigned short EEPROM_W_Data_8169_B[] = { - 0x4d15, 0xf7c2, 0x8000, 0x0000, 0x0000, 0x1300, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 -}; diff --git a/board/sh7785lcr/rtl8169_mac.c b/board/sh7785lcr/rtl8169_mac.c deleted file mode 100644 index bf0ba145d2..0000000000 --- a/board/sh7785lcr/rtl8169_mac.c +++ /dev/null @@ -1,348 +0,0 @@ -/* - * Copyright (C) 2008 Yoshihiro Shimoda - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "rtl8169.h" - -static unsigned char *PCI_MEMR; - -static void mac_delay(unsigned int cnt) -{ - udelay(cnt); -} - -static void mac_pci_setup(void) -{ - unsigned long pci_data; - - PCI_PAR = 0x00000010; - PCI_PDR = 0x00001000; - PCI_PAR = 0x00000004; - pci_data = PCI_PDR; - PCI_PDR = pci_data | 0x00000007; - PCI_PAR = 0x00000010; - - PCI_MEMR = (unsigned char *)((PCI_PDR | 0xFE240050) & 0xFFFFFFF0); -} - -static void EECS(int level) -{ - unsigned char data = *PCI_MEMR; - - if (level) - *PCI_MEMR = data | 0x08; - else - *PCI_MEMR = data & 0xf7; -} - -static void EECLK(int level) -{ - unsigned char data = *PCI_MEMR; - - if (level) - *PCI_MEMR = data | 0x04; - else - *PCI_MEMR = data & 0xfb; -} - -static void EEDI(int level) -{ - unsigned char data = *PCI_MEMR; - - if (level) - *PCI_MEMR = data | 0x02; - else - *PCI_MEMR = data & 0xfd; -} - -static inline void sh7785lcr_bitset(unsigned short bit) -{ - if (bit) - EEDI(HIGH); - else - EEDI(LOW); - - EECLK(LOW); - mac_delay(TIME1); - EECLK(HIGH); - mac_delay(TIME1); - EEDI(LOW); -} - -static inline unsigned char sh7785lcr_bitget(void) -{ - unsigned char bit; - - EECLK(LOW); - mac_delay(TIME1); - bit = *PCI_MEMR & 0x01; - EECLK(HIGH); - mac_delay(TIME1); - - return bit; -} - -static inline void sh7785lcr_setcmd(unsigned char command) -{ - sh7785lcr_bitset(BIT_DUMMY); - switch (command) { - case MAC_EEP_READ: - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - break; - case MAC_EEP_WRITE: - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - sh7785lcr_bitset(1); - break; - case MAC_EEP_ERACE: - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - break; - case MAC_EEP_EWEN: - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - sh7785lcr_bitset(0); - break; - case MAC_EEP_EWDS: - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - sh7785lcr_bitset(0); - break; - default: - break; - } -} - -static inline unsigned short sh7785lcr_getdt(void) -{ - unsigned short data = 0; - int i; - - sh7785lcr_bitget(); /* DUMMY */ - for (i = 0 ; i < 16 ; i++) { - data <<= 1; - data |= sh7785lcr_bitget(); - } - return data; -} - -static inline void sh7785lcr_setadd(unsigned short address) -{ - sh7785lcr_bitset(address & 0x0020); /* A5 */ - sh7785lcr_bitset(address & 0x0010); /* A4 */ - sh7785lcr_bitset(address & 0x0008); /* A3 */ - sh7785lcr_bitset(address & 0x0004); /* A2 */ - sh7785lcr_bitset(address & 0x0002); /* A1 */ - sh7785lcr_bitset(address & 0x0001); /* A0 */ -} - -static inline void sh7785lcr_setdata(unsigned short data) -{ - sh7785lcr_bitset(data & 0x8000); - sh7785lcr_bitset(data & 0x4000); - sh7785lcr_bitset(data & 0x2000); - sh7785lcr_bitset(data & 0x1000); - sh7785lcr_bitset(data & 0x0800); - sh7785lcr_bitset(data & 0x0400); - sh7785lcr_bitset(data & 0x0200); - sh7785lcr_bitset(data & 0x0100); - sh7785lcr_bitset(data & 0x0080); - sh7785lcr_bitset(data & 0x0040); - sh7785lcr_bitset(data & 0x0020); - sh7785lcr_bitset(data & 0x0010); - sh7785lcr_bitset(data & 0x0008); - sh7785lcr_bitset(data & 0x0004); - sh7785lcr_bitset(data & 0x0002); - sh7785lcr_bitset(data & 0x0001); -} - -static void sh7785lcr_datawrite(const unsigned short *data, unsigned short address, - unsigned int count) -{ - unsigned int i; - - for (i = 0; i < count; i++) { - EECS(HIGH); - EEDI(LOW); - mac_delay(TIME1); - - sh7785lcr_setcmd(MAC_EEP_WRITE); - sh7785lcr_setadd(address++); - sh7785lcr_setdata(*(data + i)); - - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - mac_delay(TIME2); - } -} - -static void sh7785lcr_macerase(void) -{ - unsigned int i; - unsigned short pci_address = 7; - - for (i = 0; i < 3; i++) { - EECS(HIGH); - EEDI(LOW); - mac_delay(TIME1); - sh7785lcr_setcmd(MAC_EEP_ERACE); - sh7785lcr_setadd(pci_address++); - mac_delay(TIME1); - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - } - - mac_delay(TIME2); - - printf("\n\nErace End\n"); - for (i = 0; i < 10; i++) - mac_delay(TIME2); -} - -static void sh7785lcr_macwrite(unsigned short *data) -{ - sh7785lcr_macerase(); - - sh7785lcr_datawrite(EEPROM_W_Data_8169_A, 0x0000, 7); - sh7785lcr_datawrite(data, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE); - sh7785lcr_datawrite(EEPROM_W_Data_8169_B, 0x000a, 54); -} - -void sh7785lcr_macdtrd(unsigned char *buf, unsigned short address, unsigned int count) -{ - unsigned int i; - unsigned short wk; - - for (i = 0 ; i < count; i++) { - EECS(HIGH); - EEDI(LOW); - mac_delay(TIME1); - sh7785lcr_setcmd(MAC_EEP_READ); - sh7785lcr_setadd(address++); - wk = sh7785lcr_getdt(); - - *buf++ = (unsigned char)(wk & 0xff); - *buf++ = (unsigned char)((wk >> 8) & 0xff); - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - } -} - -static void sh7785lcr_macadrd(unsigned char *buf) -{ - *PCI_MEMR = PCI_PROG; - - sh7785lcr_macdtrd(buf, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE); -} - -static void sh7785lcr_eepewen(void) -{ - *PCI_MEMR = PCI_PROG; - mac_delay(TIME1); - EECS(LOW); - EECLK(LOW); - EEDI(LOW); - EECS(HIGH); - mac_delay(TIME1); - - sh7785lcr_setcmd(MAC_EEP_EWEN); - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - sh7785lcr_bitset(BIT_DUMMY); - sh7785lcr_bitset(BIT_DUMMY); - sh7785lcr_bitset(BIT_DUMMY); - sh7785lcr_bitset(BIT_DUMMY); - - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - mac_delay(TIME1); -} - -void mac_write(unsigned short *data) -{ - mac_pci_setup(); - sh7785lcr_eepewen(); - sh7785lcr_macwrite(data); -} - -void mac_read(void) -{ - unsigned char data[6]; - - mac_pci_setup(); - sh7785lcr_macadrd(data); - printf("Mac = %02x:%02x:%02x:%02x:%02x:%02x\n", - data[0], data[1], data[2], data[3], data[4], data[5]); -} - -int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int i; - unsigned char mac[6]; - char *s, *e; - - if (argc != 2) { - printf("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - s = argv[1]; - - for (i = 0; i < 6; i++) { - mac[i] = s ? simple_strtoul(s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - mac_write((unsigned short *)mac); - - return 0; -} - -U_BOOT_CMD( - setmac, 2, 1, do_set_mac, - "setmac - write MAC address for RTL8110SCL\n", - "\n" - "setmac - write MAC address for RTL8110SCL\n" -); - -int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - if (argc != 1) { - printf("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - mac_read(); - - return 0; -} - -U_BOOT_CMD( - printmac, 1, 1, do_print_mac, - "printmac - print MAC address for RTL8110\n", - "\n" - " - print MAC address for RTL8110\n" -); diff --git a/board/sh7785lcr/selfcheck.c b/board/sh7785lcr/selfcheck.c deleted file mode 100644 index ce0620f687..0000000000 --- a/board/sh7785lcr/selfcheck.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (C) 2008 Yoshihiro Shimoda - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#if defined(CONFIG_CPU_32BIT) -#define NOCACHE_OFFSET 0x00000000 -#else -#define NOCACHE_OFFSET 0xa0000000 -#endif -#define PLD_LEDCR (0x04000008 + NOCACHE_OFFSET) -#define PLD_SWSR (0x0400000a + NOCACHE_OFFSET) -#define PLD_VERSR (0x0400000c + NOCACHE_OFFSET) - -#define SM107_DEVICEID (0x13e00060 + NOCACHE_OFFSET) - -static void wait_ms(unsigned long time) -{ - while (time--) - udelay(1000); -} - -static void test_pld(void) -{ - printf("PLD version = %04x\n", readb(PLD_VERSR)); -} - -static void test_sm107(void) -{ - printf("SM107 device ID = %04x\n", readl(SM107_DEVICEID)); -} - -static void test_led(void) -{ - printf("turn on LEDs 3, 5, 7, 9\n"); - writeb(0x55, PLD_LEDCR); - wait_ms(2000); - printf("turn on LEDs 4, 6, 8, 10\n"); - writeb(0xaa, PLD_LEDCR); - wait_ms(2000); - writeb(0x00, PLD_LEDCR); -} - -static void test_dipsw(void) -{ - printf("Please DIPSW set = B'0101\n"); - while (readb(PLD_SWSR) != 0x05) { - if (ctrlc()) - return; - } - printf("Please DIPSW set = B'1010\n"); - while (readb(PLD_SWSR) != 0x0A) { - if (ctrlc()) - return; - } - printf("DIPSW OK\n"); -} - -static void test_net(void) -{ - unsigned long data; - - writel(0x80000000, 0xfe0401c0); - data = readl(0xfe040220); - if (data == 0x816910ec) - printf("Ethernet OK\n"); - else - printf("Ethernet NG, data = %08x\n", (unsigned int)data); -} - -static void test_sata(void) -{ - unsigned long data; - - writel(0x80000800, 0xfe0401c0); - data = readl(0xfe040220); - if (data == 0x35121095) - printf("SATA OK\n"); - else - printf("SATA NG, data = %08x\n", (unsigned int)data); -} - -static void test_pci(void) -{ - writel(0x80001800, 0xfe0401c0); - printf("PCI CN1 ID = %08x\n", readl(0xfe040220)); - - writel(0x80001000, 0xfe0401c0); - printf("PCI CN2 ID = %08x\n", readl(0xfe040220)); -} - -int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - char *cmd; - - if (argc != 2) { - printf("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - cmd = argv[1]; - switch (cmd[0]) { - case 'a': /* all */ - test_pld(); - test_led(); - test_dipsw(); - test_sm107(); - test_net(); - test_sata(); - test_pci(); - break; - case 'p': /* pld or pci */ - if (cmd[1] == 'l') - test_pld(); - else - test_pci(); - break; - case 'l': /* led */ - test_led(); - break; - case 'd': /* dipsw */ - test_dipsw(); - break; - case 's': /* sm107 or sata */ - if (cmd[1] == 'm') - test_sm107(); - else - test_sata(); - break; - case 'n': /* net */ - test_net(); - break; - default: - printf("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - return 0; -} - -U_BOOT_CMD( - hwtest, 2, 1, do_hw_test, - "hwtest - hardware test for R0P7785LC0011RL board\n", - "\n" - "hwtest all - test all hardware\n" - "hwtest pld - output PLD version\n" - "hwtest led - turn on LEDs\n" - "hwtest dipsw - test DIP switch\n" - "hwtest sm107 - output SM107 version\n" - "hwtest net - check RTL8110 ID\n" - "hwtest sata - check SiI3512 ID\n" - "hwtest pci - output PCI slot device ID\n" -); diff --git a/board/sh7785lcr/sh7785lcr.c b/board/sh7785lcr/sh7785lcr.c deleted file mode 100644 index 786c758a92..0000000000 --- a/board/sh7785lcr/sh7785lcr.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2008 Yoshihiro Shimoda - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -int checkboard(void) -{ - puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -int dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -static struct pci_controller hose; -void pci_init_board(void) -{ - pci_sh7780_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/sh7785lcr/u-boot.lds b/board/sh7785lcr/u-boot.lds deleted file mode 100644 index 231769f3b3..0000000000 --- a/board/sh7785lcr/u-boot.lds +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyrigth (c) 2007 - * Nobuhiro Iwamatsu - * Copyrigth (c) 2008 Yoshihiro Shimoda - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - . = 0x08000000 + (128 * 1024 * 1024) - (512 * 1024); - - PROVIDE (reloc_dst = .); - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - cpu/sh4/start.o (.text) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(.rodata) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); - } - PROVIDE (__u_boot_cmd_end = .); - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (_end = .); -} -- cgit v1.2.1 From 78385bf2359d828184d0b3649f7ae6b933420000 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 24 Oct 2008 10:36:13 +0900 Subject: sh: sh7763rdp: Moved sh7763rdp board to board/renesas Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/sh7763rdp/Makefile | 51 +++++ board/renesas/sh7763rdp/config.mk | 11 + board/renesas/sh7763rdp/lowlevel_init.S | 350 ++++++++++++++++++++++++++++++++ board/renesas/sh7763rdp/sh7763rdp.c | 77 +++++++ board/renesas/sh7763rdp/u-boot.lds | 105 ++++++++++ board/sh7763rdp/Makefile | 51 ----- board/sh7763rdp/config.mk | 11 - board/sh7763rdp/lowlevel_init.S | 350 -------------------------------- board/sh7763rdp/sh7763rdp.c | 77 ------- board/sh7763rdp/u-boot.lds | 105 ---------- 10 files changed, 594 insertions(+), 594 deletions(-) create mode 100644 board/renesas/sh7763rdp/Makefile create mode 100644 board/renesas/sh7763rdp/config.mk create mode 100644 board/renesas/sh7763rdp/lowlevel_init.S create mode 100644 board/renesas/sh7763rdp/sh7763rdp.c create mode 100644 board/renesas/sh7763rdp/u-boot.lds delete mode 100644 board/sh7763rdp/Makefile delete mode 100644 board/sh7763rdp/config.mk delete mode 100644 board/sh7763rdp/lowlevel_init.S delete mode 100644 board/sh7763rdp/sh7763rdp.c delete mode 100644 board/sh7763rdp/u-boot.lds (limited to 'board') diff --git a/board/renesas/sh7763rdp/Makefile b/board/renesas/sh7763rdp/Makefile new file mode 100644 index 0000000000..62a683d57f --- /dev/null +++ b/board/renesas/sh7763rdp/Makefile @@ -0,0 +1,51 @@ +# +# Copyright (C) 2008 Renesas Solutions Corp. +# Copyright (C) 2008 Nobuhiro Iwamatsu +# Copyright (C) 2007 Kenati Technologies, Inc. +# +# board/sh7763rdp/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := sh7763rdp.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/renesas/sh7763rdp/config.mk b/board/renesas/sh7763rdp/config.mk new file mode 100644 index 0000000000..c52dbfd7b0 --- /dev/null +++ b/board/renesas/sh7763rdp/config.mk @@ -0,0 +1,11 @@ +# +# board/sh7763rdp/config.mk +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# + +TEXT_BASE = 0x8FFC0000 + +# PLATFORM_CPPFLAGS += -DCONFIG_MULTIBOOT diff --git a/board/renesas/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S new file mode 100644 index 0000000000..2a44eee1ad --- /dev/null +++ b/board/renesas/sh7763rdp/lowlevel_init.S @@ -0,0 +1,350 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu + * Copyright (C) 2007 Kenati Technologies, Inc. + * + * board/sh7763rdp/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + + mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */ + mov.l WDTCSR_D, r0 + mov.l r0, @r1 + + mov.l WDTST_A, r1 /* Watchdog Stop Time Register */ + mov.l WDTST_D, r0 + mov.l r0, @r1 + + mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */ + mov.l WDTBST_D, r0 + mov.l r0, @r1 + + mov.l CCR_A, r1 /* Address of Cache Control Register */ + mov.l CCR_CACHE_ICI_D, r0 /* Instruction Cache Invalidate */ + mov.l r0, @r1 + + mov.l MMUCR_A, r1 /* Address of MMU Control Register */ + mov.l MMU_CONTROL_TI_D, r0 /* TI == TLB Invalidate bit */ + mov.l r0, @r1 + + mov.l MSTPCR0_A, r1 /* Address of Power Control Register 0 */ + mov.l MSTPCR0_D, r0 + mov.l r0, @r1 + + mov.l MSTPCR1_A, r1 /*i Address of Power Control Register 1 */ + mov.l MSTPCR1_D, r0 + mov.l r0, @r1 + + mov.l RAMCR_A,r1 + mov.l RAMCR_D,r0 + mov.l r0, @r1 + + mov.l MMSELR_A,r1 + mov.l MMSELR_D,r0 + synco + mov.l r0, @r1 + + mov.l @r1,r2 /* execute two reads after setting MMSELR*/ + mov.l @r1,r2 + synco + + /* issue memory read */ + mov.l DDRSD_START_A,r1 /* memory address to read*/ + mov.l @r1,r0 + synco + + mov.l MIM8_A,r1 + mov.l MIM8_D,r0 + mov.l r0,@r1 + + mov.l MIMC_A,r1 + mov.l MIMC_D1,r0 + mov.l r0,@r1 + + mov.l STRC_A,r1 + mov.l STRC_D,r0 + mov.l r0,@r1 + + mov.l SDR4_A,r1 + mov.l SDR4_D,r0 + mov.l r0,@r1 + + mov.l MIMC_A,r1 + mov.l MIMC_D2,r0 + mov.l r0,@r1 + + nop + nop + nop + + mov.l SCR4_A,r1 + mov.l SCR4_D3,r0 + mov.l r0,@r1 + + mov.l SCR4_A,r1 + mov.l SCR4_D2,r0 + mov.l r0,@r1 + + mov.l SDMR02000_A,r1 + mov.l SDMR02000_D,r0 + mov.l r0,@r1 + + mov.l SDMR00B08_A,r1 + mov.l SDMR00B08_D,r0 + mov.l r0,@r1 + + mov.l SCR4_A,r1 + mov.l SCR4_D2,r0 + mov.l r0,@r1 + + mov.l SCR4_A,r1 + mov.l SCR4_D4,r0 + mov.l r0,@r1 + + nop + nop + nop + nop + + mov.l SCR4_A,r1 + mov.l SCR4_D4,r0 + mov.l r0,@r1 + + nop + nop + nop + nop + + mov.l SDMR00308_A,r1 + mov.l SDMR00308_D,r0 + mov.l r0,@r1 + + mov.l MIMC_A,r1 + mov.l MIMC_D3,r0 + mov.l r0,@r1 + + mov.l SCR4_A,r1 + mov.l SCR4_D1,r0 + mov.l DELAY60_D,r3 + +delay_loop_60: + mov.l r0,@r1 + dt r3 + bf delay_loop_60 + nop + + mov.l CCR_A, r1 /* Address of Cache Control Register */ + mov.l CCR_CACHE_D_2, r0 + mov.l r0, @r1 + +bsc_init: + mov.l BCR_A, r1 + mov.l BCR_D, r0 + mov.l r0, @r1 + + mov.l CS0BCR_A, r1 + mov.l CS0BCR_D, r0 + mov.l r0, @r1 + + mov.l CS1BCR_A,r1 + mov.l CS1BCR_D,r0 + mov.l r0,@r1 + + mov.l CS2BCR_A, r1 + mov.l CS2BCR_D, r0 + mov.l r0, @r1 + + mov.l CS4BCR_A, r1 + mov.l CS4BCR_D, r0 + mov.l r0, @r1 + + mov.l CS5BCR_A, r1 + mov.l CS5BCR_D, r0 + mov.l r0, @r1 + + mov.l CS6BCR_A, r1 + mov.l CS6BCR_D, r0 + mov.l r0, @r1 + + mov.l CS0WCR_A, r1 + mov.l CS0WCR_D, r0 + mov.l r0, @r1 + + mov.l CS1WCR_A, r1 + mov.l CS1WCR_D, r0 + mov.l r0, @r1 + + mov.l CS2WCR_A, r1 + mov.l CS2WCR_D, r0 + mov.l r0, @r1 + + mov.l CS4WCR_A, r1 + mov.l CS4WCR_D, r0 + mov.l r0, @r1 + + mov.l CS5WCR_A, r1 + mov.l CS5WCR_D, r0 + mov.l r0, @r1 + + mov.l CS6WCR_A, r1 + mov.l CS6WCR_D, r0 + mov.l r0, @r1 + + mov.l CS5PCR_A, r1 + mov.l CS5PCR_D, r0 + mov.l r0, @r1 + + mov.l CS6PCR_A, r1 + mov.l CS6PCR_D, r0 + mov.l r0, @r1 + + mov.l DELAY200_D,r3 + +delay_loop_200: + dt r3 + bf delay_loop_200 + nop + + mov.l PSEL0_A,r1 + mov.l PSEL0_D,r0 + mov.w r0,@r1 + + mov.l PSEL1_A,r1 + mov.l PSEL1_D,r0 + mov.w r0,@r1 + + mov.l ICR0_A,r1 + mov.l ICR0_D,r0 + mov.l r0,@r1 + + stc sr, r0 /* BL bit off(init=ON) */ + mov.l SR_MASK_D, r1 + and r1, r0 + ldc r0, sr + + rts + nop + + .align 2 + +DELAY60_D: .long 60 +DELAY200_D: .long 17800 + +CCR_A: .long 0xFF00001C +MMUCR_A: .long 0xFF000010 +RAMCR_A: .long 0xFF000074 + +/* Low power mode control */ +MSTPCR0_A: .long 0xFFC80030 +MSTPCR1_A: .long 0xFFC80038 + +/* RWBT */ +WDTST_A: .long 0xFFCC0000 +WDTCSR_A: .long 0xFFCC0004 +WDTBST_A: .long 0xFFCC0008 + +/* BSC */ +MMSELR_A: .long 0xFE600020 +BCR_A: .long 0xFF801000 +CS0BCR_A: .long 0xFF802000 +CS1BCR_A: .long 0xFF802010 +CS2BCR_A: .long 0xFF802020 +CS4BCR_A: .long 0xFF802040 +CS5BCR_A: .long 0xFF802050 +CS6BCR_A: .long 0xFF802060 +CS0WCR_A: .long 0xFF802008 +CS1WCR_A: .long 0xFF802018 +CS2WCR_A: .long 0xFF802028 +CS4WCR_A: .long 0xFF802048 +CS5WCR_A: .long 0xFF802058 +CS6WCR_A: .long 0xFF802068 +CS5PCR_A: .long 0xFF802070 +CS6PCR_A: .long 0xFF802080 +DDRSD_START_A: .long 0xAC000000 + +/* INTC */ +ICR0_A: .long 0xFFD00000 + +/* DDR I/F */ +MIM8_A: .long 0xFE800008 +MIMC_A: .long 0xFE80000C +SCR4_A: .long 0xFE800014 +STRC_A: .long 0xFE80001C +SDR4_A: .long 0xFE800034 +SDMR00308_A: .long 0xFE900308 +SDMR00B08_A: .long 0xFE900B08 +SDMR02000_A: .long 0xFE902000 + +/* GPIO */ +PSEL0_A: .long 0xFFEF0070 +PSEL1_A: .long 0xFFEF0072 + +CCR_CACHE_ICI_D:.long 0x00000800 +CCR_CACHE_D_2: .long 0x00000103 +MMU_CONTROL_TI_D:.long 0x00000004 +RAMCR_D: .long 0x00000200 +MSTPCR0_D: .long 0x00000000 +MSTPCR1_D: .long 0x00000000 + +MMSELR_D: .long 0xa5a50000 +BCR_D: .long 0x00000000 +CS0BCR_D: .long 0x77777770 +CS1BCR_D: .long 0x77777670 +CS2BCR_D: .long 0x77777670 +CS4BCR_D: .long 0x77777670 +CS5BCR_D: .long 0x77777670 +CS6BCR_D: .long 0x77777670 +CS0WCR_D: .long 0x7777770F +CS1WCR_D: .long 0x22000002 +CS2WCR_D: .long 0x7777770F +CS4WCR_D: .long 0x7777770F +CS5WCR_D: .long 0x7777770F +CS6WCR_D: .long 0x7777770F +CS5PCR_D: .long 0x77000000 +CS6PCR_D: .long 0x77000000 +ICR0_D: .long 0x00E00000 +MIM8_D: .long 0x00000000 +MIMC_D1: .long 0x01d10008 +MIMC_D2: .long 0x01d10009 +MIMC_D3: .long 0x01d10209 +SCR4_D1: .long 0x00000001 +SCR4_D2: .long 0x00000002 +SCR4_D3: .long 0x00000003 +SCR4_D4: .long 0x00000004 +STRC_D: .long 0x000f3980 +SDR4_D: .long 0x00000300 +SDMR00308_D: .long 0x00000000 +SDMR00B08_D: .long 0x00000000 +SDMR02000_D: .long 0x00000000 +PSEL0_D: .long 0x00000001 +PSEL1_D: .long 0x00000244 +SR_MASK_D: .long 0xEFFFFF0F +WDTST_D: .long 0x5A000FFF +WDTCSR_D: .long 0xA5000000 +WDTBST_D: .long 0x55000000 diff --git a/board/renesas/sh7763rdp/sh7763rdp.c b/board/renesas/sh7763rdp/sh7763rdp.c new file mode 100644 index 0000000000..88bab70e35 --- /dev/null +++ b/board/renesas/sh7763rdp/sh7763rdp.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu + * Copyright (C) 2007 Kenati Technologies, Inc. + * + * board/sh7763rdp/sh7763rdp.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define CPU_CMDREG 0xB1000006 +#define PDCR 0xffef0006 +#define PECR 0xffef0008 +#define PFCR 0xffef000a +#define PGCR 0xffef000c +#define PHCR 0xffef000e +#define PJCR 0xffef0012 +#define PKCR 0xffef0014 +#define PLCR 0xffef0016 +#define PMCR 0xffef0018 +#define PSEL1 0xffef0072 +#define PSEL2 0xffef0074 +#define PSEL3 0xffef0076 + +int checkboard(void) +{ + puts("BOARD: Renesas SH7763 RDP\n"); + return 0; +} + +int board_init(void) +{ + vu_short dat; + + /* Enable mode */ + writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG); + + /* GPIO Setting (eth1) */ + dat = inw(PSEL1); + writew(((dat & ~0xff00) | 0x2400), PSEL1); + writew(0, PFCR); + writew(0, PGCR); + writew(0, PHCR); + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state(unsigned short value) +{ +} diff --git a/board/renesas/sh7763rdp/u-boot.lds b/board/renesas/sh7763rdp/u-boot.lds new file mode 100644 index 0000000000..7177416c2f --- /dev/null +++ b/board/renesas/sh7763rdp/u-boot.lds @@ -0,0 +1,105 @@ +/* + * Copyrigth (c) 2007,2008 + * Nobuhiro Iwamatsu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x0C000000. + Although size of SDRAM can be either 16 or 32 MBytes, + we assume 16 MBytes (ie ignore upper half if the full + 32 MBytes is present). + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x8C000000 + (64*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/board/sh7763rdp/Makefile b/board/sh7763rdp/Makefile deleted file mode 100644 index 62a683d57f..0000000000 --- a/board/sh7763rdp/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# Copyright (C) 2008 Renesas Solutions Corp. -# Copyright (C) 2008 Nobuhiro Iwamatsu -# Copyright (C) 2007 Kenati Technologies, Inc. -# -# board/sh7763rdp/Makefile -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := sh7763rdp.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/sh7763rdp/config.mk b/board/sh7763rdp/config.mk deleted file mode 100644 index c52dbfd7b0..0000000000 --- a/board/sh7763rdp/config.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# board/sh7763rdp/config.mk -# -# TEXT_BASE refers to image _after_ relocation. -# -# NOTE: Must match value used in u-boot.lds (in this directory). -# - -TEXT_BASE = 0x8FFC0000 - -# PLATFORM_CPPFLAGS += -DCONFIG_MULTIBOOT diff --git a/board/sh7763rdp/lowlevel_init.S b/board/sh7763rdp/lowlevel_init.S deleted file mode 100644 index 2a44eee1ad..0000000000 --- a/board/sh7763rdp/lowlevel_init.S +++ /dev/null @@ -1,350 +0,0 @@ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * Copyright (C) 2007 Kenati Technologies, Inc. - * - * board/sh7763rdp/lowlevel_init.S - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#include - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */ - mov.l WDTCSR_D, r0 - mov.l r0, @r1 - - mov.l WDTST_A, r1 /* Watchdog Stop Time Register */ - mov.l WDTST_D, r0 - mov.l r0, @r1 - - mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */ - mov.l WDTBST_D, r0 - mov.l r0, @r1 - - mov.l CCR_A, r1 /* Address of Cache Control Register */ - mov.l CCR_CACHE_ICI_D, r0 /* Instruction Cache Invalidate */ - mov.l r0, @r1 - - mov.l MMUCR_A, r1 /* Address of MMU Control Register */ - mov.l MMU_CONTROL_TI_D, r0 /* TI == TLB Invalidate bit */ - mov.l r0, @r1 - - mov.l MSTPCR0_A, r1 /* Address of Power Control Register 0 */ - mov.l MSTPCR0_D, r0 - mov.l r0, @r1 - - mov.l MSTPCR1_A, r1 /*i Address of Power Control Register 1 */ - mov.l MSTPCR1_D, r0 - mov.l r0, @r1 - - mov.l RAMCR_A,r1 - mov.l RAMCR_D,r0 - mov.l r0, @r1 - - mov.l MMSELR_A,r1 - mov.l MMSELR_D,r0 - synco - mov.l r0, @r1 - - mov.l @r1,r2 /* execute two reads after setting MMSELR*/ - mov.l @r1,r2 - synco - - /* issue memory read */ - mov.l DDRSD_START_A,r1 /* memory address to read*/ - mov.l @r1,r0 - synco - - mov.l MIM8_A,r1 - mov.l MIM8_D,r0 - mov.l r0,@r1 - - mov.l MIMC_A,r1 - mov.l MIMC_D1,r0 - mov.l r0,@r1 - - mov.l STRC_A,r1 - mov.l STRC_D,r0 - mov.l r0,@r1 - - mov.l SDR4_A,r1 - mov.l SDR4_D,r0 - mov.l r0,@r1 - - mov.l MIMC_A,r1 - mov.l MIMC_D2,r0 - mov.l r0,@r1 - - nop - nop - nop - - mov.l SCR4_A,r1 - mov.l SCR4_D3,r0 - mov.l r0,@r1 - - mov.l SCR4_A,r1 - mov.l SCR4_D2,r0 - mov.l r0,@r1 - - mov.l SDMR02000_A,r1 - mov.l SDMR02000_D,r0 - mov.l r0,@r1 - - mov.l SDMR00B08_A,r1 - mov.l SDMR00B08_D,r0 - mov.l r0,@r1 - - mov.l SCR4_A,r1 - mov.l SCR4_D2,r0 - mov.l r0,@r1 - - mov.l SCR4_A,r1 - mov.l SCR4_D4,r0 - mov.l r0,@r1 - - nop - nop - nop - nop - - mov.l SCR4_A,r1 - mov.l SCR4_D4,r0 - mov.l r0,@r1 - - nop - nop - nop - nop - - mov.l SDMR00308_A,r1 - mov.l SDMR00308_D,r0 - mov.l r0,@r1 - - mov.l MIMC_A,r1 - mov.l MIMC_D3,r0 - mov.l r0,@r1 - - mov.l SCR4_A,r1 - mov.l SCR4_D1,r0 - mov.l DELAY60_D,r3 - -delay_loop_60: - mov.l r0,@r1 - dt r3 - bf delay_loop_60 - nop - - mov.l CCR_A, r1 /* Address of Cache Control Register */ - mov.l CCR_CACHE_D_2, r0 - mov.l r0, @r1 - -bsc_init: - mov.l BCR_A, r1 - mov.l BCR_D, r0 - mov.l r0, @r1 - - mov.l CS0BCR_A, r1 - mov.l CS0BCR_D, r0 - mov.l r0, @r1 - - mov.l CS1BCR_A,r1 - mov.l CS1BCR_D,r0 - mov.l r0,@r1 - - mov.l CS2BCR_A, r1 - mov.l CS2BCR_D, r0 - mov.l r0, @r1 - - mov.l CS4BCR_A, r1 - mov.l CS4BCR_D, r0 - mov.l r0, @r1 - - mov.l CS5BCR_A, r1 - mov.l CS5BCR_D, r0 - mov.l r0, @r1 - - mov.l CS6BCR_A, r1 - mov.l CS6BCR_D, r0 - mov.l r0, @r1 - - mov.l CS0WCR_A, r1 - mov.l CS0WCR_D, r0 - mov.l r0, @r1 - - mov.l CS1WCR_A, r1 - mov.l CS1WCR_D, r0 - mov.l r0, @r1 - - mov.l CS2WCR_A, r1 - mov.l CS2WCR_D, r0 - mov.l r0, @r1 - - mov.l CS4WCR_A, r1 - mov.l CS4WCR_D, r0 - mov.l r0, @r1 - - mov.l CS5WCR_A, r1 - mov.l CS5WCR_D, r0 - mov.l r0, @r1 - - mov.l CS6WCR_A, r1 - mov.l CS6WCR_D, r0 - mov.l r0, @r1 - - mov.l CS5PCR_A, r1 - mov.l CS5PCR_D, r0 - mov.l r0, @r1 - - mov.l CS6PCR_A, r1 - mov.l CS6PCR_D, r0 - mov.l r0, @r1 - - mov.l DELAY200_D,r3 - -delay_loop_200: - dt r3 - bf delay_loop_200 - nop - - mov.l PSEL0_A,r1 - mov.l PSEL0_D,r0 - mov.w r0,@r1 - - mov.l PSEL1_A,r1 - mov.l PSEL1_D,r0 - mov.w r0,@r1 - - mov.l ICR0_A,r1 - mov.l ICR0_D,r0 - mov.l r0,@r1 - - stc sr, r0 /* BL bit off(init=ON) */ - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - nop - - .align 2 - -DELAY60_D: .long 60 -DELAY200_D: .long 17800 - -CCR_A: .long 0xFF00001C -MMUCR_A: .long 0xFF000010 -RAMCR_A: .long 0xFF000074 - -/* Low power mode control */ -MSTPCR0_A: .long 0xFFC80030 -MSTPCR1_A: .long 0xFFC80038 - -/* RWBT */ -WDTST_A: .long 0xFFCC0000 -WDTCSR_A: .long 0xFFCC0004 -WDTBST_A: .long 0xFFCC0008 - -/* BSC */ -MMSELR_A: .long 0xFE600020 -BCR_A: .long 0xFF801000 -CS0BCR_A: .long 0xFF802000 -CS1BCR_A: .long 0xFF802010 -CS2BCR_A: .long 0xFF802020 -CS4BCR_A: .long 0xFF802040 -CS5BCR_A: .long 0xFF802050 -CS6BCR_A: .long 0xFF802060 -CS0WCR_A: .long 0xFF802008 -CS1WCR_A: .long 0xFF802018 -CS2WCR_A: .long 0xFF802028 -CS4WCR_A: .long 0xFF802048 -CS5WCR_A: .long 0xFF802058 -CS6WCR_A: .long 0xFF802068 -CS5PCR_A: .long 0xFF802070 -CS6PCR_A: .long 0xFF802080 -DDRSD_START_A: .long 0xAC000000 - -/* INTC */ -ICR0_A: .long 0xFFD00000 - -/* DDR I/F */ -MIM8_A: .long 0xFE800008 -MIMC_A: .long 0xFE80000C -SCR4_A: .long 0xFE800014 -STRC_A: .long 0xFE80001C -SDR4_A: .long 0xFE800034 -SDMR00308_A: .long 0xFE900308 -SDMR00B08_A: .long 0xFE900B08 -SDMR02000_A: .long 0xFE902000 - -/* GPIO */ -PSEL0_A: .long 0xFFEF0070 -PSEL1_A: .long 0xFFEF0072 - -CCR_CACHE_ICI_D:.long 0x00000800 -CCR_CACHE_D_2: .long 0x00000103 -MMU_CONTROL_TI_D:.long 0x00000004 -RAMCR_D: .long 0x00000200 -MSTPCR0_D: .long 0x00000000 -MSTPCR1_D: .long 0x00000000 - -MMSELR_D: .long 0xa5a50000 -BCR_D: .long 0x00000000 -CS0BCR_D: .long 0x77777770 -CS1BCR_D: .long 0x77777670 -CS2BCR_D: .long 0x77777670 -CS4BCR_D: .long 0x77777670 -CS5BCR_D: .long 0x77777670 -CS6BCR_D: .long 0x77777670 -CS0WCR_D: .long 0x7777770F -CS1WCR_D: .long 0x22000002 -CS2WCR_D: .long 0x7777770F -CS4WCR_D: .long 0x7777770F -CS5WCR_D: .long 0x7777770F -CS6WCR_D: .long 0x7777770F -CS5PCR_D: .long 0x77000000 -CS6PCR_D: .long 0x77000000 -ICR0_D: .long 0x00E00000 -MIM8_D: .long 0x00000000 -MIMC_D1: .long 0x01d10008 -MIMC_D2: .long 0x01d10009 -MIMC_D3: .long 0x01d10209 -SCR4_D1: .long 0x00000001 -SCR4_D2: .long 0x00000002 -SCR4_D3: .long 0x00000003 -SCR4_D4: .long 0x00000004 -STRC_D: .long 0x000f3980 -SDR4_D: .long 0x00000300 -SDMR00308_D: .long 0x00000000 -SDMR00B08_D: .long 0x00000000 -SDMR02000_D: .long 0x00000000 -PSEL0_D: .long 0x00000001 -PSEL1_D: .long 0x00000244 -SR_MASK_D: .long 0xEFFFFF0F -WDTST_D: .long 0x5A000FFF -WDTCSR_D: .long 0xA5000000 -WDTBST_D: .long 0x55000000 diff --git a/board/sh7763rdp/sh7763rdp.c b/board/sh7763rdp/sh7763rdp.c deleted file mode 100644 index 88bab70e35..0000000000 --- a/board/sh7763rdp/sh7763rdp.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * Copyright (C) 2007 Kenati Technologies, Inc. - * - * board/sh7763rdp/sh7763rdp.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define CPU_CMDREG 0xB1000006 -#define PDCR 0xffef0006 -#define PECR 0xffef0008 -#define PFCR 0xffef000a -#define PGCR 0xffef000c -#define PHCR 0xffef000e -#define PJCR 0xffef0012 -#define PKCR 0xffef0014 -#define PLCR 0xffef0016 -#define PMCR 0xffef0018 -#define PSEL1 0xffef0072 -#define PSEL2 0xffef0074 -#define PSEL3 0xffef0076 - -int checkboard(void) -{ - puts("BOARD: Renesas SH7763 RDP\n"); - return 0; -} - -int board_init(void) -{ - vu_short dat; - - /* Enable mode */ - writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG); - - /* GPIO Setting (eth1) */ - dat = inw(PSEL1); - writew(((dat & ~0xff00) | 0x2400), PSEL1); - writew(0, PFCR); - writew(0, PGCR); - writew(0, PHCR); - - return 0; -} - -int dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -void led_set_state(unsigned short value) -{ -} diff --git a/board/sh7763rdp/u-boot.lds b/board/sh7763rdp/u-boot.lds deleted file mode 100644 index 7177416c2f..0000000000 --- a/board/sh7763rdp/u-boot.lds +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyrigth (c) 2007,2008 - * Nobuhiro Iwamatsu - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - Base address of internal SDRAM is 0x0C000000. - Although size of SDRAM can be either 16 or 32 MBytes, - we assume 16 MBytes (ie ignore upper half if the full - 32 MBytes is present). - - NOTE: This address must match with the definition of - TEXT_BASE in config.mk (in this directory). - - */ - . = 0x8C000000 + (64*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - cpu/sh4/start.o (.text) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(.rodata) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); - } - PROVIDE (__u_boot_cmd_end = .); - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (_end = .); -} -- cgit v1.2.1 From c1da2a22817ba85b437afa2f4e715e658b219fd1 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 24 Oct 2008 10:39:44 +0900 Subject: sh: r2dplus: Moved r2dplus board to board/renesas Signed-off-by: Nobuhiro Iwamatsu --- board/r2dplus/Makefile | 47 ----------- board/r2dplus/config.mk | 23 ----- board/r2dplus/lowlevel_init.S | 154 ---------------------------------- board/r2dplus/r2dplus.c | 84 ------------------- board/r2dplus/u-boot.lds | 105 ----------------------- board/renesas/r2dplus/Makefile | 47 +++++++++++ board/renesas/r2dplus/config.mk | 23 +++++ board/renesas/r2dplus/lowlevel_init.S | 154 ++++++++++++++++++++++++++++++++++ board/renesas/r2dplus/r2dplus.c | 84 +++++++++++++++++++ board/renesas/r2dplus/u-boot.lds | 105 +++++++++++++++++++++++ 10 files changed, 413 insertions(+), 413 deletions(-) delete mode 100644 board/r2dplus/Makefile delete mode 100644 board/r2dplus/config.mk delete mode 100644 board/r2dplus/lowlevel_init.S delete mode 100644 board/r2dplus/r2dplus.c delete mode 100644 board/r2dplus/u-boot.lds create mode 100644 board/renesas/r2dplus/Makefile create mode 100644 board/renesas/r2dplus/config.mk create mode 100644 board/renesas/r2dplus/lowlevel_init.S create mode 100644 board/renesas/r2dplus/r2dplus.c create mode 100644 board/renesas/r2dplus/u-boot.lds (limited to 'board') diff --git a/board/r2dplus/Makefile b/board/r2dplus/Makefile deleted file mode 100644 index e96a8aa986..0000000000 --- a/board/r2dplus/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# Copyright (C) 2007,2008 -# Nobuhiro Iwamatsu -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := r2dplus.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/r2dplus/config.mk b/board/r2dplus/config.mk deleted file mode 100644 index 1ec7dcc605..0000000000 --- a/board/r2dplus/config.mk +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (C) 2007,2008 -# Nobuhiro Iwamatsu -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# -# NOTE: Must match value used in u-boot.lds (in this directory). -# -TEXT_BASE = 0x0FFC0000 diff --git a/board/r2dplus/lowlevel_init.S b/board/r2dplus/lowlevel_init.S deleted file mode 100644 index 5755de87b9..0000000000 --- a/board/r2dplus/lowlevel_init.S +++ /dev/null @@ -1,154 +0,0 @@ -/* - * modified from SH-IPL+g (init-r0p751rlc0011rl.S) - * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz) - * Coyright (c) 2007,2008 Nobuhiro Iwamatsu -*/ - -#include -#include - -#include - - .global lowlevel_init - .text - .align 2 - -lowlevel_init: - - mov.l CCR_A, r1 - mov.l CCR_D_D, r0 - mov.l r0,@r1 - - mov.l MMUCR_A,r1 - mov.l MMUCR_D,r0 - mov.w r0,@r1 - - mov.l BCR1_A,r1 - mov.l BCR1_D,r0 - mov.l r0,@r1 - - mov.l BCR2_A,r1 - mov.l BCR2_D,r0 - mov.w r0,@r1 - - mov.l BCR3_A,r1 - mov.l BCR3_D,r0 - mov.w r0,@r1 - - mov.l BCR4_A,r1 - mov.l BCR4_D,r0 - mov.l r0,@r1 - - mov.l WCR1_A,r1 - mov.l WCR1_D,r0 - mov.l r0,@r1 - - mov.l WCR2_A,r1 - mov.l WCR2_D,r0 - mov.l r0,@r1 - - mov.l WCR3_A,r1 - mov.l WCR3_D,r0 - mov.l r0,@r1 - - mov.l PCR_A,r1 - mov.l PCR_D,r0 - mov.w r0,@r1 - - mov.l LED_A,r1 - mov #0xff,r0 - mov.w r0,@r1 - - mov.l MCR_A,r1 - mov.l MCR_D1,r0 - mov.l r0,@r1 - - mov.l RTCNT_A,r1 - mov.l RTCNT_D,r0 - mov.w r0,@r1 - - mov.l RTCOR_A,r1 - mov.l RTCOR_D,r0 - mov.w r0,@r1 - - mov.l RFCR_A,r1 - mov.l RFCR_D,r0 - mov.w r0,@r1 - - mov.l RTCSR_A,r1 - mov.l RTCSR_D,r0 - mov.w r0,@r1 - - mov.l SDMR3_A,r1 - mov #0x55,r0 - mov.b r0,@r1 - - /* Wait DRAM refresh 30 times */ - mov.l RFCR_A,r1 - mov #30,r3 -1: - mov.w @r1,r0 - extu.w r0,r2 - cmp/hi r3,r2 - bf 1b - - mov.l MCR_A,r1 - mov.l MCR_D2,r0 - mov.l r0,@r1 - - mov.l SDMR3_A,r1 - mov #0,r0 - mov.b r0,@r1 - - mov.l IRLMASK_A,r1 - mov.l IRLMASK_D,r0 - mov.l r0,@r1 - - mov.l CCR_A, r1 - mov.l CCR_D_E, r0 - mov.l r0, @r1 - - rts - nop - - .align 2 -CCR_A: .long CCR /* Cache Control Register */ -CCR_D_D: .long 0x0808 /* Flush the cache, disable */ -CCR_D_E: .long 0x8000090B - -FRQCR_A: .long FRQCR /* FRQCR Address */ -FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */ -BCR1_A: .long BCR1 /* BCR1 Address */ -BCR1_D: .long 0x00180008 -BCR2_A: .long BCR2 /* BCR2 Address */ -BCR2_D: .long 0xabe8 -BCR3_A: .long BCR3 /* BCR3 Address */ -BCR3_D: .long 0x0000 -BCR4_A: .long BCR4 /* BCR4 Address */ -BCR4_D: .long 0x00000010 -WCR1_A: .long WCR1 /* WCR1 Address */ -WCR1_D: .long 0x33343333 -WCR2_A: .long WCR2 /* WCR2 Address */ -WCR2_D: .long 0xcff86fbf -WCR3_A: .long WCR3 /* WCR3 Address */ -WCR3_D: .long 0x07777707 -LED_A: .long 0x04000036 /* LED Address */ -RTCNT_A: .long RTCNT /* RTCNT Address */ -RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ -RTCOR_A: .long RTCOR /* RTCOR Address */ -RTCOR_D: .long 0xA534 /* RTCOR Write Code */ -RTCSR_A: .long RTCSR /* RTCSR Address */ -RTCSR_D: .long 0xA510 /* RTCSR Write Code */ -SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ -SDMR3_D: .long 0x55 -MCR_A: .long MCR /* MCR Address */ -MCR_D1: .long 0x081901F4 /* MRSET:'0' */ -MCR_D2: .long 0x481901F4 /* MRSET:'1' */ -RFCR_A: .long RFCR /* RFCR Address */ -RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ -PCR_A: .long PCR /* PCR Address */ -PCR_D: .long 0x0000 -MMUCR_A: .long MMUCR /* MMUCCR Address */ -MMUCR_D: .long 0x00000000 /* MMUCCR Data */ -IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */ -IRLMASK_D: .long 0x00000000 /* IRLMASK Data */ diff --git a/board/r2dplus/r2dplus.c b/board/r2dplus/r2dplus.c deleted file mode 100644 index 0c08d68594..0000000000 --- a/board/r2dplus/r2dplus.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (C) 2007,2008 - * Nobuhiro Iwamatsu - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -int checkboard(void) -{ - puts("BOARD: Renesas Solutions R2D Plus\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -int dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -int board_late_init(void) -{ - return 0; -} - -#define FPGA_BASE 0xA4000000 -#define FPGA_CFCTL (FPGA_BASE + 0x04) -#define CFCTL_EN (0x432) -#define FPGA_CFPOW (FPGA_BASE + 0x06) -#define CFPOW_ON (0x02) -#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A) -#define CFCDINTCLR_EN (0x01) - -void ide_set_reset(int idereset) -{ - /* if reset = 1 IDE reset will be asserted */ - if (idereset) { - outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */ - outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */ - outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */ - } -} - -static struct pci_controller hose; -void pci_init_board(void) -{ - pci_sh7751_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/r2dplus/u-boot.lds b/board/r2dplus/u-boot.lds deleted file mode 100644 index 040e530179..0000000000 --- a/board/r2dplus/u-boot.lds +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyrigth (c) 2007,2008 - * Nobuhiro Iwamatsu - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - Base address of internal SDRAM is 0x0C000000. - Although size of SDRAM can be either 16 or 32 MBytes, - we assume 16 MBytes (ie ignore upper half if the full - 32 MBytes is present). - - NOTE: This address must match with the definition of - TEXT_BASE in config.mk (in this directory). - - */ - . = 0x0C000000 + (64*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - cpu/sh4/start.o (.text) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(.rodata) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); - } - PROVIDE (__u_boot_cmd_end = .); - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (_end = .); -} diff --git a/board/renesas/r2dplus/Makefile b/board/renesas/r2dplus/Makefile new file mode 100644 index 0000000000..e96a8aa986 --- /dev/null +++ b/board/renesas/r2dplus/Makefile @@ -0,0 +1,47 @@ +# +# Copyright (C) 2007,2008 +# Nobuhiro Iwamatsu +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := r2dplus.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/renesas/r2dplus/config.mk b/board/renesas/r2dplus/config.mk new file mode 100644 index 0000000000..1ec7dcc605 --- /dev/null +++ b/board/renesas/r2dplus/config.mk @@ -0,0 +1,23 @@ +# +# Copyright (C) 2007,2008 +# Nobuhiro Iwamatsu +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# +TEXT_BASE = 0x0FFC0000 diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S new file mode 100644 index 0000000000..5755de87b9 --- /dev/null +++ b/board/renesas/r2dplus/lowlevel_init.S @@ -0,0 +1,154 @@ +/* + * modified from SH-IPL+g (init-r0p751rlc0011rl.S) + * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz) + * Coyright (c) 2007,2008 Nobuhiro Iwamatsu +*/ + +#include +#include + +#include + + .global lowlevel_init + .text + .align 2 + +lowlevel_init: + + mov.l CCR_A, r1 + mov.l CCR_D_D, r0 + mov.l r0,@r1 + + mov.l MMUCR_A,r1 + mov.l MMUCR_D,r0 + mov.w r0,@r1 + + mov.l BCR1_A,r1 + mov.l BCR1_D,r0 + mov.l r0,@r1 + + mov.l BCR2_A,r1 + mov.l BCR2_D,r0 + mov.w r0,@r1 + + mov.l BCR3_A,r1 + mov.l BCR3_D,r0 + mov.w r0,@r1 + + mov.l BCR4_A,r1 + mov.l BCR4_D,r0 + mov.l r0,@r1 + + mov.l WCR1_A,r1 + mov.l WCR1_D,r0 + mov.l r0,@r1 + + mov.l WCR2_A,r1 + mov.l WCR2_D,r0 + mov.l r0,@r1 + + mov.l WCR3_A,r1 + mov.l WCR3_D,r0 + mov.l r0,@r1 + + mov.l PCR_A,r1 + mov.l PCR_D,r0 + mov.w r0,@r1 + + mov.l LED_A,r1 + mov #0xff,r0 + mov.w r0,@r1 + + mov.l MCR_A,r1 + mov.l MCR_D1,r0 + mov.l r0,@r1 + + mov.l RTCNT_A,r1 + mov.l RTCNT_D,r0 + mov.w r0,@r1 + + mov.l RTCOR_A,r1 + mov.l RTCOR_D,r0 + mov.w r0,@r1 + + mov.l RFCR_A,r1 + mov.l RFCR_D,r0 + mov.w r0,@r1 + + mov.l RTCSR_A,r1 + mov.l RTCSR_D,r0 + mov.w r0,@r1 + + mov.l SDMR3_A,r1 + mov #0x55,r0 + mov.b r0,@r1 + + /* Wait DRAM refresh 30 times */ + mov.l RFCR_A,r1 + mov #30,r3 +1: + mov.w @r1,r0 + extu.w r0,r2 + cmp/hi r3,r2 + bf 1b + + mov.l MCR_A,r1 + mov.l MCR_D2,r0 + mov.l r0,@r1 + + mov.l SDMR3_A,r1 + mov #0,r0 + mov.b r0,@r1 + + mov.l IRLMASK_A,r1 + mov.l IRLMASK_D,r0 + mov.l r0,@r1 + + mov.l CCR_A, r1 + mov.l CCR_D_E, r0 + mov.l r0, @r1 + + rts + nop + + .align 2 +CCR_A: .long CCR /* Cache Control Register */ +CCR_D_D: .long 0x0808 /* Flush the cache, disable */ +CCR_D_E: .long 0x8000090B + +FRQCR_A: .long FRQCR /* FRQCR Address */ +FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */ +BCR1_A: .long BCR1 /* BCR1 Address */ +BCR1_D: .long 0x00180008 +BCR2_A: .long BCR2 /* BCR2 Address */ +BCR2_D: .long 0xabe8 +BCR3_A: .long BCR3 /* BCR3 Address */ +BCR3_D: .long 0x0000 +BCR4_A: .long BCR4 /* BCR4 Address */ +BCR4_D: .long 0x00000010 +WCR1_A: .long WCR1 /* WCR1 Address */ +WCR1_D: .long 0x33343333 +WCR2_A: .long WCR2 /* WCR2 Address */ +WCR2_D: .long 0xcff86fbf +WCR3_A: .long WCR3 /* WCR3 Address */ +WCR3_D: .long 0x07777707 +LED_A: .long 0x04000036 /* LED Address */ +RTCNT_A: .long RTCNT /* RTCNT Address */ +RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ +RTCOR_A: .long RTCOR /* RTCOR Address */ +RTCOR_D: .long 0xA534 /* RTCOR Write Code */ +RTCSR_A: .long RTCSR /* RTCSR Address */ +RTCSR_D: .long 0xA510 /* RTCSR Write Code */ +SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ +SDMR3_D: .long 0x55 +MCR_A: .long MCR /* MCR Address */ +MCR_D1: .long 0x081901F4 /* MRSET:'0' */ +MCR_D2: .long 0x481901F4 /* MRSET:'1' */ +RFCR_A: .long RFCR /* RFCR Address */ +RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ +PCR_A: .long PCR /* PCR Address */ +PCR_D: .long 0x0000 +MMUCR_A: .long MMUCR /* MMUCCR Address */ +MMUCR_D: .long 0x00000000 /* MMUCCR Data */ +IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */ +IRLMASK_D: .long 0x00000000 /* IRLMASK Data */ diff --git a/board/renesas/r2dplus/r2dplus.c b/board/renesas/r2dplus/r2dplus.c new file mode 100644 index 0000000000..0c08d68594 --- /dev/null +++ b/board/renesas/r2dplus/r2dplus.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2007,2008 + * Nobuhiro Iwamatsu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +int checkboard(void) +{ + puts("BOARD: Renesas Solutions R2D Plus\n"); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +#define FPGA_BASE 0xA4000000 +#define FPGA_CFCTL (FPGA_BASE + 0x04) +#define CFCTL_EN (0x432) +#define FPGA_CFPOW (FPGA_BASE + 0x06) +#define CFPOW_ON (0x02) +#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A) +#define CFCDINTCLR_EN (0x01) + +void ide_set_reset(int idereset) +{ + /* if reset = 1 IDE reset will be asserted */ + if (idereset) { + outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */ + outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */ + outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */ + } +} + +static struct pci_controller hose; +void pci_init_board(void) +{ + pci_sh7751_init(&hose); +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/renesas/r2dplus/u-boot.lds b/board/renesas/r2dplus/u-boot.lds new file mode 100644 index 0000000000..040e530179 --- /dev/null +++ b/board/renesas/r2dplus/u-boot.lds @@ -0,0 +1,105 @@ +/* + * Copyrigth (c) 2007,2008 + * Nobuhiro Iwamatsu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x0C000000. + Although size of SDRAM can be either 16 or 32 MBytes, + we assume 16 MBytes (ie ignore upper half if the full + 32 MBytes is present). + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x0C000000 + (64*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} -- cgit v1.2.1 From 58453b00b3ebb26aaa901210023f99504a90bb00 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 24 Oct 2008 10:48:31 +0900 Subject: sh: MigoR: Moved MigoR board to board/renesas Signed-off-by: Nobuhiro Iwamatsu --- board/MigoR/Makefile | 52 ------- board/MigoR/config.mk | 31 ----- board/MigoR/lowlevel_init.S | 264 ------------------------------------ board/MigoR/migo_r.c | 53 -------- board/MigoR/u-boot.lds | 105 -------------- board/renesas/MigoR/Makefile | 52 +++++++ board/renesas/MigoR/config.mk | 31 +++++ board/renesas/MigoR/lowlevel_init.S | 264 ++++++++++++++++++++++++++++++++++++ board/renesas/MigoR/migo_r.c | 53 ++++++++ board/renesas/MigoR/u-boot.lds | 105 ++++++++++++++ 10 files changed, 505 insertions(+), 505 deletions(-) delete mode 100644 board/MigoR/Makefile delete mode 100644 board/MigoR/config.mk delete mode 100644 board/MigoR/lowlevel_init.S delete mode 100644 board/MigoR/migo_r.c delete mode 100644 board/MigoR/u-boot.lds create mode 100644 board/renesas/MigoR/Makefile create mode 100644 board/renesas/MigoR/config.mk create mode 100644 board/renesas/MigoR/lowlevel_init.S create mode 100644 board/renesas/MigoR/migo_r.c create mode 100644 board/renesas/MigoR/u-boot.lds (limited to 'board') diff --git a/board/MigoR/Makefile b/board/MigoR/Makefile deleted file mode 100644 index 661b59d005..0000000000 --- a/board/MigoR/Makefile +++ /dev/null @@ -1,52 +0,0 @@ -# -# Copyright (C) 2007 -# Nobuhiro Iwamatsu -# -# Copyright (C) 2007 -# Kenati Technologies, Inc. -# -# board/MigoR/Makefile -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := migo_r.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/MigoR/config.mk b/board/MigoR/config.mk deleted file mode 100644 index 2c5085a91f..0000000000 --- a/board/MigoR/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# Copyright (C) 2007 -# Nobuhiro Iwamatsu -# -# Copyright (C) 2007 -# Kenati Technologies, Inc. -# -# board/MigoR/config.mk -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -# -# TEXT_BASE refers to image _after_ relocation. -# -# NOTE: Must match value used in u-boot.lds (in this directory). -# - -TEXT_BASE = 0x8FFC0000 diff --git a/board/MigoR/lowlevel_init.S b/board/MigoR/lowlevel_init.S deleted file mode 100644 index e48f7b3b10..0000000000 --- a/board/MigoR/lowlevel_init.S +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (C) 2007 - * Nobuhiro Iwamatsu - * - * Copyright (C) 2007 - * Kenati Technologies, Inc. - * - * board/MigoR/lowlevel_init.S - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#include - -/* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. - * - * (Note: As no stack is available, no subroutines can be called...). - */ - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - mov.l CCR_A, r1 ! Address of Cache Control Register - mov.l CCR_D, r0 ! Instruction Cache Invalidate - mov.l r0, @r1 - - mov.l MMUCR_A, r1 ! Address of MMU Control Register - mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit - mov.l r0, @r1 - - mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0 - mov.l MSTPCR0_D, r0 ! - mov.l r0, @r1 - - mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2 - mov.l MSTPCR2_D, r0 ! - mov.l r0, @r1 - - mov.l PFC_PULCR_A, r1 - mov.w PFC_PULCR_D, r0 - mov.w r0,@r1 - - mov.l PFC_DRVCR_A, r1 - mov.w PFC_DRVCR_D, r0 - mov.w r0, @r1 - - mov.l SBSCR_A, r1 ! - mov.w SBSCR_D, r0 ! - mov.w r0, @r1 - - mov.l PSCR_A, r1 ! - mov.w PSCR_D, r0 ! - mov.w r0, @r1 - - mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) - mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max - mov.w r0, @r1 - - mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register) - mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear - mov.w r0, @r1 - - mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) - mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms - mov.w r0, @r1 - - mov.l DLLFRQ_A, r1 ! 20080115 - mov.l DLLFRQ_D, r0 ! 20080115 - mov.l r0, @r1 - - mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register - mov.l FRQCR_D, r0 ! 20080115 - mov.l r0, @r1 - - mov.l CCR_A, r1 ! Address of Cache Control Register - mov.l CCR_D_2, r0 ! ?? - mov.l r0, @r1 - -bsc_init: - mov.l CMNCR_A, r1 ! CMNCR address -> R1 - mov.l CMNCR_D, r0 ! CMNCR data -> R0 - mov.l r0, @r1 ! CMNCR set - - mov.l CS0BCR_A, r1 ! CS0BCR address -> R1 - mov.l CS0BCR_D, r0 ! CS0BCR data -> R0 - mov.l r0, @r1 ! CS0BCR set - - mov.l CS4BCR_A, r1 ! CS4BCR address -> R1 - mov.l CS4BCR_D, r0 ! CS4BCR data -> R0 - mov.l r0, @r1 ! CS4BCR set - - mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1 - mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0 - mov.l r0, @r1 ! CS5ABCR set - - mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1 - mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0 - mov.l r0, @r1 ! CS5BBCR set - - mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1 - mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0 - mov.l r0, @r1 ! CS6ABCR set - - mov.l CS0WCR_A, r1 ! CS0WCR address -> R1 - mov.l CS0WCR_D, r0 ! CS0WCR data -> R0 - mov.l r0, @r1 ! CS0WCR set - - mov.l CS4WCR_A, r1 ! CS4WCR address -> R1 - mov.l CS4WCR_D, r0 ! CS4WCR data -> R0 - mov.l r0, @r1 ! CS4WCR set - - mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1 - mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0 - mov.l r0, @r1 ! CS5AWCR set - - mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1 - mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0 - mov.l r0, @r1 ! CS5BWCR set - - mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1 - mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0 - mov.l r0, @r1 ! CS6AWCR set - - ! SDRAM initialization - mov.l SDCR_A, r1 ! SB_SDCR address -> R1 - mov.l SDCR_D, r0 ! SB_SDCR data -> R0 - mov.l r0, @r1 ! SB_SDCR set - - mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1 - mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0 - mov.l r0, @r1 ! SB_SDWCR set - - mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1 - mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0 - mov.l r0, @r1 ! SB_SDPCR set - - mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1 - mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0 - mov.l r0, @r1 ! SB_RTCOR set - - mov.l RTCNT_A, r1 ! SB_RTCNT address -> R1 - mov.l RTCNT_D, r0 ! SB_RTCNT data -> R0 - mov.l r0, @r1 - - mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1 - mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0 - mov.l r0, @r1 ! SB_RTCSR set - - mov.l RFCR_A, r1 ! SB_RFCR address -> R1 - mov.l RFCR_D, r0 ! SB_RFCR data -> R0 - mov.l r0, @r1 - - mov.l SDMR3_A, r1 ! SDMR3 address -> R1 - mov #0x00, r0 ! SDMR3 data -> R0 - mov.b r0, @r1 ! SDMR3 set - - ! BL bit off (init = ON) (?!?) - - stc sr, r0 ! BL bit off(init=ON) - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - mov #0, r0 - - .align 4 - -CCR_A: .long CCR -MMUCR_A: .long MMUCR -MSTPCR0_A: .long MSTPCR0 -MSTPCR2_A: .long MSTPCR2 -PFC_PULCR_A: .long PULCR -PFC_DRVCR_A: .long DRVCR -SBSCR_A: .long SBSCR -PSCR_A: .long PSCR -RWTCSR_A: .long RWTCSR -RWTCNT_A: .long RWTCNT -FRQCR_A: .long FRQCR -PLLCR_A: .long PLLCR -DLLFRQ_A: .long DLLFRQ - -CCR_D: .long 0x00000800 -CCR_D_2: .long 0x00000103 -MMUCR_D: .long 0x00000004 -MSTPCR0_D: .long 0x00001001 -MSTPCR2_D: .long 0xffffffff -PFC_PULCR_D: .long 0x6000 -PFC_DRVCR_D: .long 0x0464 -FRQCR_D: .long 0x07033639 -PLLCR_D: .long 0x00005000 -DLLFRQ_D: .long 0x000004F6 ! 20080115 - -CMNCR_A: .long CMNCR -CMNCR_D: .long 0x0000001B ! 20080115 -CS0BCR_A: .long CS0BCR ! Flash bank 1 -CS0BCR_D: .long 0x24920400 -CS4BCR_A: .long CS4BCR ! -CS4BCR_D: .long 0x10003400 ! 20080115 -CS5ABCR_A: .long CS5ABCR ! -CS5ABCR_D: .long 0x24920400 -CS5BBCR_A: .long CS5BBCR ! -CS5BBCR_D: .long 0x24920400 -CS6ABCR_A: .long CS6ABCR ! -CS6ABCR_D: .long 0x24920400 - -CS0WCR_A: .long CS0WCR -CS0WCR_D: .long 0x00000380 -CS4WCR_A: .long CS4WCR -CS4WCR_D: .long 0x00100A81 ! 20080115 -CS5AWCR_A: .long CS5AWCR -CS5AWCR_D: .long 0x00000300 -CS5BWCR_A: .long CS5BWCR -CS5BWCR_D: .long 0x00000300 -CS6AWCR_A: .long CS6AWCR -CS6AWCR_D: .long 0x00000300 - -SDCR_A: .long SBSC_SDCR -SDCR_D: .long 0x80160809 ! 20080115 -SDWCR_A: .long SBSC_SDWCR -SDWCR_D: .long 0x0014450C ! 20080115 -SDPCR_A: .long SBSC_SDPCR -SDPCR_D: .long 0x00000087 -RTCOR_A: .long SBSC_RTCOR -RTCNT_A: .long SBSC_RTCNT -RTCNT_D: .long 0xA55A0012 -RTCOR_D: .long 0xA55A001C ! 20080115 -RTCSR_A: .long SBSC_RTCSR -RFCR_A: .long SBSC_RFCR -RFCR_D: .long 0xA55A0221 -RTCSR_D: .long 0xA55A009a ! 20080115 -SDMR3_A: .long 0xFE581180 ! 20080115 - -SR_MASK_D: .long 0xEFFFFF0F - - .align 2 - -SBSCR_D: .word 0x0044 -PSCR_D: .word 0x0000 -RWTCSR_D_1: .word 0xA507 -RWTCSR_D_2: .word 0xA504 ! 20080115 -RWTCNT_D: .word 0x5A00 diff --git a/board/MigoR/migo_r.c b/board/MigoR/migo_r.c deleted file mode 100644 index 204ca78fa4..0000000000 --- a/board/MigoR/migo_r.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2007 - * Nobuhiro Iwamatsu - * - * Copyright (C) 2007 - * Kenati Technologies, Inc. - * - * board/MigoR/migo_r.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -int checkboard(void) -{ - puts("BOARD: Renesas MigoR\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -void led_set_state (unsigned short value) -{ -} diff --git a/board/MigoR/u-boot.lds b/board/MigoR/u-boot.lds deleted file mode 100644 index f9c1effa44..0000000000 --- a/board/MigoR/u-boot.lds +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyrigth (c) 2007 - * Nobuhiro Iwamatsu - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - Base address of internal SDRAM is 0x0C000000. - Although size of SDRAM can be either 16 or 32 MBytes, - we assume 16 MBytes (ie ignore upper half if the full - 32 MBytes is present). - - NOTE: This address must match with the definition of - TEXT_BASE in config.mk (in this directory). - - */ - . = 0x8C000000 + (64*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - cpu/sh4/start.o (.text) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(.rodata) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); - } - PROVIDE (__u_boot_cmd_end = .); - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (_end = .); -} diff --git a/board/renesas/MigoR/Makefile b/board/renesas/MigoR/Makefile new file mode 100644 index 0000000000..661b59d005 --- /dev/null +++ b/board/renesas/MigoR/Makefile @@ -0,0 +1,52 @@ +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu +# +# Copyright (C) 2007 +# Kenati Technologies, Inc. +# +# board/MigoR/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := migo_r.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/renesas/MigoR/config.mk b/board/renesas/MigoR/config.mk new file mode 100644 index 0000000000..2c5085a91f --- /dev/null +++ b/board/renesas/MigoR/config.mk @@ -0,0 +1,31 @@ +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu +# +# Copyright (C) 2007 +# Kenati Technologies, Inc. +# +# board/MigoR/config.mk +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# + +TEXT_BASE = 0x8FFC0000 diff --git a/board/renesas/MigoR/lowlevel_init.S b/board/renesas/MigoR/lowlevel_init.S new file mode 100644 index 0000000000..e48f7b3b10 --- /dev/null +++ b/board/renesas/MigoR/lowlevel_init.S @@ -0,0 +1,264 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu + * + * Copyright (C) 2007 + * Kenati Technologies, Inc. + * + * board/MigoR/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +/* + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. + * + * (Note: As no stack is available, no subroutines can be called...). + */ + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + mov.l CCR_A, r1 ! Address of Cache Control Register + mov.l CCR_D, r0 ! Instruction Cache Invalidate + mov.l r0, @r1 + + mov.l MMUCR_A, r1 ! Address of MMU Control Register + mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit + mov.l r0, @r1 + + mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0 + mov.l MSTPCR0_D, r0 ! + mov.l r0, @r1 + + mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2 + mov.l MSTPCR2_D, r0 ! + mov.l r0, @r1 + + mov.l PFC_PULCR_A, r1 + mov.w PFC_PULCR_D, r0 + mov.w r0,@r1 + + mov.l PFC_DRVCR_A, r1 + mov.w PFC_DRVCR_D, r0 + mov.w r0, @r1 + + mov.l SBSCR_A, r1 ! + mov.w SBSCR_D, r0 ! + mov.w r0, @r1 + + mov.l PSCR_A, r1 ! + mov.w PSCR_D, r0 ! + mov.w r0, @r1 + + mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) + mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max + mov.w r0, @r1 + + mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register) + mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear + mov.w r0, @r1 + + mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) + mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms + mov.w r0, @r1 + + mov.l DLLFRQ_A, r1 ! 20080115 + mov.l DLLFRQ_D, r0 ! 20080115 + mov.l r0, @r1 + + mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register + mov.l FRQCR_D, r0 ! 20080115 + mov.l r0, @r1 + + mov.l CCR_A, r1 ! Address of Cache Control Register + mov.l CCR_D_2, r0 ! ?? + mov.l r0, @r1 + +bsc_init: + mov.l CMNCR_A, r1 ! CMNCR address -> R1 + mov.l CMNCR_D, r0 ! CMNCR data -> R0 + mov.l r0, @r1 ! CMNCR set + + mov.l CS0BCR_A, r1 ! CS0BCR address -> R1 + mov.l CS0BCR_D, r0 ! CS0BCR data -> R0 + mov.l r0, @r1 ! CS0BCR set + + mov.l CS4BCR_A, r1 ! CS4BCR address -> R1 + mov.l CS4BCR_D, r0 ! CS4BCR data -> R0 + mov.l r0, @r1 ! CS4BCR set + + mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1 + mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0 + mov.l r0, @r1 ! CS5ABCR set + + mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1 + mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0 + mov.l r0, @r1 ! CS5BBCR set + + mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1 + mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0 + mov.l r0, @r1 ! CS6ABCR set + + mov.l CS0WCR_A, r1 ! CS0WCR address -> R1 + mov.l CS0WCR_D, r0 ! CS0WCR data -> R0 + mov.l r0, @r1 ! CS0WCR set + + mov.l CS4WCR_A, r1 ! CS4WCR address -> R1 + mov.l CS4WCR_D, r0 ! CS4WCR data -> R0 + mov.l r0, @r1 ! CS4WCR set + + mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1 + mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0 + mov.l r0, @r1 ! CS5AWCR set + + mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1 + mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0 + mov.l r0, @r1 ! CS5BWCR set + + mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1 + mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0 + mov.l r0, @r1 ! CS6AWCR set + + ! SDRAM initialization + mov.l SDCR_A, r1 ! SB_SDCR address -> R1 + mov.l SDCR_D, r0 ! SB_SDCR data -> R0 + mov.l r0, @r1 ! SB_SDCR set + + mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1 + mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0 + mov.l r0, @r1 ! SB_SDWCR set + + mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1 + mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0 + mov.l r0, @r1 ! SB_SDPCR set + + mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1 + mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0 + mov.l r0, @r1 ! SB_RTCOR set + + mov.l RTCNT_A, r1 ! SB_RTCNT address -> R1 + mov.l RTCNT_D, r0 ! SB_RTCNT data -> R0 + mov.l r0, @r1 + + mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1 + mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0 + mov.l r0, @r1 ! SB_RTCSR set + + mov.l RFCR_A, r1 ! SB_RFCR address -> R1 + mov.l RFCR_D, r0 ! SB_RFCR data -> R0 + mov.l r0, @r1 + + mov.l SDMR3_A, r1 ! SDMR3 address -> R1 + mov #0x00, r0 ! SDMR3 data -> R0 + mov.b r0, @r1 ! SDMR3 set + + ! BL bit off (init = ON) (?!?) + + stc sr, r0 ! BL bit off(init=ON) + mov.l SR_MASK_D, r1 + and r1, r0 + ldc r0, sr + + rts + mov #0, r0 + + .align 4 + +CCR_A: .long CCR +MMUCR_A: .long MMUCR +MSTPCR0_A: .long MSTPCR0 +MSTPCR2_A: .long MSTPCR2 +PFC_PULCR_A: .long PULCR +PFC_DRVCR_A: .long DRVCR +SBSCR_A: .long SBSCR +PSCR_A: .long PSCR +RWTCSR_A: .long RWTCSR +RWTCNT_A: .long RWTCNT +FRQCR_A: .long FRQCR +PLLCR_A: .long PLLCR +DLLFRQ_A: .long DLLFRQ + +CCR_D: .long 0x00000800 +CCR_D_2: .long 0x00000103 +MMUCR_D: .long 0x00000004 +MSTPCR0_D: .long 0x00001001 +MSTPCR2_D: .long 0xffffffff +PFC_PULCR_D: .long 0x6000 +PFC_DRVCR_D: .long 0x0464 +FRQCR_D: .long 0x07033639 +PLLCR_D: .long 0x00005000 +DLLFRQ_D: .long 0x000004F6 ! 20080115 + +CMNCR_A: .long CMNCR +CMNCR_D: .long 0x0000001B ! 20080115 +CS0BCR_A: .long CS0BCR ! Flash bank 1 +CS0BCR_D: .long 0x24920400 +CS4BCR_A: .long CS4BCR ! +CS4BCR_D: .long 0x10003400 ! 20080115 +CS5ABCR_A: .long CS5ABCR ! +CS5ABCR_D: .long 0x24920400 +CS5BBCR_A: .long CS5BBCR ! +CS5BBCR_D: .long 0x24920400 +CS6ABCR_A: .long CS6ABCR ! +CS6ABCR_D: .long 0x24920400 + +CS0WCR_A: .long CS0WCR +CS0WCR_D: .long 0x00000380 +CS4WCR_A: .long CS4WCR +CS4WCR_D: .long 0x00100A81 ! 20080115 +CS5AWCR_A: .long CS5AWCR +CS5AWCR_D: .long 0x00000300 +CS5BWCR_A: .long CS5BWCR +CS5BWCR_D: .long 0x00000300 +CS6AWCR_A: .long CS6AWCR +CS6AWCR_D: .long 0x00000300 + +SDCR_A: .long SBSC_SDCR +SDCR_D: .long 0x80160809 ! 20080115 +SDWCR_A: .long SBSC_SDWCR +SDWCR_D: .long 0x0014450C ! 20080115 +SDPCR_A: .long SBSC_SDPCR +SDPCR_D: .long 0x00000087 +RTCOR_A: .long SBSC_RTCOR +RTCNT_A: .long SBSC_RTCNT +RTCNT_D: .long 0xA55A0012 +RTCOR_D: .long 0xA55A001C ! 20080115 +RTCSR_A: .long SBSC_RTCSR +RFCR_A: .long SBSC_RFCR +RFCR_D: .long 0xA55A0221 +RTCSR_D: .long 0xA55A009a ! 20080115 +SDMR3_A: .long 0xFE581180 ! 20080115 + +SR_MASK_D: .long 0xEFFFFF0F + + .align 2 + +SBSCR_D: .word 0x0044 +PSCR_D: .word 0x0000 +RWTCSR_D_1: .word 0xA507 +RWTCSR_D_2: .word 0xA504 ! 20080115 +RWTCNT_D: .word 0x5A00 diff --git a/board/renesas/MigoR/migo_r.c b/board/renesas/MigoR/migo_r.c new file mode 100644 index 0000000000..204ca78fa4 --- /dev/null +++ b/board/renesas/MigoR/migo_r.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu + * + * Copyright (C) 2007 + * Kenati Technologies, Inc. + * + * board/MigoR/migo_r.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +int checkboard(void) +{ + puts("BOARD: Renesas MigoR\n"); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state (unsigned short value) +{ +} diff --git a/board/renesas/MigoR/u-boot.lds b/board/renesas/MigoR/u-boot.lds new file mode 100644 index 0000000000..f9c1effa44 --- /dev/null +++ b/board/renesas/MigoR/u-boot.lds @@ -0,0 +1,105 @@ +/* + * Copyrigth (c) 2007 + * Nobuhiro Iwamatsu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x0C000000. + Although size of SDRAM can be either 16 or 32 MBytes, + we assume 16 MBytes (ie ignore upper half if the full + 32 MBytes is present). + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x8C000000 + (64*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} -- cgit v1.2.1 From 51b572a801be57790fe26adaa530210e7fba59cc Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 24 Oct 2008 10:49:48 +0900 Subject: sh: rsk7203: Moved rsk7203 board to board/renesas Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/rsk7203/Makefile | 45 ++++++ board/renesas/rsk7203/config.mk | 28 ++++ board/renesas/rsk7203/lowlevel_init.S | 265 ++++++++++++++++++++++++++++++++++ board/renesas/rsk7203/rsk7203.c | 71 +++++++++ board/renesas/rsk7203/u-boot.lds | 101 +++++++++++++ board/rsk7203/Makefile | 45 ------ board/rsk7203/config.mk | 28 ---- board/rsk7203/lowlevel_init.S | 265 ---------------------------------- board/rsk7203/rsk7203.c | 71 --------- board/rsk7203/u-boot.lds | 101 ------------- 10 files changed, 510 insertions(+), 510 deletions(-) create mode 100644 board/renesas/rsk7203/Makefile create mode 100644 board/renesas/rsk7203/config.mk create mode 100644 board/renesas/rsk7203/lowlevel_init.S create mode 100644 board/renesas/rsk7203/rsk7203.c create mode 100644 board/renesas/rsk7203/u-boot.lds delete mode 100644 board/rsk7203/Makefile delete mode 100644 board/rsk7203/config.mk delete mode 100644 board/rsk7203/lowlevel_init.S delete mode 100644 board/rsk7203/rsk7203.c delete mode 100644 board/rsk7203/u-boot.lds (limited to 'board') diff --git a/board/renesas/rsk7203/Makefile b/board/renesas/rsk7203/Makefile new file mode 100644 index 0000000000..7365d19301 --- /dev/null +++ b/board/renesas/rsk7203/Makefile @@ -0,0 +1,45 @@ +# +# Copyright (C) 2007,2008 Nobuhiro Iwamatsu +# Copyright (C) 2008 Renesas Solutions Corp. +# +# u-boot/board/rsk7203/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := rsk7203.o +SOBJS := lowlevel_init.o + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/renesas/rsk7203/config.mk b/board/renesas/rsk7203/config.mk new file mode 100644 index 0000000000..61aa51f2b8 --- /dev/null +++ b/board/renesas/rsk7203/config.mk @@ -0,0 +1,28 @@ +# +# Copyright (C) 2007,2008 Nobuhiro Iwamatsu +# Copyright (C) 2008 Renesas Solutions Corp. +# +# u-boot/board/rsk7203/config.mk +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# + +TEXT_BASE = 0x0C7C0000 diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S new file mode 100644 index 0000000000..e4d6f9e7df --- /dev/null +++ b/board/renesas/rsk7203/lowlevel_init.S @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2008 Nobuhiro Iwamatsu + * Copyright (C) 2008 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include + +#include + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + /* Cache setting */ + mov.l CCR1_A ,r1 + mov.l CCR1_D ,r0 + mov.l r0,@r1 + + /* ConfigurePortPins */ + mov.l PECRL3_A, r1 + mov.l PECRL3_D, r0 + mov.w r0,@r1 + + mov.l PCCRL4_A, r1 + mov.l PCCRL4_D0, r0 + mov.w r0,@r1 + + mov.l PECRL4_A, r1 + mov.l PECRL4_D0, r0 + mov.w r0,@r1 + + mov.l PEIORL_A, r1 + mov.l PEIORL_D0, r0 + mov.w r0,@r1 + + mov.l PCIORL_A, r1 + mov.l PCIORL_D, r0 + mov.w r0,@r1 + + mov.l PFCRH2_A, r1 + mov.l PFCRH2_D, r0 + mov.w r0,@r1 + + mov.l PFCRH3_A, r1 + mov.l PFCRH3_D, r0 + mov.w r0,@r1 + + mov.l PFCRH1_A, r1 + mov.l PFCRH1_D, r0 + mov.w r0,@r1 + + mov.l PFIORH_A, r1 + mov.l PFIORH_D, r0 + mov.w r0,@r1 + + mov.l PECRL1_A, r1 + mov.l PECRL1_D0, r0 + mov.w r0,@r1 + + mov.l PEIORL_A, r1 + mov.l PEIORL_D1, r0 + mov.w r0,@r1 + + /* Configure Operating Frequency */ + mov.l WTCSR_A ,r1 + mov.l WTCSR_D0 ,r0 + mov.w r0,@r1 + + mov.l WTCSR_A ,r1 + mov.l WTCSR_D1 ,r0 + mov.w r0,@r1 + + mov.l WTCNT_A ,r1 + mov.l WTCNT_D ,r0 + mov.w r0,@r1 + + /* Set clock mode*/ + mov.l FRQCR_A,r1 + mov.l FRQCR_D,r0 + mov.w r0,@r1 + + /* Configure Bus And Memory */ +init_bsc_cs0: + mov.l PCCRL4_A,r1 + mov.l PCCRL4_D1,r0 + mov.w r0,@r1 + + mov.l PECRL1_A,r1 + mov.l PECRL1_D1,r0 + mov.w r0,@r1 + + mov.l CMNCR_A,r1 + mov.l CMNCR_D,r0 + mov.l r0,@r1 + + mov.l SC0BCR_A,r1 + mov.l SC0BCR_D,r0 + mov.l r0,@r1 + + mov.l CS0WCR_A,r1 + mov.l CS0WCR_D,r0 + mov.l r0,@r1 + +init_bsc_cs1: + mov.l PECRL4_A,r1 + mov.l PECRL4_D1,r0 + mov.w r0,@r1 + + mov.l CS1WCR_A,r1 + mov.l CS1WCR_D,r0 + mov.l r0,@r1 + +init_sdram: + mov.l PCCRL2_A,r1 + mov.l PCCRL2_D,r0 + mov.w r0,@r1 + + mov.l PCCRL4_A,r1 + mov.l PCCRL4_D2,r0 + mov.w r0,@r1 + + mov.l PCCRL1_A,r1 + mov.l PCCRL1_D,r0 + mov.w r0,@r1 + + mov.l PCCRL3_A,r1 + mov.l PCCRL3_D,r0 + mov.w r0,@r1 + + mov.l CS3BCR_A,r1 + mov.l CS3BCR_D,r0 + mov.l r0,@r1 + + mov.l CS3WCR_A,r1 + mov.l CS3WCR_D,r0 + mov.l r0,@r1 + + mov.l SDCR_A,r1 + mov.l SDCR_D,r0 + mov.l r0,@r1 + + mov.l RTCOR_A,r1 + mov.l RTCOR_D,r0 + mov.l r0,@r1 + + mov.l RTCSR_A,r1 + mov.l RTCSR_D,r0 + mov.l r0,@r1 + + /* wait 200us */ + mov.l REPEAT_D,r3 + mov #0,r2 +repeat0: + add #1,r2 + cmp/hs r3,r2 + bf repeat0 + nop + + mov.l SDRAM_MODE, r1 + mov #0,r0 + mov.l r0, @r1 + + nop + rts + + .align 4 + +CCR1_A: .long CCR1 +CCR1_D: .long 0x0000090B +PCCRL4_A: .long 0xFFFE3910 +PCCRL4_D0: .long 0x00000000 +PECRL4_A: .long 0xFFFE3A10 +PECRL4_D0: .long 0x00000000 +PECRL3_A: .long 0xFFFE3A12 +PECRL3_D: .long 0x00000000 +PEIORL_A: .long 0xFFFE3A06 +PEIORL_D0: .long 0x00001C00 +PEIORL_D1: .long 0x00001C02 +PCIORL_A: .long 0xFFFE3906 +PCIORL_D: .long 0x00004000 +PFCRH2_A: .long 0xFFFE3A8C +PFCRH2_D: .long 0x00000000 +PFCRH3_A: .long 0xFFFE3A8A +PFCRH3_D: .long 0x00000000 +PFCRH1_A: .long 0xFFFE3A8E +PFCRH1_D: .long 0x00000000 +PFIORH_A: .long 0xFFFE3A84 +PFIORH_D: .long 0x00000729 +PECRL1_A: .long 0xFFFE3A16 +PECRL1_D0: .long 0x00000033 + + +WTCSR_A: .long 0xFFFE0000 +WTCSR_D0: .long 0x0000A518 +WTCSR_D1: .long 0x0000A51D +WTCNT_A: .long 0xFFFE0002 +WTCNT_D: .long 0x00005A84 +FRQCR_A: .long 0xFFFE0010 +FRQCR_D: .long 0x00000104 + +PCCRL4_D1: .long 0x00000010 +PECRL1_D1: .long 0x00000133 + +CMNCR_A: .long 0xFFFC0000 +CMNCR_D: .long 0x00001810 +SC0BCR_A: .long 0xFFFC0004 +SC0BCR_D: .long 0x10000400 +CS0WCR_A: .long 0xFFFC0028 +CS0WCR_D: .long 0x00000B41 +PECRL4_D1: .long 0x00000100 +CS1WCR_A: .long 0xFFFC002C +CS1WCR_D: .long 0x00000B01 +PCCRL4_D2: .long 0x00000011 +PCCRL3_A: .long 0xFFFE3912 +PCCRL3_D: .long 0x00000011 +PCCRL2_A: .long 0xFFFE3914 +PCCRL2_D: .long 0x00001111 +PCCRL1_A: .long 0xFFFE3916 +PCCRL1_D: .long 0x00001010 +PDCRL4_A: .long 0xFFFE3990 +PDCRL4_D: .long 0x00000011 +PDCRL3_A: .long 0xFFFE3992 +PDCRL3_D: .long 0x00000011 +PDCRL2_A: .long 0xFFFE3994 +PDCRL2_D: .long 0x00001111 +PDCRL1_A: .long 0xFFFE3996 +PDCRL1_D: .long 0x00001000 +CS3BCR_A: .long 0xFFFC0010 +CS3BCR_D: .long 0x00004400 +CS3WCR_A: .long 0xFFFC0034 +CS3WCR_D: .long 0x00002892 +SDCR_A: .long 0xFFFC004C +SDCR_D: .long 0x00000809 +RTCOR_A: .long 0xFFFC0058 +RTCOR_D: .long 0xA55A0041 +RTCSR_A: .long 0xFFFC0050 +RTCSR_D: .long 0xa55a0010 + +STBCR3_A: .long 0xFFFE0408 +STBCR3_D: .long 0x00000000 +STBCR4_A: .long 0xFFFE040C +STBCR4_D: .long 0x00000008 +STBCR5_A: .long 0xFFFE0410 +STBCR5_D: .long 0x00000000 +STBCR6_A: .long 0xFFFE0414 +STBCR6_D: .long 0x00000002 +SDRAM_MODE: .long 0xFFFC5040 +REPEAT_D: .long 0x00009C40 diff --git a/board/renesas/rsk7203/rsk7203.c b/board/renesas/rsk7203/rsk7203.c new file mode 100644 index 0000000000..2cbd45e043 --- /dev/null +++ b/board/renesas/rsk7203/rsk7203.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2008 Nobuhiro Iwamatsu + * Copyright (C) 2008 Renesas Solutions Corp. + * + * u-boot/board/rsk7203/rsk7203.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +int checkboard(void) +{ + puts("BOARD: Renesas Technology RSK7203\n"); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state(unsigned short value) +{ +} + +/* + * The RSK board has the SMSC9118 wired up 'incorrectly'. + * Byte-swapping is necessary, and so poor performance is inevitable. + * This problem cannot evade by the swap function of CHIP, this can + * evade by software Byte-swapping. + * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push + * functions necessary to solve this problem. + */ +u32 pkt_data_pull(u32 addr) +{ + volatile u16 *addr_16 = (u16 *)addr; + return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\ + | swab16(*(addr_16 + 1)); +} + +void pkt_data_push(u32 addr, u32 val) +{ + *(volatile u16 *)(addr + 2) = swab16((u16)val); + *(volatile u16 *)(addr) = swab16((u16)(val >> 16)); +} diff --git a/board/renesas/rsk7203/u-boot.lds b/board/renesas/rsk7203/u-boot.lds new file mode 100644 index 0000000000..63e5b9744e --- /dev/null +++ b/board/renesas/rsk7203/u-boot.lds @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2008 Nobuhiro Iwamatsu + * Copyright (C) 2008 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + * Base address of internal SDRAM is 0x0C000000. + * + * NOTE: This address must match with the definition of + *TEXT_BASE in config.mk (in this directory). + */ + + . = 0x0C000000 + (8*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh2/start.o (.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/board/rsk7203/Makefile b/board/rsk7203/Makefile deleted file mode 100644 index 7365d19301..0000000000 --- a/board/rsk7203/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# Copyright (C) 2007,2008 Nobuhiro Iwamatsu -# Copyright (C) 2008 Renesas Solutions Corp. -# -# u-boot/board/rsk7203/Makefile -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := rsk7203.o -SOBJS := lowlevel_init.o - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/rsk7203/config.mk b/board/rsk7203/config.mk deleted file mode 100644 index 61aa51f2b8..0000000000 --- a/board/rsk7203/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# Copyright (C) 2007,2008 Nobuhiro Iwamatsu -# Copyright (C) 2008 Renesas Solutions Corp. -# -# u-boot/board/rsk7203/config.mk -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -# -# TEXT_BASE refers to image _after_ relocation. -# -# NOTE: Must match value used in u-boot.lds (in this directory). -# - -TEXT_BASE = 0x0C7C0000 diff --git a/board/rsk7203/lowlevel_init.S b/board/rsk7203/lowlevel_init.S deleted file mode 100644 index e4d6f9e7df..0000000000 --- a/board/rsk7203/lowlevel_init.S +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright (C) 2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include - -#include - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - /* Cache setting */ - mov.l CCR1_A ,r1 - mov.l CCR1_D ,r0 - mov.l r0,@r1 - - /* ConfigurePortPins */ - mov.l PECRL3_A, r1 - mov.l PECRL3_D, r0 - mov.w r0,@r1 - - mov.l PCCRL4_A, r1 - mov.l PCCRL4_D0, r0 - mov.w r0,@r1 - - mov.l PECRL4_A, r1 - mov.l PECRL4_D0, r0 - mov.w r0,@r1 - - mov.l PEIORL_A, r1 - mov.l PEIORL_D0, r0 - mov.w r0,@r1 - - mov.l PCIORL_A, r1 - mov.l PCIORL_D, r0 - mov.w r0,@r1 - - mov.l PFCRH2_A, r1 - mov.l PFCRH2_D, r0 - mov.w r0,@r1 - - mov.l PFCRH3_A, r1 - mov.l PFCRH3_D, r0 - mov.w r0,@r1 - - mov.l PFCRH1_A, r1 - mov.l PFCRH1_D, r0 - mov.w r0,@r1 - - mov.l PFIORH_A, r1 - mov.l PFIORH_D, r0 - mov.w r0,@r1 - - mov.l PECRL1_A, r1 - mov.l PECRL1_D0, r0 - mov.w r0,@r1 - - mov.l PEIORL_A, r1 - mov.l PEIORL_D1, r0 - mov.w r0,@r1 - - /* Configure Operating Frequency */ - mov.l WTCSR_A ,r1 - mov.l WTCSR_D0 ,r0 - mov.w r0,@r1 - - mov.l WTCSR_A ,r1 - mov.l WTCSR_D1 ,r0 - mov.w r0,@r1 - - mov.l WTCNT_A ,r1 - mov.l WTCNT_D ,r0 - mov.w r0,@r1 - - /* Set clock mode*/ - mov.l FRQCR_A,r1 - mov.l FRQCR_D,r0 - mov.w r0,@r1 - - /* Configure Bus And Memory */ -init_bsc_cs0: - mov.l PCCRL4_A,r1 - mov.l PCCRL4_D1,r0 - mov.w r0,@r1 - - mov.l PECRL1_A,r1 - mov.l PECRL1_D1,r0 - mov.w r0,@r1 - - mov.l CMNCR_A,r1 - mov.l CMNCR_D,r0 - mov.l r0,@r1 - - mov.l SC0BCR_A,r1 - mov.l SC0BCR_D,r0 - mov.l r0,@r1 - - mov.l CS0WCR_A,r1 - mov.l CS0WCR_D,r0 - mov.l r0,@r1 - -init_bsc_cs1: - mov.l PECRL4_A,r1 - mov.l PECRL4_D1,r0 - mov.w r0,@r1 - - mov.l CS1WCR_A,r1 - mov.l CS1WCR_D,r0 - mov.l r0,@r1 - -init_sdram: - mov.l PCCRL2_A,r1 - mov.l PCCRL2_D,r0 - mov.w r0,@r1 - - mov.l PCCRL4_A,r1 - mov.l PCCRL4_D2,r0 - mov.w r0,@r1 - - mov.l PCCRL1_A,r1 - mov.l PCCRL1_D,r0 - mov.w r0,@r1 - - mov.l PCCRL3_A,r1 - mov.l PCCRL3_D,r0 - mov.w r0,@r1 - - mov.l CS3BCR_A,r1 - mov.l CS3BCR_D,r0 - mov.l r0,@r1 - - mov.l CS3WCR_A,r1 - mov.l CS3WCR_D,r0 - mov.l r0,@r1 - - mov.l SDCR_A,r1 - mov.l SDCR_D,r0 - mov.l r0,@r1 - - mov.l RTCOR_A,r1 - mov.l RTCOR_D,r0 - mov.l r0,@r1 - - mov.l RTCSR_A,r1 - mov.l RTCSR_D,r0 - mov.l r0,@r1 - - /* wait 200us */ - mov.l REPEAT_D,r3 - mov #0,r2 -repeat0: - add #1,r2 - cmp/hs r3,r2 - bf repeat0 - nop - - mov.l SDRAM_MODE, r1 - mov #0,r0 - mov.l r0, @r1 - - nop - rts - - .align 4 - -CCR1_A: .long CCR1 -CCR1_D: .long 0x0000090B -PCCRL4_A: .long 0xFFFE3910 -PCCRL4_D0: .long 0x00000000 -PECRL4_A: .long 0xFFFE3A10 -PECRL4_D0: .long 0x00000000 -PECRL3_A: .long 0xFFFE3A12 -PECRL3_D: .long 0x00000000 -PEIORL_A: .long 0xFFFE3A06 -PEIORL_D0: .long 0x00001C00 -PEIORL_D1: .long 0x00001C02 -PCIORL_A: .long 0xFFFE3906 -PCIORL_D: .long 0x00004000 -PFCRH2_A: .long 0xFFFE3A8C -PFCRH2_D: .long 0x00000000 -PFCRH3_A: .long 0xFFFE3A8A -PFCRH3_D: .long 0x00000000 -PFCRH1_A: .long 0xFFFE3A8E -PFCRH1_D: .long 0x00000000 -PFIORH_A: .long 0xFFFE3A84 -PFIORH_D: .long 0x00000729 -PECRL1_A: .long 0xFFFE3A16 -PECRL1_D0: .long 0x00000033 - - -WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .long 0x0000A518 -WTCSR_D1: .long 0x0000A51D -WTCNT_A: .long 0xFFFE0002 -WTCNT_D: .long 0x00005A84 -FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .long 0x00000104 - -PCCRL4_D1: .long 0x00000010 -PECRL1_D1: .long 0x00000133 - -CMNCR_A: .long 0xFFFC0000 -CMNCR_D: .long 0x00001810 -SC0BCR_A: .long 0xFFFC0004 -SC0BCR_D: .long 0x10000400 -CS0WCR_A: .long 0xFFFC0028 -CS0WCR_D: .long 0x00000B41 -PECRL4_D1: .long 0x00000100 -CS1WCR_A: .long 0xFFFC002C -CS1WCR_D: .long 0x00000B01 -PCCRL4_D2: .long 0x00000011 -PCCRL3_A: .long 0xFFFE3912 -PCCRL3_D: .long 0x00000011 -PCCRL2_A: .long 0xFFFE3914 -PCCRL2_D: .long 0x00001111 -PCCRL1_A: .long 0xFFFE3916 -PCCRL1_D: .long 0x00001010 -PDCRL4_A: .long 0xFFFE3990 -PDCRL4_D: .long 0x00000011 -PDCRL3_A: .long 0xFFFE3992 -PDCRL3_D: .long 0x00000011 -PDCRL2_A: .long 0xFFFE3994 -PDCRL2_D: .long 0x00001111 -PDCRL1_A: .long 0xFFFE3996 -PDCRL1_D: .long 0x00001000 -CS3BCR_A: .long 0xFFFC0010 -CS3BCR_D: .long 0x00004400 -CS3WCR_A: .long 0xFFFC0034 -CS3WCR_D: .long 0x00002892 -SDCR_A: .long 0xFFFC004C -SDCR_D: .long 0x00000809 -RTCOR_A: .long 0xFFFC0058 -RTCOR_D: .long 0xA55A0041 -RTCSR_A: .long 0xFFFC0050 -RTCSR_D: .long 0xa55a0010 - -STBCR3_A: .long 0xFFFE0408 -STBCR3_D: .long 0x00000000 -STBCR4_A: .long 0xFFFE040C -STBCR4_D: .long 0x00000008 -STBCR5_A: .long 0xFFFE0410 -STBCR5_D: .long 0x00000000 -STBCR6_A: .long 0xFFFE0414 -STBCR6_D: .long 0x00000002 -SDRAM_MODE: .long 0xFFFC5040 -REPEAT_D: .long 0x00009C40 diff --git a/board/rsk7203/rsk7203.c b/board/rsk7203/rsk7203.c deleted file mode 100644 index 2cbd45e043..0000000000 --- a/board/rsk7203/rsk7203.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (C) 2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - * - * u-boot/board/rsk7203/rsk7203.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -int checkboard(void) -{ - puts("BOARD: Renesas Technology RSK7203\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -int dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -void led_set_state(unsigned short value) -{ -} - -/* - * The RSK board has the SMSC9118 wired up 'incorrectly'. - * Byte-swapping is necessary, and so poor performance is inevitable. - * This problem cannot evade by the swap function of CHIP, this can - * evade by software Byte-swapping. - * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push - * functions necessary to solve this problem. - */ -u32 pkt_data_pull(u32 addr) -{ - volatile u16 *addr_16 = (u16 *)addr; - return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\ - | swab16(*(addr_16 + 1)); -} - -void pkt_data_push(u32 addr, u32 val) -{ - *(volatile u16 *)(addr + 2) = swab16((u16)val); - *(volatile u16 *)(addr) = swab16((u16)(val >> 16)); -} diff --git a/board/rsk7203/u-boot.lds b/board/rsk7203/u-boot.lds deleted file mode 100644 index 63e5b9744e..0000000000 --- a/board/rsk7203/u-boot.lds +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (C) 2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - * Base address of internal SDRAM is 0x0C000000. - * - * NOTE: This address must match with the definition of - *TEXT_BASE in config.mk (in this directory). - */ - - . = 0x0C000000 + (8*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - cpu/sh2/start.o (.text) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(.rodata) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); - } - PROVIDE (__u_boot_cmd_end = .); - - PROVIDE (reloc_dst_end = .); - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (_end = .); -} -- cgit v1.2.1