From a4d799939fdb08ce4d7464578734316cdd0bf452 Mon Sep 17 00:00:00 2001 From: Hannes Schmelzer Date: Wed, 22 Jun 2016 12:36:14 +0200 Subject: board/BuR: rename kwb board to brxre1 Rename B&R kwb board to brxre1 Signed-off-by: Hannes Schmelzer Reviewed-by: Tom Rini --- board/BuR/brxre1/Kconfig | 15 +++ board/BuR/brxre1/MAINTAINERS | 6 + board/BuR/brxre1/Makefile | 12 ++ board/BuR/brxre1/board.c | 298 +++++++++++++++++++++++++++++++++++++++++++ board/BuR/brxre1/mux.c | 198 ++++++++++++++++++++++++++++ board/BuR/kwb/Kconfig | 15 --- board/BuR/kwb/MAINTAINERS | 6 - board/BuR/kwb/Makefile | 12 -- board/BuR/kwb/board.c | 298 ------------------------------------------- board/BuR/kwb/mux.c | 198 ---------------------------- 10 files changed, 529 insertions(+), 529 deletions(-) create mode 100644 board/BuR/brxre1/Kconfig create mode 100644 board/BuR/brxre1/MAINTAINERS create mode 100644 board/BuR/brxre1/Makefile create mode 100644 board/BuR/brxre1/board.c create mode 100644 board/BuR/brxre1/mux.c delete mode 100644 board/BuR/kwb/Kconfig delete mode 100644 board/BuR/kwb/MAINTAINERS delete mode 100644 board/BuR/kwb/Makefile delete mode 100644 board/BuR/kwb/board.c delete mode 100644 board/BuR/kwb/mux.c (limited to 'board') diff --git a/board/BuR/brxre1/Kconfig b/board/BuR/brxre1/Kconfig new file mode 100644 index 0000000000..389e523f60 --- /dev/null +++ b/board/BuR/brxre1/Kconfig @@ -0,0 +1,15 @@ +if TARGET_BRXRE1 + +config SYS_BOARD + default "brxre1" + +config SYS_VENDOR + default "BuR" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "brxre1" + +endif diff --git a/board/BuR/brxre1/MAINTAINERS b/board/BuR/brxre1/MAINTAINERS new file mode 100644 index 0000000000..a10d9c1d71 --- /dev/null +++ b/board/BuR/brxre1/MAINTAINERS @@ -0,0 +1,6 @@ +BRXRE1 BOARD +M: Hannes Schmelzer +S: Maintained +F: board/BuR/brxre1/ +F: include/configs/brxre1.h +F: configs/brxre1_defconfig diff --git a/board/BuR/brxre1/Makefile b/board/BuR/brxre1/Makefile new file mode 100644 index 0000000000..782664c36e --- /dev/null +++ b/board/BuR/brxre1/Makefile @@ -0,0 +1,12 @@ +# +# Makefile +# +# Copyright (C) 2014 Hannes Schmelzer - +# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_SPL_BUILD) += mux.o +obj-y += ../common/common.o +obj-y += board.o diff --git a/board/BuR/brxre1/board.c b/board/BuR/brxre1/board.c new file mode 100644 index 0000000000..f4bfa410cc --- /dev/null +++ b/board/BuR/brxre1/board.c @@ -0,0 +1,298 @@ +/* + * board.c + * + * Board functions for B&R BRXRE1 Board + * + * Copyright (C) 2013 Hannes Schmelzer + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/bur_common.h" +#include + +/* -------------------------------------------------------------------------*/ +/* -- defines for used GPIO Hardware -- */ +#define ESC_KEY (0+19) +#define LCD_PWR (0+5) +#define PUSH_KEY (0+31) +/* -------------------------------------------------------------------------*/ +/* -- PSOC Resetcontroller Register defines -- */ + +/* I2C Address of controller */ +#define RSTCTRL_ADDR 0x75 +/* Register for CTRL-word */ +#define RSTCTRL_CTRLREG 0x01 +/* Register for giving some information to VxWorks OS */ +#define RSTCTRL_SCRATCHREG 0x04 + +/* -- defines for RSTCTRL_CTRLREG -- */ +#define RSTCTRL_FORCE_PWR_NEN 0x0404 +#define RSTCTRL_CAN_STB 0x4040 + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_SPL_BUILD) +/* TODO: check ram-timing ! */ +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +static const struct ctrl_ioregs ddr3_ioregs = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + unsigned int oldspeed; + unsigned short buf; + + struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; + struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; + /* + * enable additional clocks of modules which are accessed later from + * VxWorks OS + */ + u32 *const clk_domains[] = { 0 }; + + u32 *const clk_modules_xre1specific[] = { + &cmwkup->wkup_adctscctrl, + &cmper->spi1clkctrl, + &cmper->dcan0clkctrl, + &cmper->dcan1clkctrl, + &cmper->epwmss0clkctrl, + &cmper->epwmss1clkctrl, + &cmper->epwmss2clkctrl, + &cmper->lcdclkctrl, + &cmper->lcdcclkstctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_xre1specific, 1); + /* setup LCD-Pixel Clock */ + writel(0x2, CM_DPLL + 0x34); + /* power-OFF LCD-Display */ + gpio_direction_output(LCD_PWR, 0); + + /* setup I2C */ + enable_i2c_pin_mux(); + i2c_set_bus_num(0); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + + /* power-ON 3V3 via Resetcontroller */ + oldspeed = i2c_get_bus_speed(); + if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { + buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB; + i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1, + (uint8_t *)&buf, sizeof(buf)); + i2c_set_bus_speed(oldspeed); + } else { + puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n"); + } + + pmicsetup(0); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr3; +} + +void sdram_init(void) +{ + config_ddr(400, &ddr3_ioregs, + &ddr3_data, + &ddr3_cmd_ctrl_data, + &ddr3_emif_reg_data, 0); +} +#endif /* CONFIG_SPL_BUILD */ +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + gpmc_init(); + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + const unsigned int toff = 1000; + unsigned int cnt = 3; + unsigned short buf = 0xAAAA; + unsigned char scratchreg = 0; + unsigned int oldspeed; + + /* try to read out some boot-instruction from resetcontroller */ + oldspeed = i2c_get_bus_speed(); + if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { + i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, + &scratchreg, sizeof(scratchreg)); + i2c_set_bus_speed(oldspeed); + } else { + puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); + } + + if (gpio_get_value(ESC_KEY)) { + do { + lcd_position_cursor(1, 8); + switch (cnt) { + case 3: + lcd_puts( + "release ESC-KEY to enter SERVICE-mode."); + break; + case 2: + lcd_puts( + "release ESC-KEY to enter DIAGNOSE-mode."); + break; + case 1: + lcd_puts( + "release ESC-KEY to enter BOOT-mode. "); + break; + } + mdelay(toff); + cnt--; + if (!gpio_get_value(ESC_KEY) && + gpio_get_value(PUSH_KEY) && 2 == cnt) { + lcd_position_cursor(1, 8); + lcd_puts( + "switching to network-console ... "); + setenv("bootcmd", "run netconsole"); + cnt = 4; + break; + } else if (!gpio_get_value(ESC_KEY) && + gpio_get_value(PUSH_KEY) && 1 == cnt) { + lcd_position_cursor(1, 8); + lcd_puts( + "starting u-boot script from USB ... "); + setenv("bootcmd", "run usbscript"); + cnt = 4; + break; + } else if ((!gpio_get_value(ESC_KEY) && + gpio_get_value(PUSH_KEY) && cnt == 0) || + (gpio_get_value(ESC_KEY) && + gpio_get_value(PUSH_KEY) && cnt == 0)) { + lcd_position_cursor(1, 8); + lcd_puts( + "starting script from network ... "); + setenv("bootcmd", "run netscript"); + cnt = 4; + break; + } else if (!gpio_get_value(ESC_KEY)) { + break; + } + } while (cnt); + } else if (scratchreg == 0xCC) { + lcd_position_cursor(1, 8); + lcd_puts( + "starting vxworks from network ... "); + setenv("bootcmd", "run netboot"); + cnt = 4; + } else if (scratchreg == 0xCD) { + lcd_position_cursor(1, 8); + lcd_puts( + "starting script from network ... "); + setenv("bootcmd", "run netscript"); + cnt = 4; + } else if (scratchreg == 0xCE) { + lcd_position_cursor(1, 8); + lcd_puts( + "starting AR from eMMC ... "); + setenv("bootcmd", "run mmcboot"); + cnt = 4; + } + + lcd_position_cursor(1, 8); + switch (cnt) { + case 0: + lcd_puts("entering BOOT-mode. "); + setenv("bootcmd", "run defaultAR"); + buf = 0x0000; + break; + case 1: + lcd_puts("entering DIAGNOSE-mode. "); + buf = 0x0F0F; + break; + case 2: + lcd_puts("entering SERVICE mode. "); + buf = 0xB4B4; + break; + case 3: + lcd_puts("loading OS... "); + buf = 0x0404; + break; + } + /* write bootinfo into scratchregister of resetcontroller */ + oldspeed = i2c_get_bus_speed(); + if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { + i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, + (uint8_t *)&buf, sizeof(buf)); + i2c_set_bus_speed(oldspeed); + } else { + puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); + } + /* setup othbootargs for bootvx-command (vxWorks bootline) */ + char othbootargs[128]; + snprintf(othbootargs, sizeof(othbootargs), + "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x", + (unsigned int) gd->fb_base-0x20, + (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20), + (u32)getenv_ulong("vx_romfsbase", 16, 0), + (u32)getenv_ulong("vx_romfssize", 16, 0)); + setenv("othbootargs", othbootargs); + /* + * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does + * expect that vectors are there, original u-boot moves them to _start + */ + __asm__("ldr r0,=0x20000"); + __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */ + + return 0; +} +#endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/BuR/brxre1/mux.c b/board/BuR/brxre1/mux.c new file mode 100644 index 0000000000..40224f76f6 --- /dev/null +++ b/board/BuR/brxre1/mux.c @@ -0,0 +1,198 @@ +/* + * mux.c + * + * Pinmux Setting for B&R LEIT Board(s) + * + * Copyright (C) 2013 Hannes Schmelzer + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct module_pin_mux spi0_pin_mux[] = { + /* SPI1_SCLK */ + {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE}, + /* SPI1_D0 */ + {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE}, + /* SPI1_D1 */ + {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE}, + /* SPI1_CS0 */ + {OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE}, + /* SPI1_CS1 */ + {OFFSET(spi0_cs1), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE}, + {-1}, +}; + +static struct module_pin_mux dcan0_pin_mux[] = { + /* DCAN0 TX */ + {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN}, + /* DCAN0 RX */ + {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE}, + {-1}, +}; + +static struct module_pin_mux dcan1_pin_mux[] = { + /* DCAN1 TX */ + {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN}, + /* DCAN1 RX */ + {OFFSET(uart1_txd), MODE(2) | RXACTIVE}, + {-1}, +}; + +static struct module_pin_mux gpios[] = { + /* GPIO0_7 (PWW0 OUT) - CAN TERM */ + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_19 (DMA_INTR0) - TA602 */ + {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_20 (DMA_INTR1) - SPI0 nCS1 */ + {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ + {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)}, + /* GPIO0_30 (GPMC_WAIT0) - TA601 */ + {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_31 (GPMC_nWP) - SW601 PushButton */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO1_28 (GPMC_nWE) - FRAM_nWP */ + {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)}, + /* GPIO1_29 (gpmc_csn0) - MMC nRST */ + {OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)}, + /* GPIO2_0 (GPMC_nCS3) - VBAT_OK */ + {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, + /* GPIO2_2 (GPMC_nADV_ALE) - DCOK */ + {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO2_4 (GPMC_nWE) - TST_BAST */ + {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)}, + /* GPIO2_5 (gpmc_be0n_cle) - DISPLAY_ON_OFF */ + {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)}, + /* GPIO3_16 (mcasp0_axr0) - ETH-LED green */ + {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO3_17 (mcasp0_ahclkr) - CAN_STB */ + {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */ + {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)}, + /* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */ + {OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)}, + /* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */ + {OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux uart0_pin_mux[] = { + /* UART0_CTS */ + {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_RXD */ + {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_TXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + /* I2C_DATA */ + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + /* I2C_SCLK */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ + {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ + {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ + {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ + {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ + + {-1}, +}; + +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */ + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */ + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */ + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */ + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */ + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */ + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */ + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */ + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */ + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */ + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */ + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */ + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */ + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */ + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */ + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */ + + {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */ + {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */ + {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */ + {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */ + {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */ + {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */ + {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */ + {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */ + + {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */ + {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */ + {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */ + {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */ + + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(spi0_pin_mux); + configure_module_pin_mux(dcan0_pin_mux); + configure_module_pin_mux(dcan1_pin_mux); + configure_module_pin_mux(mmc1_pin_mux); + configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(gpios); +} diff --git a/board/BuR/kwb/Kconfig b/board/BuR/kwb/Kconfig deleted file mode 100644 index 4beefbf771..0000000000 --- a/board/BuR/kwb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_KWB - -config SYS_BOARD - default "kwb" - -config SYS_VENDOR - default "BuR" - -config SYS_SOC - default "am33xx" - -config SYS_CONFIG_NAME - default "kwb" - -endif diff --git a/board/BuR/kwb/MAINTAINERS b/board/BuR/kwb/MAINTAINERS deleted file mode 100644 index ca7d329144..0000000000 --- a/board/BuR/kwb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -KWB BOARD -M: Hannes Schmelzer -S: Maintained -F: board/BuR/kwb/ -F: include/configs/kwb.h -F: configs/kwb_defconfig diff --git a/board/BuR/kwb/Makefile b/board/BuR/kwb/Makefile deleted file mode 100644 index 782664c36e..0000000000 --- a/board/BuR/kwb/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Makefile -# -# Copyright (C) 2014 Hannes Schmelzer - -# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_SPL_BUILD) += mux.o -obj-y += ../common/common.o -obj-y += board.o diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c deleted file mode 100644 index ad74ff299c..0000000000 --- a/board/BuR/kwb/board.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - * board.c - * - * Board functions for B&R KWB Board - * - * Copyright (C) 2013 Hannes Schmelzer - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com - * - * SPDX-License-Identifier: GPL-2.0+ - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/bur_common.h" -#include - -/* -------------------------------------------------------------------------*/ -/* -- defines for used GPIO Hardware -- */ -#define ESC_KEY (0+19) -#define LCD_PWR (0+5) -#define PUSH_KEY (0+31) -/* -------------------------------------------------------------------------*/ -/* -- PSOC Resetcontroller Register defines -- */ - -/* I2C Address of controller */ -#define RSTCTRL_ADDR 0x75 -/* Register for CTRL-word */ -#define RSTCTRL_CTRLREG 0x01 -/* Register for giving some information to VxWorks OS */ -#define RSTCTRL_SCRATCHREG 0x04 - -/* -- defines for RSTCTRL_CTRLREG -- */ -#define RSTCTRL_FORCE_PWR_NEN 0x0404 -#define RSTCTRL_CAN_STB 0x4040 - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_SPL_BUILD) -/* TODO: check ram-timing ! */ -static const struct ddr_data ddr3_data = { - .datardsratio0 = MT41K256M16HA125E_RD_DQS, - .datawdsratio0 = MT41K256M16HA125E_WR_DQS, - .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, - .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, -}; -static const struct cmd_control ddr3_cmd_ctrl_data = { - .cmd0csratio = MT41K256M16HA125E_RATIO, - .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, - - .cmd1csratio = MT41K256M16HA125E_RATIO, - .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, - - .cmd2csratio = MT41K256M16HA125E_RATIO, - .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, -}; -static struct emif_regs ddr3_emif_reg_data = { - .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, - .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, - .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, - .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, - .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, - .zq_config = MT41K256M16HA125E_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, -}; - -static const struct ctrl_ioregs ddr3_ioregs = { - .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, -}; - -#define OSC (V_OSCK/1000000) -const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; - -void am33xx_spl_board_init(void) -{ - unsigned int oldspeed; - unsigned short buf; - - struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; - struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; - /* - * enable additional clocks of modules which are accessed later from - * VxWorks OS - */ - u32 *const clk_domains[] = { 0 }; - - u32 *const clk_modules_kwbspecific[] = { - &cmwkup->wkup_adctscctrl, - &cmper->spi1clkctrl, - &cmper->dcan0clkctrl, - &cmper->dcan1clkctrl, - &cmper->epwmss0clkctrl, - &cmper->epwmss1clkctrl, - &cmper->epwmss2clkctrl, - &cmper->lcdclkctrl, - &cmper->lcdcclkstctrl, - 0 - }; - do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1); - /* setup LCD-Pixel Clock */ - writel(0x2, CM_DPLL + 0x34); - /* power-OFF LCD-Display */ - gpio_direction_output(LCD_PWR, 0); - - /* setup I2C */ - enable_i2c_pin_mux(); - i2c_set_bus_num(0); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - - /* power-ON 3V3 via Resetcontroller */ - oldspeed = i2c_get_bus_speed(); - if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { - buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB; - i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1, - (uint8_t *)&buf, sizeof(buf)); - i2c_set_bus_speed(oldspeed); - } else { - puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n"); - } - - pmicsetup(0); -} - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr3; -} - -void sdram_init(void) -{ - config_ddr(400, &ddr3_ioregs, - &ddr3_data, - &ddr3_cmd_ctrl_data, - &ddr3_emif_reg_data, 0); -} -#endif /* CONFIG_SPL_BUILD */ -/* - * Basic board specific setup. Pinmux has been handled already. - */ -int board_init(void) -{ - gpmc_init(); - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ - const unsigned int toff = 1000; - unsigned int cnt = 3; - unsigned short buf = 0xAAAA; - unsigned char scratchreg = 0; - unsigned int oldspeed; - - /* try to read out some boot-instruction from resetcontroller */ - oldspeed = i2c_get_bus_speed(); - if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { - i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, - &scratchreg, sizeof(scratchreg)); - i2c_set_bus_speed(oldspeed); - } else { - puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); - } - - if (gpio_get_value(ESC_KEY)) { - do { - lcd_position_cursor(1, 8); - switch (cnt) { - case 3: - lcd_puts( - "release ESC-KEY to enter SERVICE-mode."); - break; - case 2: - lcd_puts( - "release ESC-KEY to enter DIAGNOSE-mode."); - break; - case 1: - lcd_puts( - "release ESC-KEY to enter BOOT-mode. "); - break; - } - mdelay(toff); - cnt--; - if (!gpio_get_value(ESC_KEY) && - gpio_get_value(PUSH_KEY) && 2 == cnt) { - lcd_position_cursor(1, 8); - lcd_puts( - "switching to network-console ... "); - setenv("bootcmd", "run netconsole"); - cnt = 4; - break; - } else if (!gpio_get_value(ESC_KEY) && - gpio_get_value(PUSH_KEY) && 1 == cnt) { - lcd_position_cursor(1, 8); - lcd_puts( - "starting u-boot script from USB ... "); - setenv("bootcmd", "run usbscript"); - cnt = 4; - break; - } else if ((!gpio_get_value(ESC_KEY) && - gpio_get_value(PUSH_KEY) && cnt == 0) || - (gpio_get_value(ESC_KEY) && - gpio_get_value(PUSH_KEY) && cnt == 0)) { - lcd_position_cursor(1, 8); - lcd_puts( - "starting script from network ... "); - setenv("bootcmd", "run netscript"); - cnt = 4; - break; - } else if (!gpio_get_value(ESC_KEY)) { - break; - } - } while (cnt); - } else if (scratchreg == 0xCC) { - lcd_position_cursor(1, 8); - lcd_puts( - "starting vxworks from network ... "); - setenv("bootcmd", "run netboot"); - cnt = 4; - } else if (scratchreg == 0xCD) { - lcd_position_cursor(1, 8); - lcd_puts( - "starting script from network ... "); - setenv("bootcmd", "run netscript"); - cnt = 4; - } else if (scratchreg == 0xCE) { - lcd_position_cursor(1, 8); - lcd_puts( - "starting AR from eMMC ... "); - setenv("bootcmd", "run mmcboot"); - cnt = 4; - } - - lcd_position_cursor(1, 8); - switch (cnt) { - case 0: - lcd_puts("entering BOOT-mode. "); - setenv("bootcmd", "run defaultAR"); - buf = 0x0000; - break; - case 1: - lcd_puts("entering DIAGNOSE-mode. "); - buf = 0x0F0F; - break; - case 2: - lcd_puts("entering SERVICE mode. "); - buf = 0xB4B4; - break; - case 3: - lcd_puts("loading OS... "); - buf = 0x0404; - break; - } - /* write bootinfo into scratchregister of resetcontroller */ - oldspeed = i2c_get_bus_speed(); - if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { - i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, - (uint8_t *)&buf, sizeof(buf)); - i2c_set_bus_speed(oldspeed); - } else { - puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n"); - } - /* setup othbootargs for bootvx-command (vxWorks bootline) */ - char othbootargs[128]; - snprintf(othbootargs, sizeof(othbootargs), - "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x", - (unsigned int) gd->fb_base-0x20, - (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20), - (u32)getenv_ulong("vx_romfsbase", 16, 0), - (u32)getenv_ulong("vx_romfssize", 16, 0)); - setenv("othbootargs", othbootargs); - /* - * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does - * expect that vectors are there, original u-boot moves them to _start - */ - __asm__("ldr r0,=0x20000"); - __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */ - - return 0; -} -#endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c deleted file mode 100644 index 40224f76f6..0000000000 --- a/board/BuR/kwb/mux.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * mux.c - * - * Pinmux Setting for B&R LEIT Board(s) - * - * Copyright (C) 2013 Hannes Schmelzer - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -static struct module_pin_mux spi0_pin_mux[] = { - /* SPI1_SCLK */ - {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE}, - /* SPI1_D0 */ - {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE}, - /* SPI1_D1 */ - {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE}, - /* SPI1_CS0 */ - {OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE}, - /* SPI1_CS1 */ - {OFFSET(spi0_cs1), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE}, - {-1}, -}; - -static struct module_pin_mux dcan0_pin_mux[] = { - /* DCAN0 TX */ - {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN}, - /* DCAN0 RX */ - {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE}, - {-1}, -}; - -static struct module_pin_mux dcan1_pin_mux[] = { - /* DCAN1 TX */ - {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN}, - /* DCAN1 RX */ - {OFFSET(uart1_txd), MODE(2) | RXACTIVE}, - {-1}, -}; - -static struct module_pin_mux gpios[] = { - /* GPIO0_7 (PWW0 OUT) - CAN TERM */ - {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)}, - /* GPIO0_19 (DMA_INTR0) - TA602 */ - {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)}, - /* GPIO0_20 (DMA_INTR1) - SPI0 nCS1 */ - {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)}, - /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ - {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)}, - /* GPIO0_30 (GPMC_WAIT0) - TA601 */ - {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)}, - /* GPIO0_31 (GPMC_nWP) - SW601 PushButton */ - {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)}, - /* GPIO1_28 (GPMC_nWE) - FRAM_nWP */ - {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)}, - /* GPIO1_29 (gpmc_csn0) - MMC nRST */ - {OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)}, - /* GPIO2_0 (GPMC_nCS3) - VBAT_OK */ - {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, - /* GPIO2_2 (GPMC_nADV_ALE) - DCOK */ - {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)}, - /* GPIO2_4 (GPMC_nWE) - TST_BAST */ - {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)}, - /* GPIO2_5 (gpmc_be0n_cle) - DISPLAY_ON_OFF */ - {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)}, - /* GPIO3_16 (mcasp0_axr0) - ETH-LED green */ - {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)}, - /* GPIO3_17 (mcasp0_ahclkr) - CAN_STB */ - {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)}, - /* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */ - {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)}, - /* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */ - {OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)}, - /* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */ - {OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)}, - {-1}, -}; - -static struct module_pin_mux uart0_pin_mux[] = { - /* UART0_CTS */ - {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* UART0_RXD */ - {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, - /* UART0_TXD */ - {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, - {-1}, -}; - -static struct module_pin_mux i2c0_pin_mux[] = { - /* I2C_DATA */ - {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, - /* I2C_SCLK */ - {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, - {-1}, -}; - -static struct module_pin_mux mii1_pin_mux[] = { - {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ - {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ - {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ - {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ - {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ - {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ - {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ - {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ - {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ - {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ - {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ - {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ - {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ - {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ - {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ - {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ - {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ - {-1}, -}; - -static struct module_pin_mux mmc1_pin_mux[] = { - {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ - {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ - {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ - {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ - {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ - {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ - {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ - {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ - {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ - {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ - {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ - {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ - - {-1}, -}; - -static struct module_pin_mux lcd_pin_mux[] = { - {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */ - {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */ - {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */ - {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */ - {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */ - {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */ - {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */ - {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */ - {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */ - {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */ - {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */ - {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */ - {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */ - {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */ - {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */ - {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */ - - {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */ - {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */ - {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */ - {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */ - {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */ - {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */ - {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */ - {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */ - - {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */ - {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */ - {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */ - {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */ - - {-1}, -}; - -void enable_uart0_pin_mux(void) -{ - configure_module_pin_mux(uart0_pin_mux); -} - -void enable_i2c_pin_mux(void) -{ - configure_module_pin_mux(i2c0_pin_mux); -} - -void enable_board_pin_mux(void) -{ - configure_module_pin_mux(i2c0_pin_mux); - configure_module_pin_mux(mii1_pin_mux); - configure_module_pin_mux(spi0_pin_mux); - configure_module_pin_mux(dcan0_pin_mux); - configure_module_pin_mux(dcan1_pin_mux); - configure_module_pin_mux(mmc1_pin_mux); - configure_module_pin_mux(lcd_pin_mux); - configure_module_pin_mux(gpios); -} -- cgit v1.2.1