From 952e7760bfc5b0e3b142b9ce34e7fbb7d008c900 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 24 Sep 2009 09:55:50 +0200 Subject: ppc4xx: Convert PPC4xx UIC defines from lower case to upper case The latest PPC4xx register cleanup patch missed the UIC defines. This patch now changes lower case UIC defines to upper case. Signed-off-by: Stefan Roese --- board/amcc/acadia/acadia.c | 12 ++--- board/amcc/bamboo/bamboo.c | 30 ++++++------- board/amcc/bubinga/bubinga.c | 12 ++--- board/amcc/canyonlands/canyonlands.c | 62 ++++++++++++------------- board/amcc/ebony/ebony.c | 28 ++++++------ board/amcc/katmai/katmai.c | 72 +++++++++++++++--------------- board/amcc/kilauea/kilauea.c | 52 ++++++++++----------- board/amcc/luan/luan.c | 34 +++++++------- board/amcc/makalu/makalu.c | 48 ++++++++++---------- board/amcc/ocotea/ocotea.c | 60 ++++++++++++------------- board/amcc/redwood/redwood.c | 60 ++++++++++++------------- board/amcc/sequoia/sequoia.c | 46 +++++++++---------- board/amcc/taihu/taihu.c | 14 +++--- board/amcc/taishan/taishan.c | 60 ++++++++++++------------- board/amcc/walnut/walnut.c | 14 +++--- board/amcc/yosemite/yosemite.c | 30 ++++++------- board/amcc/yucca/yucca.c | 64 +++++++++++++------------- board/cray/L1/L1.c | 14 +++--- board/csb272/csb272.c | 14 +++--- board/csb472/csb472.c | 14 +++--- board/dave/PPChameleonEVB/PPChameleonEVB.c | 14 +++--- board/eric/eric.c | 14 +++--- board/esd/apc405/apc405.c | 14 +++--- board/esd/ar405/ar405.c | 14 +++--- board/esd/ash405/ash405.c | 14 +++--- board/esd/canbt/canbt.c | 14 +++--- board/esd/cms700/cms700.c | 14 +++--- board/esd/cpci2dp/cpci2dp.c | 16 +++---- board/esd/cpci405/cpci405.c | 18 ++++---- board/esd/cpciiser4/cpciiser4.c | 16 +++---- board/esd/dp405/dp405.c | 14 +++--- board/esd/du405/du405.c | 14 +++--- board/esd/du440/du440.c | 42 ++++++++--------- board/esd/hh405/hh405.c | 14 +++--- board/esd/hub405/hub405.c | 14 +++--- board/esd/ocrtc/ocrtc.c | 14 +++--- board/esd/pci405/pci405.c | 16 +++---- board/esd/plu405/plu405.c | 14 +++--- board/esd/pmc405/pmc405.c | 14 +++--- board/esd/pmc405de/pmc405de.c | 14 +++--- board/esd/pmc440/pmc440.c | 46 +++++++++---------- board/esd/voh405/voh405.c | 14 +++--- board/esd/vom405/vom405.c | 14 +++--- board/esd/wuh405/wuh405.c | 14 +++--- board/exbitgen/exbitgen.c | 14 +++--- board/g2000/g2000.c | 26 +++++------ board/gdsys/dlvision/dlvision.c | 14 +++--- board/gdsys/gdppc440etx/gdppc440etx.c | 30 ++++++------- board/gdsys/intip/intip.c | 62 ++++++++++++------------- board/gdsys/neo/neo.c | 14 +++--- board/jse/jse.c | 12 ++--- board/korat/korat.c | 46 +++++++++---------- board/lwmon5/lwmon5.c | 46 +++++++++---------- board/mpl/mip405/mip405.c | 14 +++--- board/mpl/pip405/pip405.c | 14 +++--- board/netstal/hcu4/hcu4.c | 12 ++--- board/netstal/hcu5/hcu5.c | 46 +++++++++---------- board/netstal/mcu25/mcu25.c | 12 ++--- board/pcs440ep/pcs440ep.c | 30 ++++++------- board/prodrive/alpr/alpr.c | 60 ++++++++++++------------- board/prodrive/p3p440/p3p440.c | 30 ++++++------- board/quad100hd/quad100hd.c | 14 +++--- board/sandburst/karef/karef.c | 60 ++++++++++++------------- board/sandburst/metrobox/metrobox.c | 60 ++++++++++++------------- board/sbc405/sbc405.c | 14 +++--- board/sc3/sc3.c | 18 ++++---- board/w7o/w7o.c | 28 ++++++------ board/xes/xpedite1000/xpedite1000.c | 60 ++++++++++++------------- board/zeus/zeus.c | 14 +++--- 69 files changed, 948 insertions(+), 948 deletions(-) (limited to 'board') diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 0db619952e..482561122a 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -78,12 +78,12 @@ int board_early_init_f(void) mfsdr(SDR0_ULTRA1, reg); mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE); - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000010); - mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */ - mtdcr(uictr, 0x00000010); /* set int trigger levels */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000010); + mtdcr(UIC0PR, 0xFE7FFFF0); /* set int polarities */ + mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 2ffd720d5c..38186a5d37 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -392,21 +392,21 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ + mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ /*-------------------------------------------------------------------- * Setup the GPIO pins diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c index d0aebec2cd..49eadb9212 100644 --- a/board/amcc/bubinga/bubinga.c +++ b/board/amcc/bubinga/bubinga.c @@ -29,12 +29,12 @@ long int spd_sdram(void); int board_early_init_f(void) { - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000010); - mtdcr(uicpr, 0xFFFF7FF0); /* set int polarities */ - mtdcr(uictr, 0x00000010); /* set int trigger levels */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000010); + mtdcr(UIC0PR, 0xFFFF7FF0); /* set int polarities */ + mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * Configure CPC0_PCI to enable PerWE as output diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 3a03f30731..f359d2377a 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -116,37 +116,37 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ - - mtdcr(uic3sr, 0xffffffff); /* clear all */ - mtdcr(uic3er, 0x00000000); /* disable all */ - mtdcr(uic3cr, 0x00000000); /* all non-critical */ - mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic3tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic3sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + mtdcr(UIC3ER, 0x00000000); /* disable all */ + mtdcr(UIC3CR, 0x00000000); /* all non-critical */ + mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ #if !defined(CONFIG_ARCHES) /* SDR Setting - enable NDFC */ diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index 2439b03a9f..0543bad138 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -71,21 +71,21 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ + mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ return 0; } diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index 1a45056daa..bcef707403 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -183,42 +183,42 @@ int board_early_init_f (void) * Set critical interrupt values. Set interrupt polarities. Set interrupt * trigger levels. Make bit 0 High priority. Clear all interrupts again. *------------------------------------------------------------------------*/ - mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic3er, 0x00000000); /* disable all interrupts */ - mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical interrupts: */ - mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities*/ - mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic3sr, 0x00000000); /* clear all interrupts*/ - mtdcr (uic3sr, 0xffffffff); /* clear all interrupts*/ - - - mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic2er, 0x00000000); /* disable all interrupts*/ - mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts*/ - mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities*/ - mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ - - mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts*/ - mtdcr (uic1er, 0x00000000); /* disable all interrupts*/ - mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts*/ - mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels*/ - mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic1sr, 0x00000000); /* clear all interrupts*/ - mtdcr (uic1sr, 0xffffffff); /* clear all interrupts*/ - - mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted cascade to be checked */ - mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical interrupts*/ - mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities*/ - mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */ - mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/ - mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/ + mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical interrupts: */ + mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/ + mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ + mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC3SR, 0x00000000); /* clear all interrupts*/ + mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts*/ + + + mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC2ER, 0x00000000); /* disable all interrupts*/ + mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts*/ + mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/ + mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ + mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ + + mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts*/ + mtdcr (UIC1ER, 0x00000000); /* disable all interrupts*/ + mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts*/ + mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/ + mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC1SR, 0x00000000); /* clear all interrupts*/ + mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts*/ + + mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted cascade to be checked */ + mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical interrupts*/ + mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/ + mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ + mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC0SR, 0x00000000); /* clear all interrupts*/ + mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts*/ mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index 7e84a61a96..5ebe69272c 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -158,33 +158,33 @@ int board_early_init_f (void) | interrupts again. +-------------------------------------------------------------------*/ - mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic2er, 0x00000000); /* disable all interrupts */ - mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */ - mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */ - mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ - - mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic1er, 0x00000000); /* disable all interrupts */ - mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */ - mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */ - mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic1sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */ - - mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ + mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ + mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ + + mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ + mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ + mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ + + mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */ /* Except cascade UIC0 and UIC1 */ - mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */ - mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */ - mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ + mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ + mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ /* * Note: Some cores are still in reset when the chip starts, so diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 71ad89fa6c..5f76672fb5 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -49,23 +49,23 @@ int board_early_init_f(void) mtebc( PB2AP, 0x03800000 ); mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ - mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */ - mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */ - mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */ - mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */ - mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */ - mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ - mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */ - mtdcr( uic1sr, 0xffffffff ); - - mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */ - mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */ - mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */ - mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */ - mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */ - mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ - mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ - mtdcr( uic0sr, 0xffffffff ); + mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */ + mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */ + mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */ + mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */ + mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */ + mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ + mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */ + mtdcr( UIC1SR, 0xffffffff ); + + mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */ + mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */ + mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */ + mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */ + mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */ + mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ + mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */ + mtdcr( UIC0SR, 0xffffffff ); mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c index 9fc0ec6667..fb0e7b75eb 100644 --- a/board/amcc/makalu/makalu.c +++ b/board/amcc/makalu/makalu.c @@ -159,33 +159,33 @@ int board_early_init_f (void) | interrupts again. +-------------------------------------------------------------------*/ - mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic2er, 0x00000000); /* disable all interrupts */ - mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */ - mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */ - mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ + mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ + mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic1er, 0x00000000); /* disable all interrupts */ - mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */ - mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */ - mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic1sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ + mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ + mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */ + mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */ /* Except cascade UIC0 and UIC1 */ - mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */ - mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */ - mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ + mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ + mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ /* * Note: Some cores are still in reset when the chip starts, so diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 5e32e8a784..8513f43a8f 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -159,36 +159,36 @@ int board_early_init_f (void) * UIC2 UIC1 * UIC3 UIC2 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */ - mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - - mtdcr (uic3sr, 0xffffffff); /* clear all */ - mtdcr (uic3er, 0x00000000); /* disable all */ - mtdcr (uic3cr, 0x00000000); /* all non-critical */ - mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ - mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ - - mtdcr (uic0sr, 0xfc000000); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non-critical */ - mtdcr (uic0pr, 0xfc000000); /* */ - mtdcr (uic0tr, 0x00000000); /* */ - mtdcr (uic0vr, 0x00000001); /* */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + mtdcr (UIC1ER, 0x00000000); /* disable all */ + mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */ + mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */ + mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + mtdcr (UIC2ER, 0x00000000); /* disable all */ + mtdcr (UIC2CR, 0x00000000); /* all non-critical */ + mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ + mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + mtdcr (UIC3ER, 0x00000000); /* disable all */ + mtdcr (UIC3CR, 0x00000000); /* all non-critical */ + mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + + mtdcr (UIC0SR, 0xfc000000); /* clear all */ + mtdcr (UIC0ER, 0x00000000); /* disable all */ + mtdcr (UIC0CR, 0x00000000); /* all non-critical */ + mtdcr (UIC0PR, 0xfc000000); /* */ + mtdcr (UIC0TR, 0x00000000); /* */ + mtdcr (UIC0VR, 0x00000001); /* */ mfsdr (SDR0_MFR, mfr); mfr &= ~SDR0_MFR_ECS_MASK; /* mtsdr(SDR0_MFR, mfr); */ diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c index 49078ebee2..bc8cb0c443 100644 --- a/board/amcc/redwood/redwood.c +++ b/board/amcc/redwood/redwood.c @@ -416,41 +416,41 @@ static void early_init_UIC(void) * interrupt trigger levels. Make bit 0 High priority. Clear all * interrupts again. */ - mtdcr(uic3sr, 0xffffffff); /* Clear all interrupts */ - mtdcr(uic3er, 0x00000000); /* disable all interrupts */ - mtdcr(uic3cr, 0x00000000); /* Set Critical / Non Critical + mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr(uic3pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr(uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic3sr, 0xffffffff); /* clear all interrupts */ - - mtdcr(uic2sr, 0xffffffff); /* Clear all interrupts */ - mtdcr(uic2er, 0x00000000); /* disable all interrupts */ - mtdcr(uic2cr, 0x00000000); /* Set Critical / Non Critical + mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ + mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts */ + + mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr(uic2pr, 0xebebebff); /* Set Interrupt Polarities */ - mtdcr(uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all interrupts */ - - mtdcr(uic1sr, 0xffffffff); /* Clear all interrupts */ - mtdcr(uic1er, 0x00000000); /* disable all interrupts */ - mtdcr(uic1cr, 0x00000000); /* Set Critical / Non Critical + mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities */ + mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ + + mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr(uic1pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr(uic1tr, 0x001fc0ff); /* Set Interrupt Trigger Levels */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all interrupts */ + mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr(UIC1TR, 0x001fc0ff); /* Set Interrupt Trigger Levels */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */ - mtdcr(uic0sr, 0xffffffff); /* Clear all interrupts */ - mtdcr(uic0er, 0x00000000); /* disable all interrupts excepted + mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC0ER, 0x00000000); /* disable all interrupts excepted * cascade to be checked */ - mtdcr(uic0cr, 0x00104001); /* Set Critical / Non Critical + mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical * interrupts */ - mtdcr(uic0pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr(uic0tr, 0x000f003c); /* Set Interrupt Trigger Levels */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all interrupts */ + mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr(UIC0TR, 0x000f003c); /* Set Interrupt Trigger Levels */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */ } diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 5913455ba1..17f831c3f4 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -52,29 +52,29 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ /* 50MHz tmrclk */ out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00); diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c index 4e5796ee82..be381d60ac 100644 --- a/board/amcc/taihu/taihu.c +++ b/board/amcc/taihu/taihu.c @@ -40,13 +40,13 @@ int board_early_init_f(void) { lcd_init(); - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); - mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */ - mtdcr(uictr, 0x00000000); /* set int trigger levels */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); + mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */ + mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR); diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index 086778a652..4a0573eb38 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -132,36 +132,36 @@ int board_early_init_f (void) * UIC2 UIC1 * UIC3 UIC2 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */ - mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - - mtdcr (uic3sr, 0xffffffff); /* clear all */ - mtdcr (uic3er, 0x00000000); /* disable all */ - mtdcr (uic3cr, 0x00000000); /* all non-critical */ - mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ - mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ - - mtdcr (uic0sr, 0xfc000000); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non-critical */ - mtdcr (uic0pr, 0xfc000000); /* */ - mtdcr (uic0tr, 0x00000000); /* */ - mtdcr (uic0vr, 0x00000001); /* */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + mtdcr (UIC1ER, 0x00000000); /* disable all */ + mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */ + mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */ + mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + mtdcr (UIC2ER, 0x00000000); /* disable all */ + mtdcr (UIC2CR, 0x00000000); /* all non-critical */ + mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ + mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + mtdcr (UIC3ER, 0x00000000); /* disable all */ + mtdcr (UIC3CR, 0x00000000); /* all non-critical */ + mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + + mtdcr (UIC0SR, 0xfc000000); /* clear all */ + mtdcr (UIC0ER, 0x00000000); /* disable all */ + mtdcr (UIC0CR, 0x00000000); /* all non-critical */ + mtdcr (UIC0PR, 0xfc000000); /* */ + mtdcr (UIC0TR, 0x00000000); /* */ + mtdcr (UIC0VR, 0x00000001); /* */ /* Enable two GPIO 10~11 and TraceA signal */ mfsdr(SDR0_PFC0,reg); diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c index 28dcb66ebc..4f299324cd 100644 --- a/board/amcc/walnut/walnut.c +++ b/board/amcc/walnut/walnut.c @@ -47,13 +47,13 @@ int board_early_init_f(void) | +-------------------------------------------------------------------------*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr(uicpr, 0xFFFFFFE0); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ + mtdcr(UIC0PR, 0xFFFFFFE0); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* set UART1 control to select CTS/RTS */ #define FPGA_BRDC 0xF0300004 diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 2a654fa895..731d441526 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -82,21 +82,21 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ + mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ /*-------------------------------------------------------------------- * Setup other serial configuration diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 245004cee8..033bdd20fa 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -485,50 +485,50 @@ int board_early_init_f (void) | interrupt trigger levels. Make bit 0 High priority. Clear all | interrupts again. +-------------------------------------------------------------------*/ - mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic3er, 0x00000000); /* disable all interrupts */ - mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical + mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ + mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic3sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic3sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic2er, 0x00000000); /* disable all interrupts */ - mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical + mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities */ - mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */ + mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ + mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic1er, 0x00000000); /* disable all interrupts */ - mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical + mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels */ - mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */ + mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic1sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted + mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted * cascade to be checked */ - mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical + mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical * interrupts */ - mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */ - mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest + mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ + mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ - mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c index 5d1c4170dd..79130711d4 100644 --- a/board/cray/L1/L1.c +++ b/board/cray/L1/L1.c @@ -113,13 +113,13 @@ int board_early_init_f (void) { /* Running from ROM: global data is still READONLY */ init_sdram (); - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFFE0); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index cb24cd4ffe..740e3ac6f5 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -87,13 +87,13 @@ int board_early_init_f(void) | +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */ diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c index fa0fa193e8..0c7760a02f 100644 --- a/board/csb472/csb472.c +++ b/board/csb472/csb472.c @@ -55,13 +55,13 @@ int board_early_init_f(void) | +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */ diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c index 56751e1599..06de6e0b1d 100644 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -53,13 +53,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) * IRQ 31 (EXT IRQ 6) */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/eric/eric.c b/board/eric/eric.c index bc2a907f6b..cfcfa525a9 100644 --- a/board/eric/eric.c +++ b/board/eric/eric.c @@ -62,13 +62,13 @@ int board_early_init_f (void) | +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all SMI to be non-critical */ - mtdcr (uicpr, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */ - mtdcr (uictr, 0x10000000); /* set int trigger levels, UART0 is EDGE */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all SMI to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels, UART0 is EDGE */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr (CPC0_CR0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */ diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c index 46622a29fd..409a0540bf 100644 --- a/board/esd/apc405/apc405.c +++ b/board/esd/apc405/apc405.c @@ -155,13 +155,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0 */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0 */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c index 9d1b6d2644..a632cb42d6 100644 --- a/board/esd/ar405/ar405.c +++ b/board/esd/ar405/ar405.c @@ -130,13 +130,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */ diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 8da08facff..5f0e67cbb4 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -66,13 +66,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c index 418d3e237e..5a3f61de3c 100644 --- a/board/esd/canbt/canbt.c +++ b/board/esd/canbt/canbt.c @@ -134,13 +134,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index 7a92401893..391fbf4c1b 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -45,13 +45,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index 00c7024a85..6d9814f163 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -58,14 +58,14 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) unused */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ + + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 4c9ed2fa58..c29c876d61 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -179,22 +179,22 @@ int board_early_init_f(void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ #if defined(CONFIG_CPCI405_6U) if (cpci405_version() == 3) { - mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ + mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */ } else { - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ } #else - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ #endif - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0, + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, * INT0 highest priority */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c index 6e97392c4b..ee90e2c28a 100644 --- a/board/esd/cpciiser4/cpciiser4.c +++ b/board/esd/cpciiser4/cpciiser4.c @@ -129,14 +129,14 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - /* mtdcr(uicpr, 0xFFFFFF81); / set int polarities */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + /* mtdcr(UIC0PR, 0xFFFFFF81); / set int polarities */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c index fc0d091bca..228a57057a 100644 --- a/board/esd/dp405/dp405.c +++ b/board/esd/dp405/dp405.c @@ -43,13 +43,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c index 28a50c7b0e..f475d11072 100644 --- a/board/esd/du405/du405.c +++ b/board/esd/du405/du405.c @@ -124,13 +124,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFFB1); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFFB1); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 100 us diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 376de98354..056f455d68 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -87,37 +87,37 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ /* * UIC1: * bit30: ext. Irq 1: PLD : int 32+30 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xfffffffd); - mtdcr(uic1tr, 0x00000000); - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xfffffffd); + mtdcr(UIC1TR, 0x00000000); + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ /* * UIC2 * bit3: ext. Irq 2: DCF77 : int 64+3 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ /* select Ethernet pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index b72b716ddf..132531b39c 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -363,13 +363,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index acb23dad1f..2a2c4343c0 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -86,13 +86,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c index 709bcdd980..ab909e5030 100644 --- a/board/esd/ocrtc/ocrtc.c +++ b/board/esd/ocrtc/ocrtc.c @@ -45,13 +45,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: clear EBTC -> high-Z ebc signals between diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index 04bc569ead..34a1632401 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -155,13 +155,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * Setup GPIO pins (IRQ4/GPIO21 as GPIO) @@ -271,7 +271,7 @@ int misc_init_r (void) pci_write_config_dword(PCIDEVID_405GP, i, *ptr++); } } - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ *magic = 0; /* clear pci reconfig magic again */ } diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index a3c1cec6ef..f14ef7a20f 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -78,13 +78,13 @@ int board_early_init_f(void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index 5ff87e7a25..e7415e44cb 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -48,13 +48,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest priority */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c index 419311aec8..3725ece394 100644 --- a/board/esd/pmc405de/pmc405de.c +++ b/board/esd/pmc405de/pmc405de.c @@ -114,13 +114,13 @@ int board_early_init_f(void) * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest prio */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest prio */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 119cbf2627..f0f9bff3eb 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -148,29 +148,29 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffff7ef); - mtdcr(uic0tr, 0x00000000); - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffc7f5); - mtdcr(uic1tr, 0x00000000); - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0x27ffffff); - mtdcr(uic2tr, 0x00000000); - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffff7ef); + mtdcr(UIC0TR, 0x00000000); + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffc7f5); + mtdcr(UIC1TR, 0x00000000); + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0x27ffffff); + mtdcr(UIC2TR, 0x00000000); + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ /* select Ethernet pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 7477f56b2b..3f81665eb2 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -88,13 +88,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFFB5); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFFB5); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c index de9c7b974c..fb48022659 100644 --- a/board/esd/vom405/vom405.c +++ b/board/esd/vom405/vom405.c @@ -45,13 +45,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index e86f1d0abc..f2591d57f4 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -64,13 +64,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c index 0f8412776b..ce6469d29e 100644 --- a/board/exbitgen/exbitgen.c +++ b/board/exbitgen/exbitgen.c @@ -37,13 +37,13 @@ int board_early_init_f (void) | +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr (uicpr, 0xFFFFFF90); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF90); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* Perform reset of PHY connected to PPC via register in CPLD */ out8 (PHY_CTRL_ADDR, 0x2e); /* activate nRESET,FDX,F100,ANEN, enable output */ diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index ae258e1f26..8afffdc737 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -38,20 +38,20 @@ int board_early_init_f (void) { #if 0 /* test-only */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000010); - mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */ - mtdcr (uictr, 0x00000010); /* set int trigger levels */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000010); + mtdcr (UIC0PR, 0xFFFF7FF0); /* set int polarities */ + mtdcr (UIC0TR, 0x00000010); /* set int trigger levels */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ #else - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFFF0); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFFF0); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ #endif #if 1 /* test-only */ diff --git a/board/gdsys/dlvision/dlvision.c b/board/gdsys/dlvision/dlvision.c index 5246bc8c4f..ff5f183235 100644 --- a/board/gdsys/dlvision/dlvision.c +++ b/board/gdsys/dlvision/dlvision.c @@ -36,13 +36,13 @@ enum { int board_early_init_f(void) { - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c index 27c159bec6..7cc1bf2678 100644 --- a/board/gdsys/gdppc440etx/gdppc440etx.c +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -83,21 +83,21 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ + mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ /* * Setup other serial configuration diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c index 0de1be8579..2cd2e6d450 100644 --- a/board/gdsys/intip/intip.c +++ b/board/gdsys/intip/intip.c @@ -44,37 +44,37 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ - - mtdcr(uic3sr, 0xffffffff); /* clear all */ - mtdcr(uic3er, 0x00000000); /* disable all */ - mtdcr(uic3cr, 0x00000000); /* all non-critical */ - mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic3tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic3sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + mtdcr(UIC3ER, 0x00000000); /* disable all */ + mtdcr(UIC3CR, 0x00000000); /* all non-critical */ + mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ /* * Configure PFC (Pin Function Control) registers diff --git a/board/gdsys/neo/neo.c b/board/gdsys/neo/neo.c index 628ce3dc90..a56c2cc987 100644 --- a/board/gdsys/neo/neo.c +++ b/board/gdsys/neo/neo.c @@ -31,13 +31,13 @@ int board_early_init_f(void) { - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks diff --git a/board/jse/jse.c b/board/jse/jse.c index 6dc9a01af8..1849ca47d7 100644 --- a/board/jse/jse.c +++ b/board/jse/jse.c @@ -48,12 +48,12 @@ int board_early_init_f (void) | IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused) | IRQ 31 (EXT IRQ 6) (unused) +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF87); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* Configure the interface to the SystemACE MCU port. The SystemACE is fast, but there is no reason to have diff --git a/board/korat/korat.c b/board/korat/korat.c index 3d4d149f6c..40a097cef5 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -87,29 +87,29 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ /* * Take sim card reader and CF controller out of reset. Also enable PHY diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index a9c2a6f441..f4090f40dd 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -44,29 +44,29 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */ - mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */ - mtdcr(uic0tr, 0x00000900); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */ - mtdcr(uic1tr, 0x60000040); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */ - mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */ + mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */ + mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */ + mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */ + mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ /* Trace Pins are disabled. SDR0_PFC0 Register */ mtsdr(SDR0_PFC0, 0x0); diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index d8279e81c9..b87df01fec 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -489,13 +489,13 @@ int board_early_init_f (void) | caused the interrupt. | +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index e00d1d08f5..c2d6c6fbcf 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -552,13 +552,13 @@ int board_early_init_f (void) | caused the interrupt. | +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index 40bec8edcc..ba3e9c3cff 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -58,12 +58,12 @@ int board_early_init_f (void) * IRQ 17-24 RESERVED/UNUSED * IRQ 31 (EXT IRQ 6) (unused) */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr(uicpr, 0xFFFFE000); /* set int polarities */ - mtdcr(uictr, 0x00000000); /* set int trigger levels */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */ + mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr(CPC0_CR1, CPC0_CR1_VALUE); mtdcr(CPC0_ECR, 0x60606000); diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 836c0346da..4522612dae 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -129,29 +129,29 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */ mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */ diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c index 9054282c94..945d79aa20 100644 --- a/board/netstal/mcu25/mcu25.c +++ b/board/netstal/mcu25/mcu25.c @@ -64,12 +64,12 @@ int board_early_init_f (void) * IRQ 17-24 RESERVED/UNUSED * IRQ 31 (EXT IRQ 6) (unused) */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr(uicpr, 0xFFFFE000); /* set int polarities */ - mtdcr(uictr, 0x00000000); /* set int trigger levels */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */ + mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr(CPC0_CR1, CPC0_CR1_VALUE); mtdcr(CPC0_ECR, 0x60606000); diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index f966d02f10..ac059a903b 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -155,21 +155,21 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */ - mtdcr(uic0pr, 0xfffffe1f); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */ + mtdcr(UIC0PR, 0xfffffe1f); /* per ref-board manual */ + mtdcr(UIC0TR, 0x01c00000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ /*-------------------------------------------------------------------- * Setup other serial configuration diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index be79b42bd0..cdb91ac36b 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -60,36 +60,36 @@ int board_early_init_f (void) * UIC2 UIC1 * UIC3 UIC2 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic1pr, 0xfffffe03); /* per manual */ - mtdcr (uic1tr, 0x01c00000); /* per manual */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - - mtdcr (uic3sr, 0xffffffff); /* clear all */ - mtdcr (uic3er, 0x00000000); /* disable all */ - mtdcr (uic3cr, 0x00000000); /* all non-critical */ - mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ - mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ - - mtdcr (uic0sr, 0xfc000000); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non-critical */ - mtdcr (uic0pr, 0xfc000000); /* */ - mtdcr (uic0tr, 0x00000000); /* */ - mtdcr (uic0vr, 0x00000001); /* */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + mtdcr (UIC1ER, 0x00000000); /* disable all */ + mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (UIC1PR, 0xfffffe03); /* per manual */ + mtdcr (UIC1TR, 0x01c00000); /* per manual */ + mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + mtdcr (UIC2ER, 0x00000000); /* disable all */ + mtdcr (UIC2CR, 0x00000000); /* all non-critical */ + mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ + mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + mtdcr (UIC3ER, 0x00000000); /* disable all */ + mtdcr (UIC3CR, 0x00000000); /* all non-critical */ + mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + + mtdcr (UIC0SR, 0xfc000000); /* clear all */ + mtdcr (UIC0ER, 0x00000000); /* disable all */ + mtdcr (UIC0CR, 0x00000000); /* all non-critical */ + mtdcr (UIC0PR, 0xfc000000); /* */ + mtdcr (UIC0TR, 0x00000000); /* */ + mtdcr (UIC0VR, 0x00000001); /* */ /* Setup shutdown/SSD empty interrupt as inputs */ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index 18054e45b6..20fd4dc276 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -101,21 +101,21 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */ + mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ + mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ return 0; } diff --git a/board/quad100hd/quad100hd.c b/board/quad100hd/quad100hd.c index ffc47de25d..f878c49bfa 100644 --- a/board/quad100hd/quad100hd.c +++ b/board/quad100hd/quad100hd.c @@ -40,13 +40,13 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { /* taken from PPCBoot */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); - mtdcr(uicpr, 0xFFFF7FFE); /* set int polarities */ - mtdcr(uictr, 0x00000000); /* set int trigger levels */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); + mtdcr(UIC0PR, 0xFFFF7FFE); /* set int polarities */ + mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ mtdcr(CPC0_SRR, 0x00040000); /* Hold PCI bridge in reset */ diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c index b80c206940..92b15aa50f 100644 --- a/board/sandburst/karef/karef.c +++ b/board/sandburst/karef/karef.c @@ -212,36 +212,36 @@ int board_early_init_f (void) * UIC2 UIC1 * UIC3 UIC2 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non- critical */ - mtdcr (uic1pr, 0xfffffe03); /* polarity */ - mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffc8ff); /* polarity */ - mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - - mtdcr (uic3sr, 0xffffffff); /* clear all */ - mtdcr (uic3er, 0x00000000); /* disable all */ - mtdcr (uic3cr, 0x00000000); /* all non-critical */ - mtdcr (uic3pr, 0xffff83ff); /* polarity */ - mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */ - mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ - - mtdcr (uic0sr, 0xfc000000); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non-critical */ - mtdcr (uic0pr, 0xfc000000); - mtdcr (uic0tr, 0x00000000); - mtdcr (uic0vr, 0x00000001); + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + mtdcr (UIC1ER, 0x00000000); /* disable all */ + mtdcr (UIC1CR, 0x00000000); /* all non- critical */ + mtdcr (UIC1PR, 0xfffffe03); /* polarity */ + mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */ + mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + mtdcr (UIC2ER, 0x00000000); /* disable all */ + mtdcr (UIC2CR, 0x00000000); /* all non-critical */ + mtdcr (UIC2PR, 0xffffc8ff); /* polarity */ + mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */ + mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + mtdcr (UIC3ER, 0x00000000); /* disable all */ + mtdcr (UIC3CR, 0x00000000); /* all non-critical */ + mtdcr (UIC3PR, 0xffff83ff); /* polarity */ + mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + + mtdcr (UIC0SR, 0xfc000000); /* clear all */ + mtdcr (UIC0ER, 0x00000000); /* disable all */ + mtdcr (UIC0CR, 0x00000000); /* all non-critical */ + mtdcr (UIC0PR, 0xfc000000); + mtdcr (UIC0TR, 0x00000000); + mtdcr (UIC0VR, 0x00000001); fpga_init(); diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c index ad3f9bc28e..0c8e6dfb1e 100644 --- a/board/sandburst/metrobox/metrobox.c +++ b/board/sandburst/metrobox/metrobox.c @@ -202,36 +202,36 @@ int board_early_init_f (void) * UIC2 UIC1 * UIC3 UIC2 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non- critical */ - mtdcr (uic1pr, 0xfffffe03); /* polarity */ - mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffc8ff); /* polarity */ - mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - - mtdcr (uic3sr, 0xffffffff); /* clear all */ - mtdcr (uic3er, 0x00000000); /* disable all */ - mtdcr (uic3cr, 0x00000000); /* all non-critical */ - mtdcr (uic3pr, 0xffff83ff); /* polarity */ - mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */ - mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ - - mtdcr (uic0sr, 0xfc000000); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non-critical */ - mtdcr (uic0pr, 0xfc000000); - mtdcr (uic0tr, 0x00000000); - mtdcr (uic0vr, 0x00000001); + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + mtdcr (UIC1ER, 0x00000000); /* disable all */ + mtdcr (UIC1CR, 0x00000000); /* all non- critical */ + mtdcr (UIC1PR, 0xfffffe03); /* polarity */ + mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */ + mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + mtdcr (UIC2ER, 0x00000000); /* disable all */ + mtdcr (UIC2CR, 0x00000000); /* all non-critical */ + mtdcr (UIC2PR, 0xffffc8ff); /* polarity */ + mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */ + mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + mtdcr (UIC3ER, 0x00000000); /* disable all */ + mtdcr (UIC3CR, 0x00000000); /* all non-critical */ + mtdcr (UIC3PR, 0xffff83ff); /* polarity */ + mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + + mtdcr (UIC0SR, 0xfc000000); /* clear all */ + mtdcr (UIC0ER, 0x00000000); /* disable all */ + mtdcr (UIC0CR, 0x00000000); /* all non-critical */ + mtdcr (UIC0PR, 0xfc000000); + mtdcr (UIC0TR, 0x00000000); + mtdcr (UIC0VR, 0x00000001); fpga_init(); diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c index 66842eaf4d..74e6204db9 100644 --- a/board/sbc405/sbc405.c +++ b/board/sbc405/sbc405.c @@ -41,13 +41,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c index 5ae7b1244a..e7772c5ff6 100644 --- a/board/sc3/sc3.c +++ b/board/sc3/sc3.c @@ -294,22 +294,22 @@ int board_early_init_f (void) writeb (cpldConfig_1, CPLD_CONTROL_1); /* disable everything in CPLD */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ if (IS_CAMERON) { sc3_cameron_init(); mtdcr (0x0B6, 0x18000000); - mtdcr (uicpr, 0xFFFFFFF0); - mtdcr (uictr, 0x10001030); + mtdcr (UIC0PR, 0xFFFFFFF0); + mtdcr (UIC0TR, 0x10001030); } else { mtdcr (0x0B6, 0x0000000); - mtdcr (uicpr, 0xFFFFFFE0); - mtdcr (uictr, 0x10000020); + mtdcr (UIC0PR, 0xFFFFFFE0); + mtdcr (UIC0TR, 0x10000020); } - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* setup other implementation specific details */ mtdcr (CPC0_ECR, 0x60606000); diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index 6479beeb13..00a9f98b44 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -64,16 +64,16 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0, + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ #elif defined(CONFIG_W7OLMC) /* @@ -95,16 +95,16 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0, + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ #else /* Unknown */ # error "Unknown W7O board configuration" diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c index 58041fcd34..011fb94bb6 100644 --- a/board/xes/xpedite1000/xpedite1000.c +++ b/board/xes/xpedite1000/xpedite1000.c @@ -74,36 +74,36 @@ int board_early_init_f(void) * UIC2 UIC1 * UIC3 UIC2 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */ - mtdcr(uic1pr, 0xfffffe00); /* per ref-board manual */ - mtdcr(uic1tr, 0x01c00000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffc0ff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00ff8000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ - - mtdcr(uic3sr, 0xffffffff); /* clear all */ - mtdcr(uic3er, 0x00000000); /* disable all */ - mtdcr(uic3cr, 0x00000000); /* all non-critical */ - mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic3tr, 0x00ff8c0f); /* per ref-board manual */ - mtdcr(uic3vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic3sr, 0xffffffff); /* clear all */ - - mtdcr(uic0sr, 0xfc000000); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000000); /* all non-critical */ - mtdcr(uic0pr, 0xfc000000); /* */ - mtdcr(uic0tr, 0x00000000); /* */ - mtdcr(uic0vr, 0x00000001); /* */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000003); /* SMI & UIC1 crit are critical */ + mtdcr(UIC1PR, 0xfffffe00); /* per ref-board manual */ + mtdcr(UIC1TR, 0x01c00000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffc0ff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00ff8000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + mtdcr(UIC3ER, 0x00000000); /* disable all */ + mtdcr(UIC3CR, 0x00000000); /* all non-critical */ + mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC3TR, 0x00ff8c0f); /* per ref-board manual */ + mtdcr(UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + + mtdcr(UIC0SR, 0xfc000000); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000000); /* all non-critical */ + mtdcr(UIC0PR, 0xfc000000); /* */ + mtdcr(UIC0TR, 0x00000000); /* */ + mtdcr(UIC0VR, 0x00000001); /* */ LED0_ON(); diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c index fc9dfa02c0..01273a1f7d 100644 --- a/board/zeus/zeus.c +++ b/board/zeus/zeus.c @@ -50,13 +50,13 @@ static u32 start_time; int board_early_init_f(void) { - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); - mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */ - mtdcr(uictr, 0x00000000); /* set int trigger levels */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); + mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */ + mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ /* * Configure CPC0_PCI to enable PerWE as output -- cgit v1.2.1 From 95b602bab5fec2fffab07a01ea3947c70d1bacc1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 24 Sep 2009 13:59:57 +0200 Subject: ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese --- board/amcc/ebony/ebony.c | 24 +++++++++++------------ board/amcc/ocotea/ocotea.c | 24 +++++++++++------------ board/amcc/yosemite/yosemite.c | 32 +++++++++++++++--------------- board/cray/L1/L1.c | 18 ++++++++--------- board/csb272/csb272.c | 8 ++++---- board/csb272/init.S | 18 ++++++++--------- board/csb472/csb472.c | 8 ++++---- board/csb472/init.S | 18 ++++++++--------- board/eric/init.S | 14 ++++++------- board/exbitgen/exbitgen.c | 8 ++++---- board/exbitgen/init.S | 14 ++++++------- board/g2000/g2000.c | 14 ++++++------- board/jse/sdram.c | 36 +++++++++++++++++----------------- board/mpl/mip405/mip405.c | 38 ++++++++++++++++++------------------ board/mpl/pip405/pip405.c | 36 +++++++++++++++++----------------- board/netstal/common/fixed_sdram.c | 40 +++++++++++++++++++------------------- board/sandburst/common/sb_common.c | 24 +++++++++++------------ board/sc3/sc3.c | 22 ++++++++++----------- board/w7o/init.S | 10 +++++----- board/w7o/w7o.c | 8 ++++---- 20 files changed, 207 insertions(+), 207 deletions(-) (limited to 'board') diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index 0543bad138..e61b5de2d8 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -131,11 +131,11 @@ long int fixed_sdram(void) /*-------------------------------------------------------------------- * Setup some default *------------------------------------------------------------------*/ - mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ - mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ + mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /*-------------------------------------------------------------------- * Setup for board-specific specific mem @@ -143,20 +143,20 @@ long int fixed_sdram(void) /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ - mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram(SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ /* RA=10 RD=3 */ - mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + mtsdram(SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram(SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ udelay(400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ - mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + mtsdram(SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ for (;;) { - mfsdram(mem_mcsts, reg); + mfsdram(SDRAM0_MCSTS, reg); if (reg & 0x80000000) break; } diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 8513f43a8f..d776edabcd 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -241,11 +241,11 @@ long int fixed_sdram (void) /*-------------------------------------------------------------------- * Setup some default *------------------------------------------------------------------*/ - mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ - mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ + mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /*-------------------------------------------------------------------- * Setup for board-specific specific mem @@ -253,20 +253,20 @@ long int fixed_sdram (void) /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ - mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ /* RA=10 RD=3 */ - mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ udelay (400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ - mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ for (;;) { - mfsdram (mem_mcsts, reg); + mfsdram (SDRAM0_MCSTS, reg); if (reg & 0x80000000) break; } diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 731d441526..1ec13eb6b5 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -237,7 +237,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value) /* go through all possible SDRAM0_TR1[RDCT] values */ for (i=0; i<=0x1ff; i++) { /* set the current value for TR1 */ - mtsdram(mem_tr1, (0x80800800 | i)); + mtsdram(SDRAM0_TR1, (0x80800800 | i)); /* write values */ for (j=0; j> 28) & 0x3); */ /* write SDRAM timing for 100MHz. */ - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); mtdcr (SDRAM0_CFGDATA, 0x0086400D); /* write SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); mtdcr (SDRAM0_CFGDATA, 0x05F00000); udelay (200); /* sdram controller.*/ - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); mtdcr (SDRAM0_CFGDATA, 0x90800000); udelay (200); /* initially, disable ECC on all banks */ udelay (200); - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); tmp = mfdcr (SDRAM0_CFGDATA); tmp &= 0xff0fffff; - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); mtdcr (SDRAM0_CFGDATA, tmp); return; @@ -282,15 +282,15 @@ int testdram (void) } printf ("Enable ECC.."); - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); mtdcr (SDRAM0_CFGDATA, tmp); udelay (600); for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L) ; udelay (400); - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); tmp = mfdcr (SDRAM0_CFGDATA); tmp |= 0x00800000; mtdcr (SDRAM0_CFGDATA, tmp); diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index 740e3ac6f5..d6d65cf45c 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -135,28 +135,28 @@ phys_size_t initdram (int board_type) tot_size = 0; - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); diff --git a/board/csb272/init.S b/board/csb272/init.S index 15b26f8bf8..a6b0d4045a 100644 --- a/board/csb272/init.S +++ b/board/csb272/init.S @@ -175,26 +175,26 @@ sdram_init: * Disable memory controller to allow * values to be changed. */ - WDCR_SDRAM(mem_mcopt1, 0x00000000) + WDCR_SDRAM(SDRAM0_CFG, 0x00000000) /* * Configure Memory Banks */ - WDCR_SDRAM(mem_mb0cf, 0x00084001) - WDCR_SDRAM(mem_mb1cf, 0x00000000) - WDCR_SDRAM(mem_mb2cf, 0x00000000) - WDCR_SDRAM(mem_mb3cf, 0x00000000) + WDCR_SDRAM(SDRAM0_B0CR, 0x00084001) + WDCR_SDRAM(SDRAM0_B1CR, 0x00000000) + WDCR_SDRAM(SDRAM0_B2CR, 0x00000000) + WDCR_SDRAM(SDRAM0_B3CR, 0x00000000) /* * Set up SDTR1 (SDRAM Timing Register) */ - WDCR_SDRAM(mem_sdtr1, 0x00854009) + WDCR_SDRAM(SDRAM0_TR, 0x00854009) /* * Set RTR (Refresh Timing Register) */ - WDCR_SDRAM(mem_rtr, 0x10000000) - /* WDCR_SDRAM(mem_rtr, 0x05f00000) */ + WDCR_SDRAM(SDRAM0_RTR, 0x10000000) + /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */ /******************************************************************** * Delay to ensure 200usec have elapsed since reset. Assume worst @@ -210,7 +210,7 @@ sdram_init: /******************************************************************** * Set memory controller options reg, MCOPT1. *******************************************************************/ - WDCR_SDRAM(mem_mcopt1,0x80800000) + WDCR_SDRAM(SDRAM0_CFG,0x80800000) ..sdri_done: blr /* Return to calling function */ diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c index 0c7760a02f..20d34adfdd 100644 --- a/board/csb472/csb472.c +++ b/board/csb472/csb472.c @@ -103,28 +103,28 @@ phys_size_t initdram (int board_type) tot_size = 0; - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); diff --git a/board/csb472/init.S b/board/csb472/init.S index 105cb71bec..b31bd04550 100644 --- a/board/csb472/init.S +++ b/board/csb472/init.S @@ -171,26 +171,26 @@ sdram_init: * Disable memory controller to allow * values to be changed. */ - WDCR_SDRAM(mem_mcopt1, 0x00000000) + WDCR_SDRAM(SDRAM0_CFG, 0x00000000) /* * Configure Memory Banks */ - WDCR_SDRAM(mem_mb0cf, 0x00062001) - WDCR_SDRAM(mem_mb1cf, 0x00000000) - WDCR_SDRAM(mem_mb2cf, 0x00000000) - WDCR_SDRAM(mem_mb3cf, 0x00000000) + WDCR_SDRAM(SDRAM0_B0CR, 0x00062001) + WDCR_SDRAM(SDRAM0_B1CR, 0x00000000) + WDCR_SDRAM(SDRAM0_B2CR, 0x00000000) + WDCR_SDRAM(SDRAM0_B3CR, 0x00000000) /* * Set up SDTR1 (SDRAM Timing Register) */ - WDCR_SDRAM(mem_sdtr1, 0x00854009) + WDCR_SDRAM(SDRAM0_TR, 0x00854009) /* * Set RTR (Refresh Timing Register) */ - WDCR_SDRAM(mem_rtr, 0x10000000) - /* WDCR_SDRAM(mem_rtr, 0x05f00000) */ + WDCR_SDRAM(SDRAM0_RTR, 0x10000000) + /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */ /******************************************************************** * Delay to ensure 200usec have elapsed since reset. Assume worst @@ -206,7 +206,7 @@ sdram_init: /******************************************************************** * Set memory controller options reg, MCOPT1. *******************************************************************/ - WDCR_SDRAM(mem_mcopt1,0x80800000) + WDCR_SDRAM(SDRAM0_CFG,0x80800000) ..sdri_done: blr /* Return to calling function */ diff --git a/board/eric/init.S b/board/eric/init.S index 16ab11eae2..c18663a75d 100644 --- a/board/eric/init.S +++ b/board/eric/init.S @@ -228,7 +228,7 @@ sdram_init: /* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */ /*------------------------------------------------------------------- */ - addi r4,0,mem_mb0cf + addi r4,0,SDRAM0_B0CR mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB0CF@h ori r4,r4,MB0CF@l @@ -238,7 +238,7 @@ sdram_init: /* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */ /*------------------------------------------------------------------- */ - addi r4,0,mem_mb1cf + addi r4,0,SDRAM0_B1CR mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB1CF@h ori r4,r4,MB1CF@l @@ -248,7 +248,7 @@ sdram_init: /* Set MB2CF for bank 2. off */ /*------------------------------------------------------------------- */ - addi r4,0,mem_mb2cf + addi r4,0,SDRAM0_B2CR mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB2CF@h ori r4,r4,MB2CF@l @@ -258,7 +258,7 @@ sdram_init: /* Set MB3CF for bank 3. off */ /*------------------------------------------------------------------- */ - addi r4,0,mem_mb3cf + addi r4,0,SDRAM0_B3CR mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB3CF@h ori r4,r4,MB3CF@l @@ -305,14 +305,14 @@ sdram_init: /*------------------------------------------------------------------- */ /* Set SDTR1 */ /*------------------------------------------------------------------- */ - addi r4,0,mem_sdtr1 + addi r4,0,SDRAM0_TR mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGDATA,r6 /*------------------------------------------------------------------- */ /* Set RTR */ /*------------------------------------------------------------------- */ - addi r4,0,mem_rtr + addi r4,0,SDRAM0_RTR mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGDATA,r7 @@ -332,7 +332,7 @@ sdram_init: /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */ /* read/prefetch. */ /*------------------------------------------------------------------- */ - addi r4,0,mem_mcopt1 + addi r4,0,SDRAM0_CFG mtdcr SDRAM0_CFGADDR,r4 addis r4,0,0x8080 /* set DC_EN=1 */ ori r4,r4,0x0000 diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c index ce6469d29e..50d9748c71 100644 --- a/board/exbitgen/exbitgen.c +++ b/board/exbitgen/exbitgen.c @@ -94,28 +94,28 @@ phys_size_t initdram (int board_type) tot_size = 0; - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S index c2dae560f5..7a9726fe78 100644 --- a/board/exbitgen/init.S +++ b/board/exbitgen/init.S @@ -382,7 +382,7 @@ sdram_init: /*----------------------------------------------------------- */ /* Set SDTR1 */ /*----------------------------------------------------------- */ - addi r5,0,mem_sdtr1 + addi r5,0,SDRAM0_TR mtdcr SDRAM0_CFGADDR,r5 mtdcr SDRAM0_CFGDATA,r4 @@ -413,7 +413,7 @@ sdram_init: /* Set SDRAM bank 0 register and adjust r6 for next bank */ /*------------------------------------------------------ */ - addi r7,0,mem_mb0cf + addi r7,0,SDRAM0_B0CR mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGDATA,r6 @@ -424,7 +424,7 @@ sdram_init: cmpi 0, r12, 2 bne b1skip - addi r7,0,mem_mb1cf + addi r7,0,SDRAM0_B1CR mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGDATA,r6 @@ -432,7 +432,7 @@ sdram_init: /* Set SDRAM bank 2 register and adjust r6 for next bank */ /*------------------------------------------------------ */ -b1skip: addi r7,0,mem_mb2cf +b1skip: addi r7,0,SDRAM0_B2CR mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGDATA,r6 @@ -443,7 +443,7 @@ b1skip: addi r7,0,mem_mb2cf cmpi 0, r12, 2 bne b3skip - addi r7,0,mem_mb3cf + addi r7,0,SDRAM0_B3CR mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGDATA,r6 b3skip: @@ -456,7 +456,7 @@ b3skip: addis r7, 0, 0x05F0 /* RTR value for 100Mhz */ bl rtr_2 rtr_1: addis r7, 0, 0x03F8 -rtr_2: addi r4,0,mem_rtr +rtr_2: addi r4,0,SDRAM0_RTR mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGDATA,r7 @@ -476,7 +476,7 @@ rtr_2: addi r4,0,mem_rtr /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */ /* read/prefetch. */ /*----------------------------------------------------------- */ - addi r4,0,mem_mcopt1 + addi r4,0,SDRAM0_CFG mtdcr SDRAM0_CFGADDR,r4 addis r4,0,0x80C0 /* set DC_EN=1 */ ori r4,r4,0x0000 diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 8afffdc737..092a3d8a19 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -116,16 +116,16 @@ long int init_sdram_static_settings(void) { #define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data) /* disable memcontroller so updates work */ - mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL ); - mtsdram0( mem_rtr , MEM_RTR_INIT_VAL ); - mtsdram0( mem_pmit , MEM_PMIT_INIT_VAL ); - mtsdram0( mem_mb0cf , MEM_MB0CF_INIT_VAL ); - mtsdram0( mem_mb1cf , MEM_MB1CF_INIT_VAL ); - mtsdram0( mem_sdtr1 , MEM_SDTR1_INIT_VAL ); + mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL ); + mtsdram0( SDRAM0_RTR , MEM_RTR_INIT_VAL ); + mtsdram0( SDRAM0_PMIT , MEM_PMIT_INIT_VAL ); + mtsdram0( SDRAM0_B0CR , MEM_MB0CF_INIT_VAL ); + mtsdram0( SDRAM0_B1CR , MEM_MB1CF_INIT_VAL ); + mtsdram0( SDRAM0_TR , MEM_SDTR1_INIT_VAL ); /* SDRAM have a power on delay, 500 micro should do */ udelay(500); - mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE ); + mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE ); return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */ } diff --git a/board/jse/sdram.c b/board/jse/sdram.c index bb6f85eee5..88fdd84130 100644 --- a/board/jse/sdram.c +++ b/board/jse/sdram.c @@ -35,59 +35,59 @@ phys_size_t initdram (int board_type) /* Configure the SDRAMS */ /* disable memory controller */ - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); mtdcr (SDRAM0_CFGDATA, 0x00000000); udelay (500); /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ - mtdcr (SDRAM0_CFGADDR, mem_besra); + mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0); mtdcr (SDRAM0_CFGDATA, 0xffffffff); /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ - mtdcr (SDRAM0_CFGADDR, mem_besrb); + mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1); mtdcr (SDRAM0_CFGDATA, 0xffffffff); /* Clear SDRAM0_ECCCFG (disable ECC) */ - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); mtdcr (SDRAM0_CFGDATA, 0x00000000); /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ - mtdcr (SDRAM0_CFGADDR, mem_eccerr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR); mtdcr (SDRAM0_CFGDATA, 0xffffffff); /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */ - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); mtdcr (SDRAM0_CFGDATA, 0x010a4016); /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); mtdcr (SDRAM0_CFGDATA, 0x00084001); /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */ - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); mtdcr (SDRAM0_CFGDATA, 0x04084001); /* Memory Bank 2 Config == BE=0 */ - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); mtdcr (SDRAM0_CFGDATA, 0x00000000); /* Memory Bank 3 Config == BE=0 */ - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); mtdcr (SDRAM0_CFGDATA, 0x00000000); /* refresh timer = 0x400 */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); mtdcr (SDRAM0_CFGDATA, 0x04000000); /* Power management idle timer set to the default. */ - mtdcr (SDRAM0_CFGADDR, mem_pmit); + mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT); mtdcr (SDRAM0_CFGDATA, 0x07c00000); udelay (500); /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */ - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); mtdcr (SDRAM0_CFGDATA, 0x80e00000); return SDRAM_LEN; @@ -108,7 +108,7 @@ int testdram (void) #ifdef DEBUG printf ("SDRAM Controller Registers --\n"); - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_CFG : 0x%08x\n", val); @@ -116,19 +116,19 @@ int testdram (void) val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_STATUS: 0x%08x\n", val); - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_B0CR : 0x%08x\n", val); - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_B1CR : 0x%08x\n", val); - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_TR : 0x%08x\n", val); - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_RTR : 0x%08x\n", val); #endif diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index b87df01fec..ae8eade64a 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -348,7 +348,7 @@ int init_sdram (void) /* trc_clocks is sum of trp_clocks + tras_clocks */ trc_clocks = trp_clocks + tras_clocks; /* get SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; /* insert CASL value */ sdram_tim |= ((unsigned long) (cal_val)) << 23; @@ -369,7 +369,7 @@ int init_sdram (void) /* insert SZ value; */ tmp |= ((unsigned long) sdram_table[i].sz << 17); /* get SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; sdram_bank |= (baseaddr | tmp | 0x01); @@ -380,7 +380,7 @@ int init_sdram (void) #endif /* write SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); mtdcr (SDRAM0_CFGDATA, sdram_tim); #ifdef SDRAM_DEBUG @@ -390,22 +390,22 @@ int init_sdram (void) #endif /* write SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); mtdcr (SDRAM0_CFGDATA, sdram_bank); if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */ /* get SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; tmp |= 0x07F00000; } else { /* get SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; tmp |= 0x05F00000; } /* write SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); mtdcr (SDRAM0_CFGDATA, tmp); /* enable ECC if used */ #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI) @@ -415,18 +415,18 @@ int init_sdram (void) #ifdef SDRAM_DEBUG serial_puts ("disable ECC.. "); #endif - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); tmp = mfdcr (SDRAM0_CFGDATA); tmp &= 0xff0fffff; /* disable all banks */ - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); /* set up SDRAM Controller with ECC enabled */ #ifdef SDRAM_DEBUG serial_puts ("setup SDRAM Controller.. "); #endif mtdcr (SDRAM0_CFGDATA, tmp); - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); mtdcr (SDRAM0_CFGDATA, tmp); udelay (600); #ifdef SDRAM_DEBUG @@ -447,7 +447,7 @@ int init_sdram (void) serial_puts ("enable ECC\n"); #endif udelay (400); - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); tmp = mfdcr (SDRAM0_CFGDATA); tmp |= 0x00800000; /* enable bank 0 */ mtdcr (SDRAM0_CFGDATA, tmp); @@ -456,9 +456,9 @@ int init_sdram (void) #endif { /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000; - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); mtdcr (SDRAM0_CFGDATA, tmp); udelay (400); } @@ -631,13 +631,13 @@ phys_size_t initdram (int board_type) ds = 0; /* since the DRAM controller is allready set up, calculate the size with the bank registers */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); bank_reg[0] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); bank_reg[1] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); bank_reg[2] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); bank_reg[3] = mfdcr (SDRAM0_CFGDATA); TotalSize = 0; for (i = 0; i < 4; i++) { @@ -648,7 +648,7 @@ phys_size_t initdram (int board_type) } else ds = 1; } - mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); tmp = mfdcr (SDRAM0_CFGDATA); if (!tmp) diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index c2d6c6fbcf..792eccc154 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -361,7 +361,7 @@ int board_early_init_f (void) SDRAM_err ("unsupported SDRAM"); /* get SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; /* insert CASL value */ /* tmp |= ((unsigned long)cal_val) << 23; */ @@ -385,7 +385,7 @@ int board_early_init_f (void) #endif /* write SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); mtdcr (SDRAM0_CFGDATA, tmp); baseaddr = CONFIG_SYS_SDRAM_BASE; bank_size = (((unsigned long) density) << 22) / 2; @@ -418,7 +418,7 @@ int board_early_init_f (void) SDRAM_err ("unsupported SDRAM"); } /* endswitch */ /* get SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank |= (baseaddr | tmp | 0x01); #ifdef SDRAM_DEBUG @@ -434,11 +434,11 @@ int board_early_init_f (void) sdram_size += bank_size; /* write SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 1 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; sdram_size = 0; @@ -459,11 +459,11 @@ int board_early_init_f (void) serial_puts ("\n"); #endif /* write SDRAM bank 1 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 2 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank |= (baseaddr | tmp | 0x01); @@ -482,11 +482,11 @@ int board_early_init_f (void) sdram_size += bank_size; /* write SDRAM bank 2 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 3 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; #ifdef SDRAM_DEBUG @@ -509,12 +509,12 @@ int board_early_init_f (void) #endif /* write SDRAM bank 3 register */ - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; if (tmemclk < NSto10PS (16)) @@ -523,13 +523,13 @@ int board_early_init_f (void) tmp |= 0x03F80000; /* write SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); mtdcr (SDRAM0_CFGDATA, tmp); /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000; - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); mtdcr (SDRAM0_CFGDATA, tmp); @@ -619,13 +619,13 @@ phys_size_t initdram (int board_type) /* since the DRAM controller is allready set up, * calculate the size with the bank registers */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); bank_reg[0] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); bank_reg[1] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); bank_reg[2] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); bank_reg[3] = mfdcr (SDRAM0_CFGDATA); TotalSize = 0; for (i = 0; i < 4; i++) { diff --git a/board/netstal/common/fixed_sdram.c b/board/netstal/common/fixed_sdram.c index f7baed6e91..2f21fbb4e3 100644 --- a/board/netstal/common/fixed_sdram.c +++ b/board/netstal/common/fixed_sdram.c @@ -29,17 +29,17 @@ void show_sdram_registers(void) u32 value; printf("SDRAM Controller Registers --\n"); - mfsdram(mem_mcopt1, value); + mfsdram(SDRAM0_CFG, value); printf(" SDRAM0_CFG : 0x%08x\n", value); - mfsdram(mem_status, value); + mfsdram(SDRAM0_STATUS, value); printf(" SDRAM0_STATUS: 0x%08x\n", value); - mfsdram(mem_mb0cf, value); + mfsdram(SDRAM0_B0CR, value); printf(" SDRAM0_B0CR : 0x%08x\n", value); - mfsdram(mem_mb1cf, value); + mfsdram(SDRAM0_B1CR, value); printf(" SDRAM0_B1CR : 0x%08x\n", value); - mfsdram(mem_sdtr1, value); + mfsdram(SDRAM0_TR, value); printf(" SDRAM0_TR : 0x%08x\n", value); - mfsdram(mem_rtr, value); + mfsdram(SDRAM0_RTR, value); printf(" SDRAM0_RTR : 0x%08x\n", value); } #endif @@ -50,53 +50,53 @@ long int init_ppc405_sdram(unsigned int dram_size) printf(__FUNCTION__); #endif /* disable memory controller */ - mtsdram(mem_mcopt1, 0x00000000); + mtsdram(SDRAM0_CFG, 0x00000000); udelay (500); /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ - mtsdram(mem_besra, 0xffffffff); + mtsdram(SDRAM0_BESR0, 0xffffffff); /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ - mtsdram(mem_besrb, 0xffffffff); + mtsdram(SDRAM0_BESR1, 0xffffffff); /* Clear SDRAM0_ECCCFG (disable ECC) */ - mtsdram(mem_ecccf, 0x00000000); + mtsdram(SDRAM0_ECCCFG, 0x00000000); /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ - mtsdram(mem_eccerr, 0xffffffff); + mtsdram(SDRAM0_ECCESR, 0xffffffff); /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */ - mtsdram(mem_sdtr1, 0x008a4015); + mtsdram(SDRAM0_TR, 0x008a4015); /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 * and refresh timer */ switch (dram_size >> 20) { case 32: - mtsdram(mem_mb0cf, 0x00062001); - mtsdram(mem_rtr, 0x07F00000); + mtsdram(SDRAM0_B0CR, 0x00062001); + mtsdram(SDRAM0_RTR, 0x07F00000); break; case 64: - mtsdram(mem_mb0cf, 0x00084001); - mtsdram(mem_rtr, 0x04100000); + mtsdram(SDRAM0_B0CR, 0x00084001); + mtsdram(SDRAM0_RTR, 0x04100000); break; case 128: - mtsdram(mem_mb0cf, 0x000A4001); - mtsdram(mem_rtr, 0x04100000); + mtsdram(SDRAM0_B0CR, 0x000A4001); + mtsdram(SDRAM0_RTR, 0x04100000); break; default: printf("Invalid memory size of %d MB given\n", dram_size >> 20); } /* Power management idle timer set to the default. */ - mtsdram(mem_pmit, 0x07c00000); + mtsdram(SDRAM0_PMIT, 0x07c00000); udelay (500); /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */ - mtsdram(mem_mcopt1, 0x90800000); + mtsdram(SDRAM0_CFG, 0x90800000); #ifdef DEBUG printf("%s: done\n", __FUNCTION__); diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index d8b0564b3b..e1c61463dd 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -266,11 +266,11 @@ long int fixed_sdram (void) /*-------------------------------------------------------------------- * Setup some default *------------------------------------------------------------------*/ - mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ - mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ + mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /*-------------------------------------------------------------------- * Setup for board-specific specific mem @@ -278,20 +278,20 @@ long int fixed_sdram (void) /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ - mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ /* RA=10 RD=3 */ - mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ udelay (400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ - mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ for (;;) { - mfsdram (mem_mcsts, reg); + mfsdram (SDRAM0_MCSTS, reg); if (reg & 0x80000000) break; } diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c index e7772c5ff6..63927f7298 100644 --- a/board/sc3/sc3.c +++ b/board/sc3/sc3.c @@ -577,7 +577,7 @@ static int printSDRAMConfig(char reg, unsigned long cr) } #ifdef SC3_DEBUGOUT -static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf}; +static unsigned int mbcf[] = {SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR}; #endif phys_size_t initdram (int board_type) @@ -591,7 +591,7 @@ phys_size_t initdram (int board_type) puts("\nSDRAM configuration:\n"); - mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); ul1 = mfdcr(SDRAM0_CFGDATA); if (!(ul1 & 0x80000000)) { @@ -604,7 +604,7 @@ phys_size_t initdram (int board_type) mems += printSDRAMConfig (i, ul1); } - mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); ul1 = mfdcr(SDRAM0_CFGDATA); printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1); @@ -614,14 +614,14 @@ phys_size_t initdram (int board_type) printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4); printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1)); puts ("Misc:\n"); - mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); ul1 = mfdcr(SDRAM0_CFGDATA); printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7); - mtdcr(SDRAM0_CFGADDR,mem_pmit); + mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT); ul2=mfdcr(SDRAM0_CFGDATA); - mtdcr(SDRAM0_CFGADDR,mem_mcopt1); + mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG); ul1=mfdcr(SDRAM0_CFGDATA); if (ul1 & 0x20000000) @@ -658,7 +658,7 @@ phys_size_t initdram (int board_type) else puts(" -Memory lines only at write cycles active outputs\n"); - mtdcr (SDRAM0_CFGADDR, mem_status); + mtdcr (SDRAM0_CFGADDR, SDRAM0_STATUS); ul1 = mfdcr (SDRAM0_CFGDATA); if (ul1 & 0x80000000) puts(" -SDRAM Controller ready\n"); @@ -670,19 +670,19 @@ phys_size_t initdram (int board_type) return (mems * 1024 * 1024); #else - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); ul1 = mfdcr (SDRAM0_CFGDATA); mems = printSDRAMConfig (0, ul1); - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); ul1 = mfdcr (SDRAM0_CFGDATA); mems += printSDRAMConfig (1, ul1); - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); ul1 = mfdcr(SDRAM0_CFGDATA); mems += printSDRAMConfig (2, ul1); - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); ul1 = mfdcr(SDRAM0_CFGDATA); mems += printSDRAMConfig (3, ul1); diff --git a/board/w7o/init.S b/board/w7o/init.S index 090b07a1e6..5477f986b9 100644 --- a/board/w7o/init.S +++ b/board/w7o/init.S @@ -182,7 +182,7 @@ sdram_init: * Disable memory controller to allow * values to be changed. */ - addi r3, 0, mem_mcopt1 + addi r3, 0, SDRAM0_CFG mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0 ori r4, r4, 0x0 @@ -192,7 +192,7 @@ sdram_init: * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2 * All other banks are disabled. */ - addi r3, 0, mem_mb0cf + addi r3, 0, SDRAM0_B0CR mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */ ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */ @@ -222,7 +222,7 @@ sdram_init: /* * Set up SDTR1 */ - addi r3, 0, mem_sdtr1 + addi r3, 0, SDRAM0_TR mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */ ori r4, r4, 0x400D @@ -231,7 +231,7 @@ sdram_init: /* * Set RTR */ - addi r3, 0, mem_rtr + addi r3, 0, SDRAM0_RTR mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */ mtdcr SDRAM0_CFGDATA, r4 @@ -250,7 +250,7 @@ sdram_init: /******************************************************************** * Set memory controller options reg, MCOPT1. *******************************************************************/ - addi r3, 0, mem_mcopt1 + addi r3, 0, SDRAM0_CFG mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */ ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */ diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index 00a9f98b44..a818808ba0 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -170,16 +170,16 @@ unsigned long get_dram_size (void) int size = 0; /* Get bank Size registers */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); /* get bank 0 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */ regs[0] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); /* get bank 1 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */ regs[1] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); /* get bank 2 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */ regs[2] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); /* get bank 3 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */ regs[3] = mfdcr (SDRAM0_CFGDATA); /* compute the size, add each bank if enabled */ -- cgit v1.2.1 From b306db2f1bf561b5823a655c677fe28cfad80cfb Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 24 Sep 2009 14:10:30 +0200 Subject: ppc4xx: Remove mtsdram0() marcos and use common mtsdram() instead Additionally some whitespace coding style fixes. Signed-off-by: Stefan Roese --- board/g2000/g2000.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'board') diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 092a3d8a19..03cd6b8847 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -114,18 +114,17 @@ int checkboard (void) long int init_sdram_static_settings(void) { -#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data) /* disable memcontroller so updates work */ - mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL ); - mtsdram0( SDRAM0_RTR , MEM_RTR_INIT_VAL ); - mtsdram0( SDRAM0_PMIT , MEM_PMIT_INIT_VAL ); - mtsdram0( SDRAM0_B0CR , MEM_MB0CF_INIT_VAL ); - mtsdram0( SDRAM0_B1CR , MEM_MB1CF_INIT_VAL ); - mtsdram0( SDRAM0_TR , MEM_SDTR1_INIT_VAL ); + mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL); + mtsdram(SDRAM0_RTR, MEM_RTR_INIT_VAL); + mtsdram(SDRAM0_PMIT, MEM_PMIT_INIT_VAL); + mtsdram(SDRAM0_B0CR, MEM_MB0CF_INIT_VAL); + mtsdram(SDRAM0_B1CR, MEM_MB1CF_INIT_VAL); + mtsdram(SDRAM0_TR, MEM_SDTR1_INIT_VAL); /* SDRAM have a power on delay, 500 micro should do */ udelay(500); - mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE ); + mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE); return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */ } -- cgit v1.2.1