From 945af8d723a29e9b6289d84250745ed0dc16fc81 Mon Sep 17 00:00:00 2001 From: wdenk Date: Wed, 16 Jul 2003 21:53:01 +0000 Subject: * Add support for IceCube board (with MGT5100 and MPC5200 CPUs) * Add support for MGT5100 and MPC5200 processors --- board/a3000/a3000.c | 12 +- board/exbitgen/flash.c | 24 +-- board/exbitgen/init.S | 296 +++++++++++++------------- board/exbitgen/u-boot.lds | 2 +- board/gen860t/gen860t.c | 2 +- board/icecube/Makefile | 47 +++++ board/icecube/config.mk | 31 +++ board/icecube/flash.c | 480 +++++++++++++++++++++++++++++++++++++++++++ board/icecube/icecube.c | 116 +++++++++++ board/icecube/u-boot.lds | 122 +++++++++++ board/lwmon/lwmon.c | 2 +- board/omap1510inn/platform.S | 334 +++++++++++++++--------------- board/omap1510inn/u-boot.lds | 20 +- board/sacsng/sacsng.c | 2 +- board/sl8245/u-boot.lds | 1 - board/tqm8xx/flash.c | 2 +- 16 files changed, 1144 insertions(+), 349 deletions(-) create mode 100644 board/icecube/Makefile create mode 100644 board/icecube/config.mk create mode 100644 board/icecube/flash.c create mode 100644 board/icecube/icecube.c create mode 100644 board/icecube/u-boot.lds (limited to 'board') diff --git a/board/a3000/a3000.c b/board/a3000/a3000.c index 8d665855ca..efc95a30e8 100644 --- a/board/a3000/a3000.c +++ b/board/a3000/a3000.c @@ -91,31 +91,31 @@ Done: */ #ifndef CONFIG_PCI_PNP static struct pci_config_table pci_a3000_config_table[] = { - /* vendor, device, class */ - /* bus, dev, func */ + /* vendor, device, class */ + /* bus, dev, func */ { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, /* dp83815 eth0 divice */ + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, /* dp83815 eth0 divice */ pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, PCI_ENET0_MEMADDR, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x14, PCI_ANY_ID, /* PCI slot1 */ + PCI_ANY_ID, 0x14, PCI_ANY_ID, /* PCI slot1 */ pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, PCI_ENET1_MEMADDR, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */ + PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */ pci_cfgfunc_config_device, { PCI_ENET2_IOADDR, PCI_ENET2_MEMADDR, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x16, PCI_ANY_ID, /* PCI slot3 */ + PCI_ANY_ID, 0x16, PCI_ANY_ID, /* PCI slot3 */ pci_cfgfunc_config_device, { PCI_ENET3_IOADDR, PCI_ENET3_MEMADDR, PCI_COMMAND_IO | diff --git a/board/exbitgen/flash.c b/board/exbitgen/flash.c index f687ea3a26..ae88994b2c 100644 --- a/board/exbitgen/flash.c +++ b/board/exbitgen/flash.c @@ -217,7 +217,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) short i; FLASH_WORD_SIZE value; ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; /* Write auto select command: read Manufacturer ID */ addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; @@ -247,7 +247,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) switch (value) { case (FLASH_WORD_SIZE)AMD_ID_F040B: - info->flash_id += FLASH_AM040; + info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 512 ko */ break; @@ -335,14 +335,14 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) } /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || (info->flash_id == FLASH_AM040) || (info->flash_id == FLASH_AMDLV033C) || (info->flash_id == FLASH_AMDLV065D)) { ulong sectsize = info->size / info->sector_count; for (i = 0; i < info->sector_count; i++) info->start[i] = base + (i * sectsize); - } else { + } else { if (info->flash_id & FLASH_BTYPE) { /* set sector offsets for bottom boot block type */ info->start[0] = base + 0x00000000; @@ -370,9 +370,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) /* D0 = 1 if protected */ addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) info->protect[i] = 0; - else + else info->protect[i] = addr2[2] & 1; } @@ -450,7 +450,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) while ((addr2[0] & 0x00800080) != (FLASH_WORD_SIZE) 0x00800080) { if ((now=get_timer(start)) > - CFG_FLASH_ERASE_TOUT) { + CFG_FLASH_ERASE_TOUT) { printf ("Timeout\n"); addr[0] = (FLASH_WORD_SIZE)0x00F000F0; return 1; @@ -551,12 +551,12 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ static int write_word (flash_info_t *info, ulong dest, ulong data) { - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; ulong start; int flag; - int i; + int i; /* Check if Flash is (sufficiently) erased */ if ((*((volatile ulong *)dest) & data) != data) { @@ -565,7 +565,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) return 2; } - for (i=0; i < 4/sizeof(FLASH_WORD_SIZE); i++) { + for (i=0; i < 4/sizeof(FLASH_WORD_SIZE); i++) { /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S index 96b0abae1b..0e6cd04ba8 100644 --- a/board/exbitgen/init.S +++ b/board/exbitgen/init.S @@ -34,7 +34,7 @@ #include #include "exbitgen.h" - + /* IIC declarations (This is an extract from 405gp_i2c.h, which also contains some */ /* c-code declarations and consequently can't be included here). */ /* (Possibly to be solved somehow else). */ @@ -100,25 +100,25 @@ #define TIMEBASE_10PS (1000000000 / CONFIG_SYS_CLK_FREQ) * 100 #define FLASH_8bit_AP 0x9B015480 -#define FLASH_8bit_CR 0xFFF18000 /* 1MB(min), 8bit, R/W */ +#define FLASH_8bit_CR 0xFFF18000 /* 1MB(min), 8bit, R/W */ #define FLASH_32bit_AP 0x9B015480 #define FLASH_32bit_CR 0xFFE3C000 /* 2MB, 32bit, R/W */ #define WDCR_EBC(reg,val) addi r4,0,reg;\ - mtdcr ebccfga,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr ebccfgd,r4 + mtdcr ebccfga,r4;\ + addis r4,0,val@h;\ + ori r4,r4,val@l;\ + mtdcr ebccfgd,r4 /*--------------------------------------------------------------------- * Function: ext_bus_cntlr_init - * Description: Initializes the External Bus Controller for the external - * peripherals. IMPORTANT: For pass1 this code must run from + * Description: Initializes the External Bus Controller for the external + * peripherals. IMPORTANT: For pass1 this code must run from * cache since you can not reliably change a peripheral banks * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT + * For ex., since we are running from ROM on bank 0, we can NOT * execute the code that modifies bank 0 timings from ROM, so * we run it from cache. * Bank 0 - Boot flash @@ -126,63 +126,63 @@ * Bank 5 - CPLD * Bank 6 - not used * Bank 7 - Heathrow chip - *--------------------------------------------------------------------- + *--------------------------------------------------------------------- */ - .globl ext_bus_cntlr_init + .globl ext_bus_cntlr_init ext_bus_cntlr_init: - mflr r4 /* save link register */ - bl ..getAddr + mflr r4 /* save link register */ + bl ..getAddr ..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 10; used to prefetch */ - mtctr r4 /* 10 cache lines to fit this function */ - /* in cache (gives us 8x10=80 instrctns) */ + mflr r3 /* get address of ..getAddr */ + mtlr r4 /* restore link register */ + addi r4,0,14 /* set ctr to 10; used to prefetch */ + mtctr r4 /* 10 cache lines to fit this function */ + /* in cache (gives us 8x10=80 instrctns) */ ..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 10 cache lines */ + icbt r0,r3 /* prefetch cache line for addr in r3 */ + addi r3,r3,32 /* move to next cache line */ + bdnz ..ebcloop /* continue for 10 cache lines */ mflr r31 /* save link register */ - - /*----------------------------------------------------------- - * Delay to ensure all accesses to ROM are complete before changing + + /*----------------------------------------------------------- + * Delay to ensure all accesses to ROM are complete before changing * bank 0 timings. 200usec should be enough. - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - *----------------------------------------------------------- + * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles + *----------------------------------------------------------- */ addis r3,0,0x0 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 + ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ + mtctr r3 ..spinlp: - bdnz ..spinlp /* spin loop */ + bdnz ..spinlp /* spin loop */ - /*--------------------------------------------------------------- - * Memory Bank 0 (Boot Flash) initialization - *--------------------------------------------------------------- + /*--------------------------------------------------------------- + * Memory Bank 0 (Boot Flash) initialization + *--------------------------------------------------------------- */ WDCR_EBC(pb0ap, FLASH_32bit_AP) WDCR_EBC(pb0cr, 0xffe38000) /*pnc WDCR_EBC(pb0cr, FLASH_32bit_CR) */ - - /*--------------------------------------------------------------- - * Memory Bank 5 (CPLD) initialization - *--------------------------------------------------------------- + + /*--------------------------------------------------------------- + * Memory Bank 5 (CPLD) initialization + *--------------------------------------------------------------- */ WDCR_EBC(pb5ap, 0x01010040) /*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */ WDCR_EBC(pb5cr, 0x10038000) - /*--------------------------------------------------------------- */ - /* Memory Bank 6 (not used) initialization */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 6 (not used) initialization */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb6cr, 0x00000000) /* Read HW ID to determine whether old H2 board or new generic CPU board */ addis r3, 0, HW_ID_ADDR@h ori r3, r3, HW_ID_ADDR@l - lbz r3,0x0000(r3) + lbz r3,0x0000(r3) cmpi 0, r3, 1 /* if (HW_ID==1) */ beq setup_h2evalboard /* then jump */ cmpi 0, r3, 2 /* if (HW_ID==2) */ @@ -191,9 +191,9 @@ ext_bus_cntlr_init: beq setup_genieboard /* then jump */ setup_genieboard: - /*--------------------------------------------------------------- */ - /* Memory Bank 1 (Application Flash) initialization for generic CPU board */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 1 (Application Flash) initialization for generic CPU board */ + /*--------------------------------------------------------------- */ /* WDCR_EBC(pb1ap, 0x7b015480) /###* T.B.M. */ /* WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */ WDCR_EBC(pb1ap, 0x9b015480) /* hlb-20020207: burst 8 bit 6 cycles */ @@ -201,68 +201,68 @@ setup_genieboard: /* WDCR_EBC(pb1cr, 0x20098000) /###* 16 MB */ WDCR_EBC(pb1cr, 0x200B8000) /* 32 MB */ - /*--------------------------------------------------------------- */ - /* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb4ap, 0x01010000) /* */ WDCR_EBC(pb4cr, 0x1021c000) /* */ - /*--------------------------------------------------------------- */ - /* Memory Bank 7 (Heathrow chip on Reference board) initialization */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 7 (Heathrow chip on Reference board) initialization */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb7ap, 0x200ffe80) /* No Ready, many wait states (let reflections die out) */ WDCR_EBC(pb7cr, 0X4001A000) bl setup_continue - + setup_h2evalboard: - /*--------------------------------------------------------------- */ - /* Memory Bank 1 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 1 (Application Flash) initialization */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb1ap, 0x7b015480) /* T.B.M. */ /*3010 WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb1cr, 0x20058000) + WDCR_EBC(pb1cr, 0x20058000) - /*--------------------------------------------------------------- */ - /* Memory Bank 2 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 2 (Application Flash) initialization */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb2ap, 0x7b015480) /* T.B.M. */ /*3010 WDCR_EBC(pb2ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb2cr, 0x20458000) + WDCR_EBC(pb2cr, 0x20458000) /*--------------------------------------------------------------- */ - /* Memory Bank 3 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ + /* Memory Bank 3 (Application Flash) initialization */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb3ap, 0x7b015480) /* T.B.M. */ /*3010 WDCR_EBC(pb3ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb3cr, 0x20858000) + WDCR_EBC(pb3cr, 0x20858000) - /*--------------------------------------------------------------- */ - /* Memory Bank 4 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 4 (Application Flash) initialization */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb4ap, 0x7b015480) /* T.B.M. */ /*3010 WDCR_EBC(pb4ap, 0x7F8FFE80) /###* T.B.M. */ WDCR_EBC(pb4cr, 0x20C58000) - /*--------------------------------------------------------------- */ - /* Memory Bank 7 (Heathrow chip) initialization */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 7 (Heathrow chip) initialization */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb7ap, 0x02000280) /* No Ready, 4 wait states */ WDCR_EBC(pb7cr, 0X4001A000) setup_continue: - - mtlr r31 /* restore lr */ + + mtlr r31 /* restore lr */ nop /* pass2 DCR errata #8 */ - blr + blr /*--------------------------------------------------------------------- */ /* Function: sdram_init */ /* Description: Configures SDRAM memory banks. */ /*--------------------------------------------------------------------- */ - .globl sdram_init + .globl sdram_init sdram_init: #if CFG_MONITOR_BASE < CFG_FLASH_BASE @@ -377,12 +377,12 @@ sdram_init: subf r5, r6, r17 or r4, r4, r5 - /*----------------------------------------------------------- */ - /* Set SDTR1 */ - /*----------------------------------------------------------- */ - addi r5,0,mem_sdtr1 - mtdcr memcfga,r5 - mtdcr memcfgd,r4 + /*----------------------------------------------------------- */ + /* Set SDTR1 */ + /*----------------------------------------------------------- */ + addi r5,0,mem_sdtr1 + mtdcr memcfga,r5 + mtdcr memcfgd,r4 /*----------------------------------------------------------- */ /* */ @@ -444,36 +444,36 @@ b1skip: addi r7,0,mem_mb2cf addi r7,0,mem_mb3cf mtdcr memcfga,r7 mtdcr memcfgd,r6 -b3skip: +b3skip: - /*----------------------------------------------------------- */ - /* Set RTR */ - /*----------------------------------------------------------- */ + /*----------------------------------------------------------- */ + /* Set RTR */ + /*----------------------------------------------------------- */ cmpi 0, r30, 1600 bge rtr_1 - addis r7, 0, 0x05F0 /* RTR value for 100Mhz */ + addis r7, 0, 0x05F0 /* RTR value for 100Mhz */ bl rtr_2 rtr_1: addis r7, 0, 0x03F8 rtr_2: addi r4,0,mem_rtr mtdcr memcfga,r4 mtdcr memcfgd,r7 - /*----------------------------------------------------------- */ - /* Delay to ensure 200usec have elapsed since reset. Assume worst */ - /* case that the core is running 200Mhz: */ - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ - /*----------------------------------------------------------- */ - addis r3,0,0x0000 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 + /*----------------------------------------------------------- */ + /* Delay to ensure 200usec have elapsed since reset. Assume worst */ + /* case that the core is running 200Mhz: */ + /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ + /*----------------------------------------------------------- */ + addis r3,0,0x0000 + ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ + mtctr r3 ..spinlp2: - bdnz ..spinlp2 /* spin loop */ + bdnz ..spinlp2 /* spin loop */ - /*----------------------------------------------------------- */ - /* Set memory controller options reg, MCOPT1. */ + /*----------------------------------------------------------- */ + /* Set memory controller options reg, MCOPT1. */ /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */ /* read/prefetch. */ - /*----------------------------------------------------------- */ + /*----------------------------------------------------------- */ addi r4,0,mem_mcopt1 mtdcr memcfga,r4 addis r4,0,0x80C0 /* set DC_EN=1 */ @@ -481,13 +481,13 @@ rtr_2: addi r4,0,mem_rtr mtdcr memcfgd,r4 - /*----------------------------------------------------------- */ - /* Delay to ensure 10msec have elapsed since reset. This is */ - /* required for the MPC952 to stabalize. Assume worst */ - /* case that the core is running 200Mhz: */ - /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */ - /* This delay should occur before accessing SDRAM. */ - /*----------------------------------------------------------- */ + /*----------------------------------------------------------- */ + /* Delay to ensure 10msec have elapsed since reset. This is */ + /* required for the MPC952 to stabalize. Assume worst */ + /* case that the core is running 200Mhz: */ + /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */ + /* This delay should occur before accessing SDRAM. */ + /*----------------------------------------------------------- */ addis r3,0,0x001E ori r3,r3,0x8480 /* ensure 10msec have passed since reset */ mtctr r3 @@ -501,8 +501,8 @@ rtr_2: addi r4,0,mem_rtr stb r4,0(r5) eieio - mtlr r31 /* restore lr */ - blr + mtlr r31 /* restore lr */ + blr /*--------------------------------------------------------------------- */ /* Function: read_spd */ @@ -512,21 +512,21 @@ rtr_2: addi r4,0,mem_rtr #define WRITE_I2C(reg,val) \ addi r3,0,val;\ - addis r4, 0, 0xef60;\ - ori r4, r4, 0x0500 + reg;\ - stb r3, 0(r4);\ - eieio + addis r4, 0, 0xef60;\ + ori r4, r4, 0x0500 + reg;\ + stb r3, 0(r4);\ + eieio #define READ_I2C(reg) \ - addis r3, 0, 0xef60;\ - ori r3, r3, 0x0500 + reg;\ - lbz r3, 0x0000(r3);\ - eieio + addis r3, 0, 0xef60;\ + ori r3, r3, 0x0500 + reg;\ + lbz r3, 0x0000(r3);\ + eieio read_spd: mflr r5 - + /* Initialize i2c */ /*--------------- */ WRITE_I2C(IICLMADR, 0x00) /* clear lo master address */ @@ -558,9 +558,9 @@ read_spd: /* Wait a little */ /*-------------- */ - addis r3,0,0x0000 - ori r3,r3,0xA000 - mtctr r3 + addis r3,0,0x0000 + ori r3,r3,0xA000 + mtctr r3 in02: bdnz in02 /* Issue write command */ @@ -572,12 +572,12 @@ in02: bdnz in02 /*--------------- */ addi r7, 0, 0 /* byte counter in r7 */ addi r8, 0, 0 /* checksum in r8 */ -rdlp: +rdlp: /* issue read command */ /*------------------- */ cmpi 0, r7, 127 blt rd01 - WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT) + WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT) bl rd02 rd01: WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_CHT | IIC_CNTL_PT) rd02: bl wait_i2c_transfer_done @@ -585,46 +585,46 @@ rd02: bl wait_i2c_transfer_done /* Fetch byte from buffer */ /*----------------------- */ READ_I2C(IICMDBUF) - + /* Retrieve parameters that are going to be used during configuration. */ /* Save them in dedicated registers. */ /*------------------------------------------------------------ */ cmpi 0, r7, 3 /* Save byte 3 in r10 */ bne rd10 - addi r10, r3, 0 + addi r10, r3, 0 rd10: cmpi 0, r7, 4 /* Save byte 4 in r11 */ bne rd11 - addi r11, r3, 0 + addi r11, r3, 0 rd11: cmpi 0, r7, 5 /* Save byte 5 in r12 */ bne rd12 - addi r12, r3, 0 + addi r12, r3, 0 rd12: cmpi 0, r7, 17 /* Save byte 17 in r13 */ bne rd13 - addi r13, r3, 0 + addi r13, r3, 0 rd13: cmpi 0, r7, 18 /* Save byte 18 in r14 */ bne rd14 - addi r14, r3, 0 + addi r14, r3, 0 rd14: cmpi 0, r7, 31 /* Save byte 31 in r15 */ bne rd15 - addi r15, r3, 0 + addi r15, r3, 0 rd15: cmpi 0, r7, 27 /* Save byte 27 in r16 */ bne rd16 - addi r16, r3, 0 + addi r16, r3, 0 rd16: cmpi 0, r7, 29 /* Save byte 29 in r17 */ bne rd17 - addi r17, r3, 0 + addi r17, r3, 0 rd17: cmpi 0, r7, 30 /* Save byte 30 in r18 */ bne rd18 - addi r18, r3, 0 + addi r18, r3, 0 rd18: cmpi 0, r7, 9 /* Save byte 9 in r19 */ bne rd19 - addi r19, r3, 0 + addi r19, r3, 0 rd19: cmpi 0, r7, 23 /* Save byte 23 in r20 */ bne rd20 - addi r20, r3, 0 + addi r20, r3, 0 rd20: cmpi 0, r7, 25 /* Save byte 25 in r21 */ bne rd21 - addi r21, r3, 0 + addi r21, r3, 0 rd21: /* Calculate checksum of the first 63 bytes */ @@ -647,16 +647,16 @@ rd30: andi. r8, r8, 0xff /* use only 8 bits */ eieio rderr: bl rderr -rd31: - +rd31: + /* Increment byte counter and check whether all bytes have been read. */ /*------------------------------------------------------------------- */ addi r7, r7, 1 cmpi 0, r7, 127 bgt rd05 bl rdlp -rd05: - mtlr r5 /* restore lr */ +rd05: + mtlr r5 /* restore lr */ blr wait_i2c_transfer_done: @@ -664,8 +664,8 @@ wait_i2c_transfer_done: wt01: READ_I2C(IICSTS) andi. r4, r3, IIC_STS_PT cmpi 0, r4, IIC_STS_PT - beq wt01 - mtlr r6 /* restore lr */ + beq wt01 + mtlr r6 /* restore lr */ blr /*--------------------------------------------------------------------- */ @@ -696,7 +696,7 @@ fm01: cmpi 0, r10, 11 cmpi 0, r13, 2 bne fm02 addi r3, 0, 1 - bl fmfound + bl fmfound fm02: cmpi 0, r10, 12 bne fm03 @@ -815,7 +815,7 @@ fm14: cmpi 0, r10, 13 addi r3, 0, 7 bl fmfound -fm15: +fm15: /* not found, error code to be issued on LEDs */ addi r7, 0, LED_SDRAM_CODE_2 addis r6, 0, 0x1000 @@ -827,7 +827,7 @@ fmerr: bl fmerr fmfound:addi r6, 0, 1 subf r3, r6, r3 - mtlr r5 /* restore lr */ + mtlr r5 /* restore lr */ blr /*--------------------------------------------------------------------- */ @@ -838,13 +838,13 @@ fmfound:addi r6, 0, 1 find_size_code: mflr r5 - + addi r3, r15, 0 /* density */ addi r7, 0, 0 fs01: andi. r6, r3, 0x01 cmpi 0, r6, 1 beq fs04 - + addi r7, r7, 1 cmpi 0, r7, 7 bge fs02 @@ -866,7 +866,7 @@ fs04: addi r3, r7, 0 addi r6, 0, 1 subf r3, r6, r3 fs05: - mtlr r5 /* restore lr */ + mtlr r5 /* restore lr */ blr /*--------------------------------------------------------------------- */ @@ -895,9 +895,9 @@ fc01: srw r6, r14, r4 /* */ addi r7, r19, 0 /* SDRAM cycle time for highest CAS latenty */ bl fc03 -fc02: +fc02: addi r7, r20, 0 /* SDRAM cycle time for next-highest CAS latenty */ -fc03: +fc03: addi r8, r7, 0 addi r9, 0, 4 srw r7, r7, r9 @@ -910,7 +910,7 @@ fc03: bgt fc05 addi r3, r2, 0 bl fc05 -fc04: +fc04: addi r7, r21, 0 /* SDRAM cycle time for third-highest CAS latenty */ addi r8, r7, 0 addi r9, 0, 2 @@ -933,9 +933,9 @@ fc06: addi r6, 0, 1 cmpi 0, r4, 0 bne fc01 -fc07: +fc07: - mtlr r5 /* restore lr */ + mtlr r5 /* restore lr */ blr #endif @@ -1000,7 +1000,7 @@ fc07: /* Size: 2 MB */ /* Usage: read/write */ /* Width: 32 bit */ - + /* Walnut fpga pb7ap */ /* 0 1 8 1 5 2 8 0 */ /* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */ diff --git a/board/exbitgen/u-boot.lds b/board/exbitgen/u-boot.lds index 36f9491963..7dd539178e 100644 --- a/board/exbitgen/u-boot.lds +++ b/board/exbitgen/u-boot.lds @@ -98,7 +98,7 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - *(.got) + *(.got) _GOT2_TABLE_ = .; *(.got2) _FIXUP_TABLE_ = .; diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c index 4921f5b14d..434055ce67 100644 --- a/board/gen860t/gen860t.c +++ b/board/gen860t/gen860t.c @@ -303,7 +303,7 @@ board_poweroff(void) } #ifdef CONFIG_POST -/* +/* * Returns 1 if keys pressed to start the power-on long-running tests * Called from board_init_f(). */ diff --git a/board/icecube/Makefile b/board/icecube/Makefile new file mode 100644 index 0000000000..eb5ed591a9 --- /dev/null +++ b/board/icecube/Makefile @@ -0,0 +1,47 @@ + +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/icecube/config.mk b/board/icecube/config.mk new file mode 100644 index 0000000000..9913cfb486 --- /dev/null +++ b/board/icecube/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# IceCube board +# + +TEXT_BASE = 0xfff00000 +# TEXT_BASE = 0x00100000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/icecube/flash.c b/board/icecube/flash.c new file mode 100644 index 0000000000..9164bd9ea1 --- /dev/null +++ b/board/icecube/flash.c @@ -0,0 +1,480 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it + * has nothing to do with the flash chip being 8-bit or 16-bit. + */ +#ifdef CONFIG_FLASH_16BIT +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; +#define FLASH_ID_MASK 0xFFFF +#else +typedef unsigned char FLASH_PORT_WIDTH; +typedef volatile unsigned char FLASH_PORT_WIDTHV; +#define FLASH_ID_MASK 0xFF +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define ORMASK(size) ((-size) & OR_AM_MSK) + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x02aa + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); +static flash_info_t *flash_get_info(ulong base); + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + int i; + extern void flash_preinit(void); + + flash_preinit(); + + /* Init: no FLASHes known */ + for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { + ulong flashbase = CFG_FLASH_BASE; + + memset(&flash_info[i], 0, sizeof(flash_info_t)); + + flash_info[i].size = + flash_get_size((FPW *)flashbase, &flash_info[i]); + + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", + i, flash_info[i].size); + } + + size += flash_info[i].size; + } +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + + return size ? size : 1; +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t *info) +{ + FPWV *base = (FPWV *)(info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW)0x00FF00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = (FPW)0x00F000F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->start[0] <= base && base <= info->start[0] + info->size - 1) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + uchar *boottype; + uchar *bootletter; + uchar *fmt; + uchar botbootletter[] = "B"; + uchar topbootletter[] = "T"; + uchar botboottype[] = "bottom boot sector"; + uchar topboottype[] = "top boot sector"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + /* check for top or bottom boot, if it applies */ + if (info->flash_id & FLASH_BTYPE) { + boottype = botboottype; + bootletter = botbootletter; + } + else { + boottype = topboottype; + bootletter = topbootletter; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMDLV065D: + fmt = "29LV065 (64 Mbit, uniform sectors)\n"; + break; + default: + fmt = "Unknown Chip Type\n"; + break; + } + + printf (fmt, bootletter, boottype); + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + int i; + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + udelay(100); + switch (addr[0] & 0xff) { + + case (uchar)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case (uchar)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { + + case (FPW)AMD_ID_LV065D: + info->flash_id += FLASH_AMDLV065D; + info->sector_count = 128; + info->size = 0x00800000; + for( i = 0; i < info->sector_count; i++ ) + info->start[i] = (ulong)addr + (i * 0x10000); + break; /* => 8 or 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* => no or unknown flash */ + } + + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect; + int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMDLV065D: + break; + case FLASH_UNKNOWN: + default: + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + last = get_timer(0); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && rcode == 0; sect++) { + + if (info->protect[sect] != 0) /* protected, skip it */ + continue; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr = (FPWV *)(info->start[sect]); + if (intel) { + *addr = (FPW)0x00500050; /* clear status register */ + *addr = (FPW)0x00200020; /* erase setup */ + *addr = (FPW)0x00D000D0; /* erase confirm */ + } + else { + /* must be AMD style if not Intel */ + FPWV *base; /* first address in bank */ + + base = (FPWV *)(info->start[0]); + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + *addr = (FPW)0x00300030; /* erase sector */ + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* wait at least 50us for AMD, 80us for Intel. + * Let's wait 1 ms. + */ + udelay (1000); + + while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + + if (intel) { + /* suspend erase */ + *addr = (FPW)0x00B000B0; + } + + flash_reset(info); /* reset to read mode */ + rcode = 1; /* failed */ + break; + } + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) {/* every second */ + putc ('.'); + last = get_timer(0); + } + } + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) { /* every second */ + putc ('.'); + last = get_timer(0); + } + + flash_reset(info); /* reset to read mode */ + } + + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left ) + data += *((uchar *)addr + i); + else + data += *src++; + } + + /* write one word to the flash */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + res = write_word_amd(info, (FPWV *)addr, data); + break; + default: + /* unknown flash type, error! */ + printf ("missing or unknown FLASH type\n"); + res = 1; /* not really a timeout, but gives error */ + break; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + + base = (FPWV *)(info->start[0]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + /* data polling for D7 */ + while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00F000F0; /* reset bank */ + res = 1; + } + } + + return (res); +} diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c new file mode 100644 index 0000000000..916e78055e --- /dev/null +++ b/board/icecube/icecube.c @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +long int initdram (int board_type) +{ +#ifndef CFG_RAMBOOT + /* configure SDRAM start/end */ +#if defined(CONFIG_MPC5200) + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x00000018;/* 32M at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x02000000;/* disabled */ + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000; + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002; + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = 0x408d0000; + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002; + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004; + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000; + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000; +#elif defined(CONFIG_MGT5100) + *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; + *(vu_long *)MPC5XXX_SDRAM_STOP = 0x000007ff;/* 64M */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004; + + /* address select register */ + *(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0000; + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0002; + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000; + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0002; + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0004; + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000; + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x514f0000; +#endif +#else +#ifdef CONFIG_MGT5100 + *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ +#endif +#endif + /* return total ram size */ +#if defined(CONFIG_MGT5100) + return (64 * 1024 * 1024); +#elif defined(CONFIG_MPC5200) + return (32 * 1024 * 1024); +#endif +} + +int checkboard (void) +{ +#if defined(CONFIG_MPC5200) + puts ("Board: Motorola MPC5200 (IceCube)\n"); +#elif defined(CONFIG_MGT5100) + puts ("Board: Motorola MGT5100 (IceCube)\n"); +#endif + return 0; +} + +void flash_preinit(void) +{ + /* + * Now, when we are in RAM, enable flash write + * access for detection process. + * Note that CS_BOOT cannot be cleared when + * executing in flash. + */ +#if defined(CONFIG_MGT5100) + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ +#endif + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ +} diff --git a/board/icecube/u-boot.lds b/board/icecube/u-boot.lds new file mode 100644 index 0000000000..d999dd16ad --- /dev/null +++ b/board/icecube/u-boot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c index cf824082cf..b869bf3460 100644 --- a/board/lwmon/lwmon.c +++ b/board/lwmon/lwmon.c @@ -1073,7 +1073,7 @@ static int key_pressed(void) #endif /* CONFIG_MODEM_SUPPORT */ #ifdef CONFIG_POST -/* +/* * Returns 1 if keys pressed to start the power-on long-running tests * Called from board_init_f(). */ diff --git a/board/omap1510inn/platform.S b/board/omap1510inn/platform.S index 6bad32d4bb..a1602d14c6 100644 --- a/board/omap1510inn/platform.S +++ b/board/omap1510inn/platform.S @@ -42,171 +42,171 @@ _TEXT_BASE: .globl platformsetup platformsetup: - /* - * Configure 1510 pins functions to match our board. - */ - ldr r0, REG_PULL_DWN_CTRL_0 - ldr r1, VAL_PULL_DWN_CTRL_0 - str r1, [r0] - ldr r0, REG_PULL_DWN_CTRL_1 - ldr r1, VAL_PULL_DWN_CTRL_1 - str r1, [r0] - ldr r0, REG_PULL_DWN_CTRL_2 - ldr r1, VAL_PULL_DWN_CTRL_2 - str r1, [r0] - ldr r0, REG_PULL_DWN_CTRL_3 - ldr r1, VAL_PULL_DWN_CTRL_3 - str r1, [r0] - ldr r0, REG_FUNC_MUX_CTRL_4 - ldr r1, VAL_FUNC_MUX_CTRL_4 - str r1, [r0] - ldr r0, REG_FUNC_MUX_CTRL_5 - ldr r1, VAL_FUNC_MUX_CTRL_5 - str r1, [r0] - ldr r0, REG_FUNC_MUX_CTRL_6 - ldr r1, VAL_FUNC_MUX_CTRL_6 - str r1, [r0] - ldr r0, REG_FUNC_MUX_CTRL_7 - ldr r1, VAL_FUNC_MUX_CTRL_7 - str r1, [r0] - ldr r0, REG_FUNC_MUX_CTRL_8 - ldr r1, VAL_FUNC_MUX_CTRL_8 - str r1, [r0] - ldr r0, REG_FUNC_MUX_CTRL_9 - ldr r1, VAL_FUNC_MUX_CTRL_9 - str r1, [r0] - ldr r0, REG_FUNC_MUX_CTRL_A - ldr r1, VAL_FUNC_MUX_CTRL_A - str r1, [r0] - ldr r0, REG_FUNC_MUX_CTRL_B - ldr r1, VAL_FUNC_MUX_CTRL_B - str r1, [r0] - ldr r0, REG_FUNC_MUX_CTRL_C - ldr r1, VAL_FUNC_MUX_CTRL_C - str r1, [r0] - ldr r0, REG_VOLTAGE_CTRL_0 - ldr r1, VAL_VOLTAGE_CTRL_0 - str r1, [r0] - ldr r0, REG_TEST_DBG_CTRL_0 - ldr r1, VAL_TEST_DBG_CTRL_0 - str r1, [r0] - ldr r0, REG_MOD_CONF_CTRL_0 - ldr r1, VAL_MOD_CONF_CTRL_0 - str r1, [r0] + /* + * Configure 1510 pins functions to match our board. + */ + ldr r0, REG_PULL_DWN_CTRL_0 + ldr r1, VAL_PULL_DWN_CTRL_0 + str r1, [r0] + ldr r0, REG_PULL_DWN_CTRL_1 + ldr r1, VAL_PULL_DWN_CTRL_1 + str r1, [r0] + ldr r0, REG_PULL_DWN_CTRL_2 + ldr r1, VAL_PULL_DWN_CTRL_2 + str r1, [r0] + ldr r0, REG_PULL_DWN_CTRL_3 + ldr r1, VAL_PULL_DWN_CTRL_3 + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_4 + ldr r1, VAL_FUNC_MUX_CTRL_4 + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_5 + ldr r1, VAL_FUNC_MUX_CTRL_5 + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_6 + ldr r1, VAL_FUNC_MUX_CTRL_6 + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_7 + ldr r1, VAL_FUNC_MUX_CTRL_7 + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_8 + ldr r1, VAL_FUNC_MUX_CTRL_8 + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_9 + ldr r1, VAL_FUNC_MUX_CTRL_9 + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_A + ldr r1, VAL_FUNC_MUX_CTRL_A + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_B + ldr r1, VAL_FUNC_MUX_CTRL_B + str r1, [r0] + ldr r0, REG_FUNC_MUX_CTRL_C + ldr r1, VAL_FUNC_MUX_CTRL_C + str r1, [r0] + ldr r0, REG_VOLTAGE_CTRL_0 + ldr r1, VAL_VOLTAGE_CTRL_0 + str r1, [r0] + ldr r0, REG_TEST_DBG_CTRL_0 + ldr r1, VAL_TEST_DBG_CTRL_0 + str r1, [r0] + ldr r0, REG_MOD_CONF_CTRL_0 + ldr r1, VAL_MOD_CONF_CTRL_0 + str r1, [r0] - /* Move to 1510 mode */ - ldr r0, REG_COMP_MODE_CTRL_0 - ldr r1, VAL_COMP_MODE_CTRL_0 - str r1, [r0] + /* Move to 1510 mode */ + ldr r0, REG_COMP_MODE_CTRL_0 + ldr r1, VAL_COMP_MODE_CTRL_0 + str r1, [r0] - /* Set up Traffic Ctlr*/ - ldr r0, REG_TC_IMIF_PRIO - mov r1, #0x0 - str r1, [r0] - ldr r0, REG_TC_EMIFS_PRIO - str r1, [r0] - ldr r0, REG_TC_EMIFF_PRIO - str r1, [r0] + /* Set up Traffic Ctlr*/ + ldr r0, REG_TC_IMIF_PRIO + mov r1, #0x0 + str r1, [r0] + ldr r0, REG_TC_EMIFS_PRIO + str r1, [r0] + ldr r0, REG_TC_EMIFF_PRIO + str r1, [r0] - ldr r0, REG_TC_EMIFS_CONFIG - ldr r1, [r0] - bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */ - bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */ - str r1, [r0] /* EMIFS GlB Configuration. (value 0x12 most likely) */ + ldr r0, REG_TC_EMIFS_CONFIG + ldr r1, [r0] + bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */ + bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */ + str r1, [r0] /* EMIFS GlB Configuration. (value 0x12 most likely) */ - /* Setup some clock domains */ - ldr r1, =OMAP1510_CLKS - ldr r0, REG_ARM_IDLECT2 - strh r1, [r0] /* CLKM, Clock domain control. */ + /* Setup some clock domains */ + ldr r1, =OMAP1510_CLKS + ldr r0, REG_ARM_IDLECT2 + strh r1, [r0] /* CLKM, Clock domain control. */ - mov r1, #0x01 /* PER_EN bit */ - ldr r0, REG_ARM_RSTCT2 - strh r1, [r0] /* CLKM; Peripheral reset. */ + mov r1, #0x01 /* PER_EN bit */ + ldr r0, REG_ARM_RSTCT2 + strh r1, [r0] /* CLKM; Peripheral reset. */ - /* Set CLKM to Sync-Scalable */ - /* I supposidly need to enable the dsp clock before switching */ - mov r1, #0x1000 - ldr r0, REG_ARM_SYSST - strh r1, [r0] - mov r0, #0x400 + /* Set CLKM to Sync-Scalable */ + /* I supposidly need to enable the dsp clock before switching */ + mov r1, #0x1000 + ldr r0, REG_ARM_SYSST + strh r1, [r0] + mov r0, #0x400 1: - subs r0, r0, #0x1 /* wait for any bubbles to finish */ - bne 1b + subs r0, r0, #0x1 /* wait for any bubbles to finish */ + bne 1b - ldr r1, VAL_ARM_CKCTL /* use 12Mhz ref, PER must be <= 50Mhz so /2 */ - ldr r0, REG_ARM_CKCTL - strh r1, [r0] + ldr r1, VAL_ARM_CKCTL /* use 12Mhz ref, PER must be <= 50Mhz so /2 */ + ldr r0, REG_ARM_CKCTL + strh r1, [r0] - /* setup DPLL 1 */ - ldr r1, VAL_DPLL1_CTL - ldr r0, REG_DPLL1_CTL - strh r1, [r0] - ands r1, r1, #0x10 /* Check if PLL is enabled. */ - beq lock_end /* Do not look for lock if BYPASS selected */ + /* setup DPLL 1 */ + ldr r1, VAL_DPLL1_CTL + ldr r0, REG_DPLL1_CTL + strh r1, [r0] + ands r1, r1, #0x10 /* Check if PLL is enabled. */ + beq lock_end /* Do not look for lock if BYPASS selected */ 2: - ldrh r1, [r0] - ands r1, r1, #0x01 /* Check the LOCK bit. */ - beq 2b /* ...loop until bit goes hi. */ + ldrh r1, [r0] + ands r1, r1, #0x01 /* Check the LOCK bit. */ + beq 2b /* ...loop until bit goes hi. */ lock_end: - /* Set memory timings corresponding to the new clock speed */ + /* Set memory timings corresponding to the new clock speed */ - /* Check execution location to determine current execution location - * and branch to appropriate initialization code. - */ - mov r0, #0x10000000 /* Load physical SDRAM base. */ - mov r1, pc /* Get current execution location. */ - cmp r1, r0 /* Compare. */ - bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */ + /* Check execution location to determine current execution location + * and branch to appropriate initialization code. + */ + mov r0, #0x10000000 /* Load physical SDRAM base. */ + mov r1, pc /* Get current execution location. */ + cmp r1, r0 /* Compare. */ + bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */ - /* - * Delay for SDRAM initialization. - */ - mov r3, #0x1800 /* value should be checked */ + /* + * Delay for SDRAM initialization. + */ + mov r3, #0x1800 /* value should be checked */ 3: - subs r3, r3, #0x1 /* Decrement count */ - bne 3b + subs r3, r3, #0x1 /* Decrement count */ + bne 3b - /* - * Set SDRAM control values. Disable refresh before MRS command. - */ - ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG /* get good value */ - bic r3, r0, #0xC /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */ - orr r3, r3, #0x8000000 /* (BIT27) Disable CLK when Power down or Self-Refresh */ - orr r3, r3, #0x4000000 /* BIT26 Power Down Enable */ - ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */ - str r3, [r2] /* Store the passed value with AR disabled. */ + /* + * Set SDRAM control values. Disable refresh before MRS command. + */ + ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG /* get good value */ + bic r3, r0, #0xC /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */ + orr r3, r3, #0x8000000 /* (BIT27) Disable CLK when Power down or Self-Refresh */ + orr r3, r3, #0x4000000 /* BIT26 Power Down Enable */ + ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */ + str r3, [r2] /* Store the passed value with AR disabled. */ - ldr r1, VAL_TC_EMIFF_MRS /* get MRS value */ - ldr r2, REG_TC_EMIFF_MRS /* Point to MRS register. */ - str r1, [r2] /* Store the passed value.*/ + ldr r1, VAL_TC_EMIFF_MRS /* get MRS value */ + ldr r2, REG_TC_EMIFF_MRS /* Point to MRS register. */ + str r1, [r2] /* Store the passed value.*/ - ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */ - str r0, [r2] /* Store the passed value. */ + ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */ + str r0, [r2] /* Store the passed value. */ - /* - * Delay for SDRAM initialization. - */ - mov r3, #0x1800 + /* + * Delay for SDRAM initialization. + */ + mov r3, #0x1800 4: - subs r3, r3, #1 /* Decrement count. */ - bne 4b + subs r3, r3, #1 /* Decrement count. */ + bne 4b skip_sdram: - /* slow interface */ - ldr r1, VAL_TC_EMIFS_CS0_CONFIG - ldr r0, REG_TC_EMIFS_CS0_CONFIG - str r1, [r0] /* Chip Select 0 */ - ldr r1, VAL_TC_EMIFS_CS1_CONFIG - ldr r0, REG_TC_EMIFS_CS1_CONFIG - str r1, [r0] /* Chip Select 1 */ - ldr r1, VAL_TC_EMIFS_CS2_CONFIG - ldr r0, REG_TC_EMIFS_CS2_CONFIG - str r1, [r0] /* Chip Select 2 */ - ldr r1, VAL_TC_EMIFS_CS3_CONFIG - ldr r0, REG_TC_EMIFS_CS3_CONFIG - str r1, [r0] /* Chip Select 3 */ + /* slow interface */ + ldr r1, VAL_TC_EMIFS_CS0_CONFIG + ldr r0, REG_TC_EMIFS_CS0_CONFIG + str r1, [r0] /* Chip Select 0 */ + ldr r1, VAL_TC_EMIFS_CS1_CONFIG + ldr r0, REG_TC_EMIFS_CS1_CONFIG + str r1, [r0] /* Chip Select 1 */ + ldr r1, VAL_TC_EMIFS_CS2_CONFIG + ldr r0, REG_TC_EMIFS_CS2_CONFIG + str r1, [r0] /* Chip Select 2 */ + ldr r1, VAL_TC_EMIFS_CS3_CONFIG + ldr r0, REG_TC_EMIFS_CS3_CONFIG + str r1, [r0] /* Chip Select 3 */ /* Next, Enable the RS232 Line Drivers in the FPGA. */ /* Also, power on the audio CODEC's amplifier here, */ @@ -217,22 +217,22 @@ skip_sdram: /* Also, disable the CODEC's clocks. */ /* omap1510-HelenP1 [specific] */ - ldr r0, REG_FPGA_POWER - mov r1, #0 - ldr r2, REG_FPGA_DIP_SWITCH - ldrb r3, [r2] - cmp r3, #0x8 - movne r1, #0x62 /* Enable the RS232 Line Drivers in the EPLD */ - strb r1, [r0] - ldr r0, REG_FPGA_AUDIO - mov r1, #0x0 /* Disable sound driver (CODEC clocks) */ - strb r1, [r0] + ldr r0, REG_FPGA_POWER + mov r1, #0 + ldr r2, REG_FPGA_DIP_SWITCH + ldrb r3, [r2] + cmp r3, #0x8 + movne r1, #0x62 /* Enable the RS232 Line Drivers in the EPLD */ + strb r1, [r0] + ldr r0, REG_FPGA_AUDIO + mov r1, #0x0 /* Disable sound driver (CODEC clocks) */ + strb r1, [r0] - /* back to arch calling code */ + /* back to arch calling code */ mov pc, lr /* the literal pools origin */ - .ltorg + .ltorg /* OMAP configuration registers */ REG_FUNC_MUX_CTRL_0: /* 32 bits */ @@ -288,13 +288,13 @@ REG_TC_EMIFF_PRIO: /* 32 bits */ REG_TC_EMIFS_CONFIG: /* 32 bits */ .word 0xfffecc0c REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ - .word 0xfffecc10 + .word 0xfffecc10 REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ - .word 0xfffecc14 + .word 0xfffecc14 REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ - .word 0xfffecc18 + .word 0xfffecc18 REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ - .word 0xfffecc1c + .word 0xfffecc1c REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */ .word 0xfffecc20 REG_TC_EMIFF_MRS: /* 32 bits */ @@ -303,27 +303,27 @@ REG_TC_EMIFF_MRS: /* 32 bits */ REG_ARM_CKCTL: /* 16 bits */ .word 0xfffece00 REG_ARM_IDLECT2: /* 16 bits */ - .word 0xfffece08 + .word 0xfffece08 REG_ARM_RSTCT2: /* 16 bits */ - .word 0xfffece14 + .word 0xfffece14 REG_ARM_SYSST: /* 16 bits */ - .word 0xfffece18 + .word 0xfffece18 /* DPLL control registers */ REG_DPLL1_CTL: /* 16 bits */ .word 0xfffecf00 /* identification code register */ REG_IDCODE: /* 32 bits */ - .word 0xfffed404 + .word 0xfffed404 /* Innovator specific */ REG_FPGA_LED_DIGIT: /* 8 bits (not used on Innovator) */ - .word 0x08000003 + .word 0x08000003 REG_FPGA_POWER: /* 8 bits */ - .word 0x08000005 + .word 0x08000005 REG_FPGA_AUDIO: /* 8 bits (not used on Innovator) */ .word 0x0800000c REG_FPGA_DIP_SWITCH: /* 8 bits (not used on Innovator) */ - .word 0x0800000e + .word 0x0800000e VAL_COMP_MODE_CTRL_0: .word 0x0000eaef @@ -359,8 +359,8 @@ VAL_VOLTAGE_CTRL_0: .word 0x00000007 VAL_TEST_DBG_CTRL_0: /* See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 . - * This slows down internal SRAM accesses. - */ + * This slows down internal SRAM accesses. + */ .word 0x00000007 VAL_MOD_CONF_CTRL_0: .word 0x0b000008 diff --git a/board/omap1510inn/u-boot.lds b/board/omap1510inn/u-boot.lds index caa1d24b4f..46cf9dc556 100644 --- a/board/omap1510inn/u-boot.lds +++ b/board/omap1510inn/u-boot.lds @@ -27,23 +27,23 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { - . = 0x00000000; + . = 0x00000000; - . = ALIGN(4); + . = ALIGN(4); .text : { cpu/arm925t/start.o (.text) *(.text) } - . = ALIGN(4); - .rodata : { *(.rodata) } + . = ALIGN(4); + .rodata : { *(.rodata) } - . = ALIGN(4); - .data : { *(.data) } + . = ALIGN(4); + .data : { *(.data) } - . = ALIGN(4); - .got : { *(.got) } + . = ALIGN(4); + .got : { *(.got) } __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } @@ -51,8 +51,8 @@ SECTIONS armboot_end_data = .; - . = ALIGN(4); - .bss : { *(.bss) } + . = ALIGN(4); + .bss : { *(.bss) } armboot_end = .; } diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c index 79d56f33b0..eb7e416df5 100644 --- a/board/sacsng/sacsng.c +++ b/board/sacsng/sacsng.c @@ -818,7 +818,7 @@ int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); #endif /* CONFIG_MISC_INIT_R */ #ifdef CONFIG_POST -/* +/* * Returns 1 if keys pressed to start the power-on long-running tests * Called from board_init_f(). */ diff --git a/board/sl8245/u-boot.lds b/board/sl8245/u-boot.lds index e0d0b17634..6bd865e8cc 100644 --- a/board/sl8245/u-boot.lds +++ b/board/sl8245/u-boot.lds @@ -129,4 +129,3 @@ SECTIONS _end = . ; PROVIDE (end = .); } - diff --git a/board/tqm8xx/flash.c b/board/tqm8xx/flash.c index 6ce6235d3f..d949c2eb6b 100644 --- a/board/tqm8xx/flash.c +++ b/board/tqm8xx/flash.c @@ -305,7 +305,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) info->sector_count = 64; info->size = 0x00800000; /* => 8 MB */ break; - } + } switch(addr[14]) { case AMD_ID_LV128U_2: if (addr[15] != AMD_ID_LV128U_3) { -- cgit v1.2.1