From 6904e377465db6c731adf4fb0eb67e55454606d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Wed, 30 Jan 2013 11:19:13 +0000 Subject: imx: mx6q DDR3 init: Fix tMRD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3. For all DDR3 speed bins: tMRD(min) = 4 nCK tMOD(min) = max(12 nCK, 15 ns) Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5]. Signed-off-by: Benoît Thébaudeau Tested-by: Eric Nelson --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index c86cd407a2..9ac8027a9f 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -110,7 +110,7 @@ DATA 4 0x021b0018 0x00081740 DATA 4 0x021b001c 0x00008000 DATA 4 0x021b000c 0x555A7975 -DATA 4 0x021b0010 0xFF538E64 +DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2 -- cgit v1.2.1 From aa53149e1108ab9395ee8309ce6f90480bfdf34b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Wed, 30 Jan 2013 11:19:14 +0000 Subject: imx: mx6q DDR3 init: Fix tXPR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MMDC1_MDOR.tXPR should be set as specified for the JEDEC DDR3 timing tXPR. For all DDR3 speed bins: tXPR(min) = max(5 nCK, tRFC(min) + 10 ns) tRFC(2 Gb) = 160 ns All the users of mx6q_4x_mt41j128.cfg have a 2-Gb density (Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and Micron MT41K128M16JT-125:K for i.MX6 SABRE SD). Hence, MMDC1_MDOR.tXPR should be set to max(5 nCK, 170 ns), which is 170 ns and 91 nCK at 532 MHz, encoded as 0x5A in the bit-field MMDC1_MDOR[23:16]. Signed-off-by: Benoît Thébaudeau --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 9ac8027a9f..1c24da826a 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2 -DATA 4 0x021b0030 0x005B0E21 +DATA 4 0x021b0030 0x005A0E21 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0040 0x00000027 -- cgit v1.2.1 From ada02b84636242f5142f74016dbedb50889e93d0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Wed, 30 Jan 2013 11:19:15 +0000 Subject: imx: mx6q DDR3 init: Fix SDE_to_RST MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded as 0x10 for the bit-field MMDC1_MDOR[13:8]. Signed-off-by: Benoît Thébaudeau --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 1c24da826a..73317b54a8 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2 -DATA 4 0x021b0030 0x005A0E21 +DATA 4 0x021b0030 0x005A1021 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0040 0x00000027 -- cgit v1.2.1 From 1791b1f97f71bb4f110ca851ab10479640b7bc05 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Wed, 30 Jan 2013 11:19:16 +0000 Subject: imx: mx6q DDR3 init: Fix RST_to_CKE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded as 0x23 for the bit-field MMDC1_MDOR[5:0]. Signed-off-by: Benoît Thébaudeau --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 73317b54a8..51f8c359a5 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2 -DATA 4 0x021b0030 0x005A1021 +DATA 4 0x021b0030 0x005A1023 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0040 0x00000027 -- cgit v1.2.1 From b42b5b7a243ab3923fd80ab03f950f036b6e1329 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Wed, 30 Jan 2013 11:19:17 +0000 Subject: imx: mx6q DDR3 init: Fix MR0.PPD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28]. Signed-off-by: Benoît Thébaudeau --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 51f8c359a5..d50858d1b7 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x00008033 DATA 4 0x021b001c 0x0000803B DATA 4 0x021b001c 0x00428031 DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x09408030 -DATA 4 0x021b001c 0x09408038 +DATA 4 0x021b001c 0x19408030 +DATA 4 0x021b001c 0x19408038 DATA 4 0x021b001c 0x04008040 DATA 4 0x021b001c 0x04008048 -- cgit v1.2.1 From 7c92c540754a0c3756d467a9b0695f2a40d1fe86 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Wed, 30 Jan 2013 11:19:18 +0000 Subject: imx: mx6q DDR3 init: Benefit from available CL = 7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All the users of mx6q_4x_mt41j128.cfg (DDR3-1333H Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and DDR3-1600K Micron MT41K128M16JT-125:K for i.MX6 SABRE SD) support the optional down binning to DDR3-1066F (CL = 7, CWL = 6), which is possible at 532 MHz, so use it. In these conditions: tRCD(min) = 13.125 ns tRP(min) = 13.125 ns tRC(min) = max(tRAS(min, DDR3-1333H), tRAS(min, DDR3-1600K)) + tRP(min) tRAS(min, DDR3-1333H) = 36 ns tRAS(min, DDR3-1600K) = 35 ns MMDC1_MDCFG0.tCL should be set to 7 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG0[3:0]. MR0.CL should be set as in MMDC1_MDCFG0.tCL, i.e. to 7 nCK, which is encoded as 0x6 in MRS.LMR.MR0.{A6:A4, A2} and MMDC1_MDSCR[22:20, 18]. MMDC1_MDCFG1.tCWL should be set to 6 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG1[2:0]. MMDC1_MDCFG1.tRCD should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[31:29]. MMDC1_MDCFG1.tRP should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[28:26]. MMDC1_MDCFG1.tRC should be set to 49.125 ns, which is 27 nCK at 532 MHz, encoded as 0x1A in the bit-field MMDC1_MDCFG1[25:21]. Signed-off-by: Benoît Thébaudeau --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index d50858d1b7..f4cae5eeb9 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -109,8 +109,8 @@ DATA 4 0x021b4828 0x33333333 DATA 4 0x021b0018 0x00081740 DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b000c 0x555A7975 -DATA 4 0x021b0010 0xFF538F64 +DATA 4 0x021b000c 0x555A7974 +DATA 4 0x021b0010 0xDB538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2 @@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x00008033 DATA 4 0x021b001c 0x0000803B DATA 4 0x021b001c 0x00428031 DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x19408030 -DATA 4 0x021b001c 0x19408038 +DATA 4 0x021b001c 0x19308030 +DATA 4 0x021b001c 0x19308038 DATA 4 0x021b001c 0x04008040 DATA 4 0x021b001c 0x04008048 -- cgit v1.2.1 From 74cf809972658eae18c33e078c05a7cc9c9460c9 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Tue, 19 Feb 2013 10:07:00 +0000 Subject: i.MX6: mx6qsabrelite: indent with tabs This patch has no functional changes and simply replaces leading spaces with tabs. Signed-off-by: Eric Nelson --- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 106 +++++++++++++------------- 1 file changed, 53 insertions(+), 53 deletions(-) (limited to 'board') diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index f010d0c60d..c6c64c3440 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -46,12 +46,12 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ @@ -72,9 +72,9 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - return 0; + return 0; } iomux_v3_cfg_t const uart1_pads[] = { @@ -83,8 +83,8 @@ iomux_v3_cfg_t const uart1_pads[] = { }; iomux_v3_cfg_t const uart2_pads[] = { - MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -132,23 +132,23 @@ struct i2c_pads_info i2c_pad_info2 = { }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const enet_pads1[] = { @@ -227,7 +227,7 @@ iomux_v3_cfg_t const usb_pads[] = { static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); } #ifdef CONFIG_USB_EHCI_MX6 @@ -246,55 +246,55 @@ int board_ehci_hcd_init(int port) #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) { - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; - if (cfg->esdhc_base == USDHC3_BASE_ADDR) { + if (cfg->esdhc_base == USDHC3_BASE_ADDR) { gpio_direction_input(IMX_GPIO_NR(7, 0)); ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); - } else { + } else { gpio_direction_input(IMX_GPIO_NR(2, 6)); ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); - } + } - return ret; + return ret; } int board_mmc_init(bd_t *bis) { - s32 status = 0; - u32 index = 0; + s32 status = 0; + u32 index = 0; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); break; default: - printf("Warning: you configured more USDHC controllers" + printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; - } + return status; + } - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - } + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } - return status; + return status; } #endif @@ -732,8 +732,8 @@ int overwrite_console(void) int board_init(void) { - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_MXC_SPI setup_spi(); @@ -746,14 +746,14 @@ int board_init(void) setup_sata(); #endif - return 0; + return 0; } int checkboard(void) { - puts("Board: MX6Q-Sabre Lite\n"); + puts("Board: MX6Q-Sabre Lite\n"); - return 0; + return 0; } struct button_key { -- cgit v1.2.1 From cfb8b9d3351ebb519f9c27e0aeba814e7c81ee85 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Tue, 19 Feb 2013 10:07:01 +0000 Subject: i.MX6: consolidate pad names for multi-CPU boards Rename all i.MX6 pad declarations to MX6_PAD_x, so a board may support either i.MX6Quad/Dual (MX6Q) or i.MX6Dual-Lite/Solo (MX6DL) by including the proper header. Boards mx6qarm2, mx6qsabreauto, mx6qsabrelite, and mx6qsabresd only support MX6Q, so they include mx6q_pins.h. Signed-off-by: Eric Nelson --- board/freescale/mx6qarm2/mx6qarm2.c | 78 +++++------ board/freescale/mx6qsabreauto/mx6qsabreauto.c | 60 ++++---- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 190 +++++++++++++------------- board/freescale/mx6qsabresd/mx6qsabresd.c | 102 +++++++------- 4 files changed, 215 insertions(+), 215 deletions(-) (limited to 'board') diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index ee20d4fc28..ff7f5e83a0 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include @@ -55,53 +55,53 @@ int dram_init(void) } iomux_v3_cfg_t const uart4_pads[] = { - MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { - MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 9e3700e1ee..91cc0073bd 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include @@ -54,26 +54,26 @@ int dram_init(void) } iomux_v3_cfg_t const uart4_pads[] = { - MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { - MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -82,18 +82,18 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usdhc3_pads[] = { - MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_uart(void) diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index c6c64c3440..f7b7f07754 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include @@ -78,13 +78,13 @@ int dram_init(void) } iomux_v3_cfg_t const uart1_pads[] = { - MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const uart2_pads[] = { - MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -92,13 +92,13 @@ iomux_v3_cfg_t const uart2_pads[] = { /* I2C1, SGTL5000 */ struct i2c_pads_info i2c_pad_info0 = { .scl = { - .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC, + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC, .gp = IMX_GPIO_NR(3, 21) }, .sda = { - .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC, + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC, .gp = IMX_GPIO_NR(3, 28) } }; @@ -106,13 +106,13 @@ struct i2c_pads_info i2c_pad_info0 = { /* I2C2 Camera, MIPI */ struct i2c_pads_info i2c_pad_info1 = { .scl = { - .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC, + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC, .gp = IMX_GPIO_NR(4, 12) }, .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC, + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, .gp = IMX_GPIO_NR(4, 13) } }; @@ -120,86 +120,86 @@ struct i2c_pads_info i2c_pad_info1 = { /* I2C3, J15 - RGB connector */ struct i2c_pads_info i2c_pad_info2 = { .scl = { - .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC, - .gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC, + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC, .gp = IMX_GPIO_NR(1, 5) }, .sda = { - .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC, - .gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC, + .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, .gp = IMX_GPIO_NR(7, 11) } }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const enet_pads1[] = { - MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), /* pin 35 - 1 (PHY_AD2) on reset */ - MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 32 - 1 - (MODE0) all */ - MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 31 - 1 - (MODE1) all */ - MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 28 - 1 - (MODE2) all */ - MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 27 - 1 - (MODE3) all */ - MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 42 PHY nRST */ - MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads2[] = { - MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; /* Button assignments for J14 */ static iomux_v3_cfg_t const button_pads[] = { /* Menu */ - MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Back */ - MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Labelled Search (mapped to Power under Android) */ - MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Home */ - MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Volume Down */ - MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Volume Up */ - MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -221,7 +221,7 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usb_pads[] = { - MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_uart(void) @@ -306,10 +306,10 @@ u32 get_board_rev(void) #ifdef CONFIG_MXC_SPI iomux_v3_cfg_t const ecspi1_pads[] = { /* SS1 */ - MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), }; void setup_spi(void) @@ -403,44 +403,44 @@ int setup_sata(void) static iomux_v3_cfg_t const backlight_pads[] = { /* Backlight on RGB connector: J15 */ - MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL), #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) /* Backlight on LVDS connector: J6 */ - MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) }; static iomux_v3_cfg_t const rgb_pads[] = { - MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, - MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, - MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, - MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, - MX6Q_PAD_DI0_PIN4__GPIO_4_20, - MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, - MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, - MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, - MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, - MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, - MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, - MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, - MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, - MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, - MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, - MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, - MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, - MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, - MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, - MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, - MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, - MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, - MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, - MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, - MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, - MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, - MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, - MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, - MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, + MX6_PAD_DI0_PIN4__GPIO_4_20, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, }; struct display_info_t { diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c index 65c4a1a4f3..2b3926aaf3 100644 --- a/board/freescale/mx6qsabresd/mx6qsabresd.c +++ b/board/freescale/mx6qsabresd/mx6qsabresd.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include @@ -52,28 +52,28 @@ int dram_init(void) } iomux_v3_cfg_t const uart1_pads[] = { - MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { - MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), /* AR8031 PHY Reset */ - MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -87,44 +87,44 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usdhc2_pads[] = { - MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; static void setup_iomux_uart(void) -- cgit v1.2.1 From f94669f30656cd05bbc75f6c799a1b06c493f3d2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 23 Feb 2013 02:43:03 +0000 Subject: mxs: m28: Enable power to USB port 0 The USB port 0 can now be used alongside the USB port 1, thus enable power to it. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Otavio Salvador Cc: Stefano Babic --- board/denx/m28evk/m28evk.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'board') diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c index d93efafad0..aff7c1fe5e 100644 --- a/board/denx/m28evk/m28evk.c +++ b/board/denx/m28evk/m28evk.c @@ -57,6 +57,10 @@ int board_early_init_f(void) mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 | MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP); gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0); + + mxs_iomux_setup_pad(MX28_PAD_AUART3_RX__GPIO_3_12 | + MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP); + gpio_direction_output(MX28_PAD_AUART3_RX__GPIO_3_12, 0); #endif return 0; -- cgit v1.2.1 From 920178d38133e76da8b0394b0d3f088e7afbaee7 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 23 Feb 2013 02:43:06 +0000 Subject: mx23evk: Adjust DRAM control register to use full 128MB of RAM Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of full 128MB of RAM. Signed-off-by: Otavio Salvador --- board/freescale/mx23evk/spl_boot.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'board') diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c index 6007433605..b6f4e7eff2 100644 --- a/board/freescale/mx23evk/spl_boot.c +++ b/board/freescale/mx23evk/spl_boot.c @@ -98,6 +98,16 @@ const iomux_cfg_t iomux_setup[] = { (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), }; +#define HW_DRAM_CTL14 (0x38 >> 2) +#define CS_MAP 0x3 +#define INTAREF 0x2 +#define HW_DRAM_CTL14_CONFIG (INTAREF << 8 | CS_MAP) + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG; +} + void board_init_ll(void) { mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); -- cgit v1.2.1 From 36c7c9250d7c4717808a637da74e59a29a235848 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 23 Feb 2013 02:43:09 +0000 Subject: mx23_olinuxino: Add support for status LED This allow user to know if the bootloader is running, even without a serial console. Signed-off-by: Otavio Salvador --- board/olimex/mx23_olinuxino/mx23_olinuxino.c | 7 +++++++ board/olimex/mx23_olinuxino/spl_boot.c | 4 ++++ 2 files changed, 11 insertions(+) (limited to 'board') diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index 6a6053b385..2501417613 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -28,6 +28,9 @@ #include #include #include +#ifdef CONFIG_STATUS_LED +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -67,5 +70,9 @@ int board_init(void) /* Adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + status_led_set(STATUS_LED_BOOT, STATUS_LED_STATE); +#endif + return 0; } diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c index 7def8bc3e9..3bbf5ad7a3 100644 --- a/board/olimex/mx23_olinuxino/spl_boot.c +++ b/board/olimex/mx23_olinuxino/spl_boot.c @@ -84,6 +84,10 @@ const iomux_cfg_t iomux_setup[] = { MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + /* Green LED */ + MX23_PAD_SSP1_DETECT__GPIO_2_1 | + (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL), + /* MMC 0 */ MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP, MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP, -- cgit v1.2.1 From ebe1d17006001adfa375335acdd56f326264aeb8 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 2 Mar 2013 05:17:29 +0000 Subject: mx23_olinuxino: Enable USB support This enabled USB support for the mx23_olinuxino board. Signed-off-by: Otavio Salvador --- board/olimex/mx23_olinuxino/mx23_olinuxino.c | 5 +++++ board/olimex/mx23_olinuxino/spl_boot.c | 4 ++++ 2 files changed, 9 insertions(+) (limited to 'board') diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index 2501417613..92527177ca 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -45,6 +45,11 @@ int board_early_init_f(void) /* SSP0 clock at 96MHz */ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); +#ifdef CONFIG_CMD_USB + /* Enable LAN9512 */ + gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1); +#endif + return 0; } diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c index 3bbf5ad7a3..a96c293c0a 100644 --- a/board/olimex/mx23_olinuxino/spl_boot.c +++ b/board/olimex/mx23_olinuxino/spl_boot.c @@ -95,6 +95,10 @@ const iomux_cfg_t iomux_setup[] = { MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP, MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP, MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP, + + /* Ethernet */ + MX23_PAD_GPMI_ALE__GPIO_0_17 | + (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), }; void board_init_ll(void) -- cgit v1.2.1 From 1b097cff51a6781ce3a0036b7f0a9e53864c9727 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 28 Feb 2013 14:35:02 +0000 Subject: mx6: Provide a structure for accessing HDMI registers Provide a structure for accessing HDMI registers, so that we can use proper read/write accessors. Signed-off-by: Fabio Estevam Tested-by: Eric Nelson --- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 28 +++++++++++---------------- 1 file changed, 11 insertions(+), 17 deletions(-) (limited to 'board') diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index f7b7f07754..5b69a6d2de 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -455,32 +455,26 @@ struct display_info_t { static int detect_hdmi(struct display_info_t const *dev) { - return __raw_readb(HDMI_ARB_BASE_ADDR+HDMI_PHY_STAT0) & HDMI_PHY_HPD; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD; } static void enable_hdmi(struct display_info_t const *dev) { + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; u8 reg; printf("%s: setup HDMI monitor\n", __func__); - reg = __raw_readb( - HDMI_ARB_BASE_ADDR - +HDMI_PHY_CONF0); + reg = readb(&hdmi->phy_conf0); reg |= HDMI_PHY_CONF0_PDZ_MASK; - __raw_writeb(reg, - HDMI_ARB_BASE_ADDR - +HDMI_PHY_CONF0); + writeb(reg, &hdmi->phy_conf0); + udelay(3000); reg |= HDMI_PHY_CONF0_ENTMDS_MASK; - __raw_writeb(reg, - HDMI_ARB_BASE_ADDR - +HDMI_PHY_CONF0); + writeb(reg, &hdmi->phy_conf0); udelay(3000); reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; - __raw_writeb(reg, - HDMI_ARB_BASE_ADDR - +HDMI_PHY_CONF0); - __raw_writeb(HDMI_MC_PHYRSTZ_ASSERT, - HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ); + writeb(reg, &hdmi->phy_conf0); + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); } static int detect_i2c(struct display_info_t const *dev) @@ -638,6 +632,7 @@ static void setup_display(void) struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; int reg; @@ -654,8 +649,7 @@ static void setup_display(void) writel(reg, &mxc_ccm->CCGR2); /* clear HDMI PHY reset */ - __raw_writeb(HDMI_MC_PHYRSTZ_DEASSERT, - HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ); + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); -- cgit v1.2.1 From 7315e3bf2cc95abf9ae53f43ccbd31c6f638aacd Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 7 Mar 2013 07:32:53 +0000 Subject: mx23_olinuxino: Fix warning for implicit declaration Fixes a build warning of implicit declaration of gpio_direction_output, as bellow: ,---- | mx23_olinuxino.c: In function 'board_early_init_f': | mx23_olinuxino.c:51:2: warning: implicit declaration | of function 'gpio_direction_output' | [-Wimplicit-function-declaration] `---- Signed-off-by: Otavio Salvador --- board/olimex/mx23_olinuxino/mx23_olinuxino.c | 1 + 1 file changed, 1 insertion(+) (limited to 'board') diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index 92527177ca..9ed7718152 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -23,6 +23,7 @@ */ #include +#include #include #include #include -- cgit v1.2.1 From d67b0d97b156f9ec2fc4c838d84b1e510d6e49b4 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Mon, 11 Mar 2013 08:44:53 +0000 Subject: Add Boundary Devices Nitrogen6X boards Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg | 58 ++ board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg | 58 ++ board/boundary/nitrogen6x/6x_bootscript.txt | 63 ++ .../boundary/nitrogen6x/6x_bootscript_android.txt | 64 ++ .../nitrogen6x/6x_bootscript_android_recovery.txt | 64 ++ board/boundary/nitrogen6x/6x_upgrade.txt | 45 ++ board/boundary/nitrogen6x/800mhz_2x128mx16.cfg | 58 ++ board/boundary/nitrogen6x/800mhz_2x256mx16.cfg | 58 ++ board/boundary/nitrogen6x/800mhz_4x128mx16.cfg | 57 ++ board/boundary/nitrogen6x/800mhz_4x256mx16.cfg | 58 ++ board/boundary/nitrogen6x/Makefile | 41 + board/boundary/nitrogen6x/README | 92 +++ board/boundary/nitrogen6x/clocks.cfg | 46 ++ board/boundary/nitrogen6x/ddr-setup.cfg | 112 +++ board/boundary/nitrogen6x/nitrogen6dl.cfg | 45 ++ board/boundary/nitrogen6x/nitrogen6dl2g.cfg | 45 ++ board/boundary/nitrogen6x/nitrogen6q.cfg | 45 ++ board/boundary/nitrogen6x/nitrogen6q2g.cfg | 45 ++ board/boundary/nitrogen6x/nitrogen6s.cfg | 45 ++ board/boundary/nitrogen6x/nitrogen6s1g.cfg | 45 ++ board/boundary/nitrogen6x/nitrogen6x.c | 895 +++++++++++++++++++++ 21 files changed, 2039 insertions(+) create mode 100644 board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg create mode 100644 board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg create mode 100644 board/boundary/nitrogen6x/6x_bootscript.txt create mode 100644 board/boundary/nitrogen6x/6x_bootscript_android.txt create mode 100644 board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt create mode 100644 board/boundary/nitrogen6x/6x_upgrade.txt create mode 100644 board/boundary/nitrogen6x/800mhz_2x128mx16.cfg create mode 100644 board/boundary/nitrogen6x/800mhz_2x256mx16.cfg create mode 100644 board/boundary/nitrogen6x/800mhz_4x128mx16.cfg create mode 100644 board/boundary/nitrogen6x/800mhz_4x256mx16.cfg create mode 100644 board/boundary/nitrogen6x/Makefile create mode 100644 board/boundary/nitrogen6x/README create mode 100644 board/boundary/nitrogen6x/clocks.cfg create mode 100644 board/boundary/nitrogen6x/ddr-setup.cfg create mode 100644 board/boundary/nitrogen6x/nitrogen6dl.cfg create mode 100644 board/boundary/nitrogen6x/nitrogen6dl2g.cfg create mode 100644 board/boundary/nitrogen6x/nitrogen6q.cfg create mode 100644 board/boundary/nitrogen6x/nitrogen6q2g.cfg create mode 100644 board/boundary/nitrogen6x/nitrogen6s.cfg create mode 100644 board/boundary/nitrogen6x/nitrogen6s1g.cfg create mode 100644 board/boundary/nitrogen6x/nitrogen6x.c (limited to 'board') diff --git a/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg new file mode 100644 index 0000000000..16a37d0ced --- /dev/null +++ b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7974 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42720306 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026F0266 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4273030A +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02740240 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45393B3E +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x403A3747 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40434541 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x473E4A3B +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0011000E +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x000E001B +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00190015 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00070018 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg new file mode 100644 index 0000000000..0607703825 --- /dev/null +++ b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43040319 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03040279 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43040321 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03030251 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4d434248 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c4d +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x34424543 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x49324933 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001a0017 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00170027 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000a001f +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/6x_bootscript.txt b/board/boundary/nitrogen6x/6x_bootscript.txt new file mode 100644 index 0000000000..061b3a44b5 --- /dev/null +++ b/board/boundary/nitrogen6x/6x_bootscript.txt @@ -0,0 +1,63 @@ +setenv bootargs enable_wait_mode=off +setenv nextcon 0; + +if hdmidet ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24 + setenv fbmem "fbmem=28M"; + setexpr nextcon $nextcon + 1 +else + echo "------ no HDMI monitor"; +fi + +i2c dev 2 +if i2c probe 0x04 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbmem "fbmem=10M"; + else + setenv fbmem ${fbmem},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no Freescale display"; +fi + +if i2c probe 0x38 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbmem "fbmem=10M"; + else + setenv fbmem ${fbmem},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 1024x600 display"; +fi + +if i2c probe 0x48 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbmem "fbmem=10M"; + else + setenv fbmem ${fbmem},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 800x480 display"; +fi + +while test "3" -ne $nextcon ; do + setenv bootargs $bootargs video=mxcfb${nextcon}:off ; + setexpr nextcon $nextcon + 1 ; +done + +setenv bootargs $bootargs $fbmem +setenv bootargs "$bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 rootwait" + +if test "sata" = "${dtype}" ; then + setenv bootargs "$bootargs root=/dev/sda1" ; +else + setenv "bootargs $bootargs root=/dev/mmcblk0p1" ; +fi +${fs}load ${dtype} ${disk}:1 10800000 /boot/uImage && bootm 10800000 ; +echo "Error loading kernel image" diff --git a/board/boundary/nitrogen6x/6x_bootscript_android.txt b/board/boundary/nitrogen6x/6x_bootscript_android.txt new file mode 100644 index 0000000000..0982cf8054 --- /dev/null +++ b/board/boundary/nitrogen6x/6x_bootscript_android.txt @@ -0,0 +1,64 @@ +${dtype} dev ${disk} + +setenv bootargs enable_wait_mode=off +setenv nextcon 0; +setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ; + +i2c dev 2 + +if i2c probe 0x04 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no Freescale display"; +fi + +if i2c probe 0x38 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 1024x600 display"; +fi + +if i2c probe 0x48 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 800x480 display"; +fi + +if hdmidet ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=28M"; + else + setenv fbcon ${fbcon},28M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no HDMI monitor"; +fi + +while test "3" -ne $nextcon ; do + setenv bootargs $bootargs video=mxcfb${nextcon}:off ; + setexpr nextcon $nextcon + 1 ; +done + +setenv bootargs $bootargs fbcon=$fbcon +${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000 +echo "Error loading kernel image" diff --git a/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt b/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt new file mode 100644 index 0000000000..0982cf8054 --- /dev/null +++ b/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt @@ -0,0 +1,64 @@ +${dtype} dev ${disk} + +setenv bootargs enable_wait_mode=off +setenv nextcon 0; +setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ; + +i2c dev 2 + +if i2c probe 0x04 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no Freescale display"; +fi + +if i2c probe 0x38 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 1024x600 display"; +fi + +if i2c probe 0x48 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 800x480 display"; +fi + +if hdmidet ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=28M"; + else + setenv fbcon ${fbcon},28M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no HDMI monitor"; +fi + +while test "3" -ne $nextcon ; do + setenv bootargs $bootargs video=mxcfb${nextcon}:off ; + setexpr nextcon $nextcon + 1 ; +done + +setenv bootargs $bootargs fbcon=$fbcon +${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000 +echo "Error loading kernel image" diff --git a/board/boundary/nitrogen6x/6x_upgrade.txt b/board/boundary/nitrogen6x/6x_upgrade.txt new file mode 100644 index 0000000000..0d8e8e542b --- /dev/null +++ b/board/boundary/nitrogen6x/6x_upgrade.txt @@ -0,0 +1,45 @@ +setenv stdout serial,vga +echo "check U-Boot" ; +setenv offset 0x400 +if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk}:1 12000000 u-boot.nopadding ; then + echo "read $filesize bytes from SD card" ; + if sf probe || sf probe || \ + sf probe 1 27000000 || sf probe 1 27000000 ; then + echo "probed SPI ROM" ; + if sf read 0x12400000 $offset $filesize ; then + if cmp.b 0x12000000 0x12400000 $filesize ; then + echo "------- U-Boot versions match" ; + else + echo "Need U-Boot upgrade" ; + echo "Program in 5 seconds" ; + for n in 5 4 3 2 1 ; do + echo $n ; + sleep 1 ; + done + echo "erasing" ; + sf erase 0 0x50000 ; + # two steps to prevent bricking + echo "programming" ; + sf write 0x12000000 $offset $filesize ; + echo "verifying" ; + if sf read 0x12400000 $offset $filesize ; then + if cmp.b 0x12000000 0x12400000 $filesize ; then + while echo "---- U-Boot upgraded. reset" ; do + sleep 120 + done + else + echo "Read verification error" ; + fi + else + echo "Error re-reading EEPROM" ; + fi + fi + else + echo "Error reading boot loader from EEPROM" ; + fi + else + echo "Error initializing EEPROM" ; + fi ; +else + echo "No U-Boot image found on SD card" ; +fi diff --git a/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg new file mode 100644 index 0000000000..de33e650a1 --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg new file mode 100644 index 0000000000..19707cfe22 --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg new file mode 100644 index 0000000000..dd6a423205 --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420F020F +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x01760175 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x41640171 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015E0160 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45464B4A +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x49484A46 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40402E32 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3A3A3231 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x003A003A +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0030002F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x002F0038 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00270039 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg new file mode 100644 index 0000000000..d5d06e2686 --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/Makefile b/board/boundary/nitrogen6x/Makefile new file mode 100644 index 0000000000..fe1e5e0c2e --- /dev/null +++ b/board/boundary/nitrogen6x/Makefile @@ -0,0 +1,41 @@ +# +# Copyright (C) 2012-2013, Guennadi Liakhovetski +# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. +# Copyright (C) 2013, Boundary Devices +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := nitrogen6x.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README new file mode 100644 index 0000000000..50490931e0 --- /dev/null +++ b/board/boundary/nitrogen6x/README @@ -0,0 +1,92 @@ +U-Boot for the Boundary Devices Nitrogen6X and +Freescale i.MX6Q SabreLite boards + +This file contains information for the port of +U-Boot to the Boundary Devices Nitrogen6X and +Freescale i.MX6Q SabreLite boards. + +1. Boot source, boot from SPI NOR +--------------------------------- +The configuration in this directory supports both the +Nitrogen6X and Freescale SabreLite board, but in a +different fashion from Freescale's implementation in +board/freescale/mx6qsabrelite. + +In particular, this image supports booting from SPI NOR +and saving the environment to SPI NOR. + +It does not support 'boot from SD' at offset 0x400 +except through the 'bmode' command. + http://lists.denx.de/pipermail/u-boot/2012-August/131151.html + +2. Boots using 6x_bootscript on SATA or SD card +----------------------------------------------- +The default bootcmd for these boards is configured +to look for and source a boot script named '6x_bootscript' +in the root of the first partition of the following +devices: + + sata 0 + mmc 0 + mmc 1 + +They're searched in the order listed above, trying both the +ext2 and fat filesystems. + +2. Maintaining the SPI NOR +-------------------------- +A couple of convenience commands + + clearenv - clear environment to factory default + upgradeu - look and source a boot script named + '6x_upgrade' to upgrade the U-Boot version + in SPI NOR. The search is the same as for + 6x_bootscript described above. + +3. Display support +------------------ +U-Boot support for the following displays is configured by +default: + + HDMI - 1024 x 768 for maximum compatibility + Hannstar-XGA - 1024 x 768 LVDS (Freescale part number MCIMX-LVDS1) + wsvga-lvds - 1024 x 600 LVDS (Boundary p/n Nit6X_1024x600) + wvga-rgb - 800 x 480 RGB (Boundary p/n Nit6X_800x480) + +Since the ipuv3_fb display driver currently supports only a single display, +this code auto-detects panel by probing the HDMI Phy for Hot Plug Detect +or the I2C touch controller of the LVDS and RGB displays in the priority +listed above. + +Setting 'panel' environment variable to one of the names above will +override auto-detection and force activation of the specified panel. + +4. Building +------------ + +To build U-Boot for one of the Nitrogen6x or SabreLite board: + + make nitrogen6x_config + make u-boot.imx + +Note that 'nitrogen6x' is a placeholder. The complete list of supported +board configurations is shown in tha MAINTAINERS file: + nitrogen6q i.MX6Q/6D 1GB + nitrogen6dl i.MX6DL 1GB + nitrogen6s i.MX6S 512MB + nitrogen6q2g i.MX6Q/6D 2GB + nitrogen6dl2g i.MX6DL 2GB + nitrogen6s1g i.MX6S 1GB + +The -6q variants support either the i.MX6Quad or i.MX6Dual processors +and are configured for a 64-bit memory bus at 1066 MHz. + +The -6dl variants also use a 64-bit memory bus, operated at 800MHz. + +The -6s variants use a 32-bit memory bus at 800MHz. + +If you place the u-boot.imx into a single-partition SD card +along with a binary version of the boot script 6x_upgrade.txt, +you can program it using 'upgradeu': + + U-Boot> run upgradeu diff --git a/board/boundary/nitrogen6x/clocks.cfg b/board/boundary/nitrogen6x/clocks.cfg new file mode 100644 index 0000000000..e7d1f86cdb --- /dev/null +++ b/board/boundary/nitrogen6x/clocks.cfg @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/boundary/nitrogen6x/ddr-setup.cfg b/board/boundary/nitrogen6x/ddr-setup.cfg new file mode 100644 index 0000000000..c3158120a4 --- /dev/null +++ b/board/boundary/nitrogen6x/ddr-setup.cfg @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + +/* + * MDMISC mirroring interleaved (row/bank/col) + */ +DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 + +/* + * MDSCR con_req + */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg new file mode 100644 index 0000000000..d6da96c5e8 --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_4x128mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg new file mode 100644 index 0000000000..0b1c35c314 --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_4x256mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg new file mode 100644 index 0000000000..680a853683 --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6q.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "1066mhz_4x128mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg new file mode 100644 index 0000000000..f57ab0eedf --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "1066mhz_4x256mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg new file mode 100644 index 0000000000..b5af5cc1b5 --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6s.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_2x128mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg new file mode 100644 index 0000000000..5aeefc8783 --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_2x256mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c new file mode 100644 index 0000000000..0dbb6d26bf --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -0,0 +1,895 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013, Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define WEAK_PULLUP (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define WEAK_PULLDOWN (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) + +int dram_init(void) +{ + gd->ram_size = CONFIG_DDR_MB * 1024 * 1024; + + return 0; +} + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* I2C1, SGTL5000 */ +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +/* I2C2 Camera, MIPI */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* I2C3, J15 - RGB connector */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC, + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, + .gp = IMX_GPIO_NR(7, 11) + } +}; + +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* pin 35 - 1 (PHY_AD2) on reset */ + MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 42 PHY nRST */ + MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +/* wl1271 pads on nitrogen6x */ +iomux_v3_cfg_t const wl12xx_pads[] = { + (MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK) + | MUX_PAD_CTRL(WEAK_PULLDOWN), + (MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK) + | MUX_PAD_CTRL(OUTPUT_40OHM), + (MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK) + | MUX_PAD_CTRL(OUTPUT_40OHM), +}; +#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) +#define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15) +#define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16) + +/* Button assignments for J14 */ +static iomux_v3_cfg_t const button_pads[] = { + /* Menu */ + MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Back */ + MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Labelled Search (mapped to Power under Android) */ + MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Home */ + MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Volume Down */ + MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Volume Up */ + MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */ + gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */ + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + + /* Need delay 10ms according to KSZ9021 spec */ + udelay(1000 * 10); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */ + gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */ + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + +iomux_v3_cfg_t const usb_pads[] = { + MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + + /* Reset USB hub */ + gpio_direction_output(IMX_GPIO_NR(7, 12), 0); + mdelay(2); + gpio_set_value(IMX_GPIO_NR(7, 12), 1); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) { + gpio_direction_input(IMX_GPIO_NR(7, 0)); + ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); + } else { + gpio_direction_input(IMX_GPIO_NR(2, 6)); + ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } + + return status; +} +#endif + +u32 get_board_rev(void) +{ + return 0x63000; +} + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + /* SS1 */ + MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; + +void setup_spi(void) +{ + gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + /* min rx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + /* scan phy 4,5,6,7 */ + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + free(bus); + return 0; + } + printf("using phy at %d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } +#endif + return 0; +} + +static void setup_buttons(void) +{ + imx_iomux_v3_setup_multiple_pads(button_pads, + ARRAY_SIZE(button_pads)); +} + +#ifdef CONFIG_CMD_SATA + +int setup_sata(void) +{ + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; + int ret = enable_sata_clock(); + if (ret) + return ret; + + clrsetbits_le32(&iomuxc_regs->gpr[13], + IOMUXC_GPR13_SATA_MASK, + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB + |IOMUXC_GPR13_SATA_PHY_7_SATA2M + |IOMUXC_GPR13_SATA_SPEED_3G + |(3<phy_stat0) & HDMI_PHY_HPD; +} + +static void enable_hdmi(struct display_info_t const *dev) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + u8 reg; + printf("%s: setup HDMI monitor\n", __func__); + reg = readb(&hdmi->phy_conf0); + reg |= HDMI_PHY_CONF0_PDZ_MASK; + writeb(reg, &hdmi->phy_conf0); + + udelay(3000); + reg |= HDMI_PHY_CONF0_ENTMDS_MASK; + writeb(reg, &hdmi->phy_conf0); + udelay(3000); + reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; + writeb(reg, &hdmi->phy_conf0); + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); +} + +static int detect_i2c(struct display_info_t const *dev) +{ + return ((0 == i2c_set_bus_num(dev->bus)) + && + (0 == i2c_probe(dev->addr))); +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + writel(reg, &iomux->gpr[2]); + gpio_direction_output(LVDS_BACKLIGHT_GP, 1); +} + +static void enable_rgb(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads( + rgb_pads, + ARRAY_SIZE(rgb_pads)); + gpio_direction_output(RGB_BACKLIGHT_GP, 1); +} + +static struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x4, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x38, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "wsvga-lvds", + .refresh = 60, + .xres = 1024, + .yres = 600, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x48, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = detect_i2c, + .enable = enable_rgb, + .mode = { + .name = "wvga-rgb", + .refresh = 57, + .xres = 800, + .yres = 480, + .pixclock = 37037, + .left_margin = 40, + .right_margin = 60, + .upper_margin = 10, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; + +int board_video_skip(void) +{ + int i; + int ret; + char const *panel = getenv("panel"); + if (!panel) { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + struct display_info_t const *dev = displays+i; + if (dev->detect(dev)) { + panel = dev->mode.name; + printf("auto-detected panel %s\n", panel); + break; + } + } + if (!panel) { + panel = displays[0].mode.name; + printf("No panel detected: default to %s\n", panel); + } + } else { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + if (!strcmp(panel, displays[i].mode.name)) + break; + } + } + if (i < ARRAY_SIZE(displays)) { + ret = ipuv3_fb_init(&displays[i].mode, 0, + displays[i].pixfmt); + if (!ret) { + displays[i].enable(displays+i); + printf("Display: %s (%ux%u)\n", + displays[i].mode.name, + displays[i].mode.xres, + displays[i].mode.yres); + } else + printf("LCD %s cannot be configured: %d\n", + displays[i].mode.name, ret); + } else { + printf("unsupported panel %s\n", panel); + ret = -EINVAL; + } + return (0 != ret); +} + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + + int reg; + + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET + |MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* Turn on HDMI PHY clock */ + reg = __raw_readl(&mxc_ccm->CCGR2); + reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK + |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; + writel(reg, &mxc_ccm->CCGR2); + + /* clear HDMI PHY reset */ + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); + + /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ + writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); + writel(0x13<pfd_480_set); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3<cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK + |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK + |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + <chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + <gpr[3]); + + /* backlights off until needed */ + imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); + gpio_direction_input(LVDS_BACKLIGHT_GP); + gpio_direction_input(RGB_BACKLIGHT_GP); +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + /* Disable wl1271 For Nitrogen6w */ + gpio_direction_input(WL12XX_WL_IRQ_GP); + gpio_direction_output(WL12XX_WL_ENABLE_GP, 0); + gpio_direction_output(WL12XX_BT_ENABLE_GP, 0); + + imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); + setup_buttons(); + +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + + return 0; +} + +int checkboard(void) +{ + if (gpio_get_value(WL12XX_WL_IRQ_GP)) + puts("Board: Nitrogen6X\n"); + else + puts("Board: SABRE Lite\n"); + + return 0; +} + +struct button_key { + char const *name; + unsigned gpnum; + char ident; +}; + +static struct button_key const buttons[] = { + {"back", IMX_GPIO_NR(2, 2), 'B'}, + {"home", IMX_GPIO_NR(2, 4), 'H'}, + {"menu", IMX_GPIO_NR(2, 1), 'M'}, + {"search", IMX_GPIO_NR(2, 3), 'S'}, + {"volup", IMX_GPIO_NR(7, 13), 'V'}, + {"voldown", IMX_GPIO_NR(4, 5), 'v'}, +}; + +/* + * generate a null-terminated string containing the buttons pressed + * returns number of keys pressed + */ +static int read_keys(char *buf) +{ + int i, numpressed = 0; + for (i = 0; i < ARRAY_SIZE(buttons); i++) { + if (!gpio_get_value(buttons[i].gpnum)) + buf[numpressed++] = buttons[i].ident; + } + buf[numpressed] = '\0'; + return numpressed; +} + +static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char envvalue[ARRAY_SIZE(buttons)+1]; + int numpressed = read_keys(envvalue); + setenv("keybd", envvalue); + return numpressed == 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "Tests for keypresses, sets 'keybd' environment variable", + "Returns 0 (true) to shell if key is pressed." +); + +#ifdef CONFIG_PREBOOT +static char const kbd_magic_prefix[] = "key_magic"; +static char const kbd_command_prefix[] = "key_cmd"; + +static void preboot_keys(void) +{ + int numpressed; + char keypress[ARRAY_SIZE(buttons)+1]; + numpressed = read_keys(keypress); + if (numpressed) { + char *kbd_magic_keys = getenv("magic_keys"); + char *suffix; + /* + * loop over all magic keys + */ + for (suffix = kbd_magic_keys; *suffix; ++suffix) { + char *keys; + char magic[sizeof(kbd_magic_prefix) + 1]; + sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); + keys = getenv(magic); + if (keys) { + if (!strcmp(keys, keypress)) + break; + } + } + if (*suffix) { + char cmd_name[sizeof(kbd_command_prefix) + 1]; + char *cmd; + sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); + cmd = getenv(cmd_name); + if (cmd) { + setenv("preboot", cmd); + return; + } + } + } +} +#endif + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_PREBOOT + preboot_keys(); +#endif + +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + return 0; +} -- cgit v1.2.1 From 19a0f7fa271de0345bb2df90d443c547c41e8037 Mon Sep 17 00:00:00 2001 From: "fabio.estevam@freescale.com" Date: Thu, 14 Mar 2013 02:32:55 +0000 Subject: nitrogen: Use unsigned long to specify the total RAM size When building for the nitrogen boards with 2GiB the following warning happens: nitrogen6x.c:89:38: warning: integer overflow in expression [-Woverflow] 2GiB can not fit in 32-bits, so use ulong instead. Reported-by: Albert Aribaud Signed-off-by: Fabio Estevam --- board/boundary/nitrogen6x/nitrogen6x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 0dbb6d26bf..229c237839 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -86,7 +86,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = CONFIG_DDR_MB * 1024 * 1024; + gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); return 0; } -- cgit v1.2.1