From 7d0b8cfeaa930b5946b993373a21b41ea0746be0 Mon Sep 17 00:00:00 2001 From: Justin Waters Date: Wed, 13 Apr 2016 17:03:18 -0400 Subject: board: ge: bx50v3: Disable unused pins Certain pins are not used on the i.MX6, and should have a neutral pad configuration in order to reduce electrical interference on the board. This commit defines these pins with a default value rather than relying on the system defaults. Signed-off-by: Justin Waters Signed-off-by: Akshay Bhat Cc: Stefano Babic --- board/ge/bx50v3/bx50v3.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'board') diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 70c298d2d0..3cf51055d1 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -27,6 +27,10 @@ #include DECLARE_GLOBAL_DATA_PTR; +#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) + #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -467,6 +471,12 @@ int board_eth_init(bd_t *bis) static iomux_v3_cfg_t const misc_pads[] = { MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL), }; #define SUS_S3_OUT IMX_GPIO_NR(4, 11) #define WIFI_EN IMX_GPIO_NR(6, 14) -- cgit v1.2.1 From de708da0e87f39d99f902a5434702d6ba0f4c5e0 Mon Sep 17 00:00:00 2001 From: Akshay Bhat Date: Tue, 12 Apr 2016 18:13:57 -0400 Subject: board: ge: bx50v3: Split display setup function B450v3/B650v3 uses single channel LVDS and does not support HDMI. B850v3 uses dual channel LVDS and supports HDMI. Hence split the display setup into two different functions. Signed-off-by: Akshay Bhat Cc: Stefano Babic --- board/ge/bx50v3/bx50v3.c | 112 ++++++++++++++++++++++++++++------------------- 1 file changed, 67 insertions(+), 45 deletions(-) (limited to 'board') diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 3cf51055d1..83d97d7829 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -394,55 +394,75 @@ struct display_info_t const displays[] = {{ } } }; size_t display_count = ARRAY_SIZE(displays); -static void setup_display(void) +static void setup_display_b850v3(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - int reg; - enable_ipu_clock(); + /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */ + clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + imx_setup_hdmi(); - reg = readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; - writel(reg, &mxc_ccm->CCGR3); - - reg = readl(&mxc_ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | - MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | - (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); - writel(reg, &mxc_ccm->cs2cdr); - - reg = readl(&mxc_ccm->cscmr2); - reg |= (MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); - writel(reg, &mxc_ccm->cscmr2); - - reg = readl(&mxc_ccm->chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - writel(reg, &mxc_ccm->chsccdr); - - reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES - | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH - | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW - | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG - | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT - | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG - | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT - | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 - | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; - writel(reg, &iomux->gpr[2]); - - reg = readl(&iomux->gpr[3]); - reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | - IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | - IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 - << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 - << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); - writel(reg, &iomux->gpr[3]); + /* Set LDB_DI0 as clock source for IPU_DI0 */ + clrsetbits_le32(&mxc_ccm->chsccdr, + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK, + (CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); + + /* Turn on IPU LDB DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); + + enable_ipu_clock(); + + writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | + IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT | + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | + IOMUXC_GPR2_SPLIT_MODE_EN_MASK | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 | + IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0, + &iomux->gpr[2]); + + clrbits_le32(&iomux->gpr[3], + IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | + IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | + IOMUXC_GPR3_HDMI_MUX_CTL_MASK); +} + +static void setup_display_bx50v3(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* IPU1 DI0 clock is 480/7 = 68.5 MHz */ + setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + + /* Set LDB_DI0 as clock source for IPU_DI0 */ + clrsetbits_le32(&mxc_ccm->chsccdr, + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK, + (CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); + + /* Turn on IPU LDB DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); + + enable_ipu_clock(); + + writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, + &iomux->gpr[2]); + + clrsetbits_le32(&iomux->gpr[3], + IOMUXC_GPR3_LVDS0_MUX_CTL_MASK, + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)); /* backlights off until needed */ imx_iomux_v3_setup_multiple_pads(backlight_pads, @@ -488,7 +508,6 @@ int board_early_init_f(void) setup_iomux_uart(); - return 0; } @@ -497,7 +516,10 @@ int board_init(void) gpio_direction_output(SUS_S3_OUT, 1); gpio_direction_output(WIFI_EN, 1); #if defined(CONFIG_VIDEO_IPUV3) - setup_display(); + if (IS_ENABLED(CONFIG_TARGET_GE_B850V3)) + setup_display_b850v3(); + else + setup_display_bx50v3(); #endif /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -- cgit v1.2.1 From 494d43ec35ff3d27926ed9d668e0df4b7e6ae6d3 Mon Sep 17 00:00:00 2001 From: Akshay Bhat Date: Tue, 12 Apr 2016 18:13:58 -0400 Subject: board: ge: bx50v3: Setup LDB_DI_CLK source To generate accurate pixel clocks required by the displays we need to set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since PLL5 is disabled on reset, we need to enable PLL5. Signed-off-by: Akshay Bhat Cc: Stefano Babic --- board/ge/bx50v3/bx50v3.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'board') diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 83d97d7829..3acd4fa2d8 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -394,11 +394,46 @@ struct display_info_t const displays[] = {{ } } }; size_t display_count = ARRAY_SIZE(displays); +static void enable_videopll(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + s32 timeout = 100000; + + setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); + + /* set video pll to 910MHz (24MHz * (37+11/12)) + * video pll post div to 910/4 = 227.5MHz + */ + clrsetbits_le32(&ccm->analog_pll_video, + BM_ANADIG_PLL_VIDEO_DIV_SELECT | + BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT, + BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) | + BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0)); + + writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); + + clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); + + while (timeout--) + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) + break; + + if (timeout < 0) + printf("Warning: video pll lock timeout!\n"); + + clrsetbits_le32(&ccm->analog_pll_video, + BM_ANADIG_PLL_VIDEO_BYPASS, + BM_ANADIG_PLL_VIDEO_ENABLE); +} + static void setup_display_b850v3(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + enable_videopll(); + /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */ clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); @@ -508,6 +543,14 @@ int board_early_init_f(void) setup_iomux_uart(); +#if defined(CONFIG_VIDEO_IPUV3) + if (IS_ENABLED(CONFIG_TARGET_GE_B850V3)) + /* Set LDB clock to Video PLL */ + select_ldb_di_clock_source(MXC_PLL5_CLK); + else + /* Set LDB clock to USB PLL */ + select_ldb_di_clock_source(MXC_PLL3_SW_CLK); +#endif return 0; } -- cgit v1.2.1 From 54971ac6de20b8834882efb69dc6ad5c1d4a9915 Mon Sep 17 00:00:00 2001 From: Akshay Bhat Date: Tue, 12 Apr 2016 18:13:59 -0400 Subject: board: ge: bx50v3: Use pwm for display backlight Setup the LCD backlight brightness control pin to use PWM Signed-off-by: Akshay Bhat Cc: Stefano Babic --- board/ge/bx50v3/bx50v3.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'board') diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 3acd4fa2d8..dcf51dd7d0 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -25,6 +25,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ @@ -328,6 +329,8 @@ static iomux_v3_cfg_t const backlight_pads[] = { /* Backlight enable for LVDS display */ MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0) + /* backlight PWM brightness control */ + MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void do_enable_hdmi(struct display_info_t const *dev) @@ -595,9 +598,17 @@ int board_late_init(void) * as per specifications from CHI MEI */ mdelay(250); + /* enable backlight PWM 1 */ + pwm_init(0, 0, 0); + + /* duty cycle 5000000ns, period: 5000000ns */ + pwm_config(0, 5000000, 5000000); + /* Backlight Power */ gpio_direction_output(LVDS_BACKLIGHT_GP, 1); + pwm_enable(0); + return 0; } -- cgit v1.2.1 From 8d293f49b419dd394cdf4b7a501ad86b782efc3f Mon Sep 17 00:00:00 2001 From: Akshay Bhat Date: Tue, 12 Apr 2016 18:14:00 -0400 Subject: board: ge: bx50v3: Fix to meet LVDS display power on timing On a reset/reboot, the display power needs to be off for atleast 500ms before turning it back on. So add a delay to the boot process to meet the display timing requirement. Signed-off-by: Akshay Bhat Cc: Stefano Babic --- board/ge/bx50v3/bx50v3.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'board') diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index dcf51dd7d0..ff8f4d7b97 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -476,6 +476,13 @@ static void setup_display_bx50v3(void) struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + /* When a reset/reboot is performed the display power needs to be turned + * off for atleast 500ms. The boot time is ~300ms, we need to wait for + * an additional 200ms here. Unfortunately we use external PMIC for + * doing the reset, so can not differentiate between POR vs soft reset + */ + mdelay(200); + /* IPU1 DI0 clock is 480/7 = 68.5 MHz */ setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); -- cgit v1.2.1 From 69cc7dbf1f62492788ab810db7d8444a623c23c2 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 18 Apr 2016 09:56:16 -0300 Subject: Add initial support for Technexion's PICO-IMX6UL-EMMC board Add support for Technexion's PICO-IMX6UL-EMMC board. For information about this board, please visit: http://www.technexion.com/products/pico/pico-som/pico-imx6-emmc Signed-off-by: Richard Hu Signed-off-by: Fabio Estevam --- board/technexion/pico-imx6ul/Kconfig | 15 ++++ board/technexion/pico-imx6ul/MAINTAINERS | 7 ++ board/technexion/pico-imx6ul/Makefile | 7 ++ board/technexion/pico-imx6ul/imximage.cfg | 97 +++++++++++++++++++++++ board/technexion/pico-imx6ul/pico-imx6ul.c | 119 +++++++++++++++++++++++++++++ 5 files changed, 245 insertions(+) create mode 100644 board/technexion/pico-imx6ul/Kconfig create mode 100644 board/technexion/pico-imx6ul/MAINTAINERS create mode 100644 board/technexion/pico-imx6ul/Makefile create mode 100644 board/technexion/pico-imx6ul/imximage.cfg create mode 100644 board/technexion/pico-imx6ul/pico-imx6ul.c (limited to 'board') diff --git a/board/technexion/pico-imx6ul/Kconfig b/board/technexion/pico-imx6ul/Kconfig new file mode 100644 index 0000000000..81acd611f4 --- /dev/null +++ b/board/technexion/pico-imx6ul/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PICO_IMX6UL + +config SYS_BOARD + default "pico-imx6ul" + +config SYS_VENDOR + default "technexion" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "pico-imx6ul" + +endif diff --git a/board/technexion/pico-imx6ul/MAINTAINERS b/board/technexion/pico-imx6ul/MAINTAINERS new file mode 100644 index 0000000000..594a883d15 --- /dev/null +++ b/board/technexion/pico-imx6ul/MAINTAINERS @@ -0,0 +1,7 @@ +Technexion PICO-IMX6UL board +M: Richard Hu +M: Fabio Estevam +S: Maintained +F: board/technexion/pico-imx6ul/ +F: include/configs/pico-imx6ul.h +F: configs/pico-imx6ul_defconfig diff --git a/board/technexion/pico-imx6ul/Makefile b/board/technexion/pico-imx6ul/Makefile new file mode 100644 index 0000000000..ac8ff9e548 --- /dev/null +++ b/board/technexion/pico-imx6ul/Makefile @@ -0,0 +1,7 @@ +# (C) Copyright 2015 Technexion Ltd. +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := pico-imx6ul.o diff --git a/board/technexion/pico-imx6ul/imximage.cfg b/board/technexion/pico-imx6ul/imximage.cfg new file mode 100644 index 0000000000..9145b44887 --- /dev/null +++ b/board/technexion/pico-imx6ul/imximage.cfg @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x01380134 +DATA 4 0x021B0848 0x40404244 +DATA 4 0x021B0850 0x40405050 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x00333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D8B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x00000047 +DATA 4 0x021B0000 0x83180000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c b/board/technexion/pico-imx6ul/pico-imx6ul.c new file mode 100644 index 0000000000..c038d4326e --- /dev/null +++ b/board/technexion/pico-imx6ul/pico-imx6ul.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2015 Technexion Ltd. + * + * Author: Richard Hu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const uart6_pads[] = { + MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usb_otg_pad[] = { + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads)); +} + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad)); +} + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_usb_phy_mode(int port) +{ + return USB_INIT_DEVICE; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + setup_usb(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: PICO-IMX6UL-EMMC\n"); + + return 0; +} -- cgit v1.2.1