From 1428d8327006445a861e347e8b1640e8eb9c5edf Mon Sep 17 00:00:00 2001
From: Keerthy <j-keerthy@ti.com>
Date: Tue, 7 Jun 2016 16:05:25 +0530
Subject: arm: dra7xx: Assign omap_vcores based on board type

Currently omap_vcores which holds pmic data is being assigned based
on the SoC type. PMIC is not a part of SoC. It is logical to
to assign omap_vcores based on board type. Hence over ride the
vcores_init function and assign omap_vcores based on the board type.

Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
---
 board/ti/dra7xx/evm.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)

(limited to 'board')

diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 3fbbc9b23b..0394e4ee57 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -305,6 +305,82 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 	}
 }
 
+struct vcores_data dra752_volts = {
+	.mpu.value	= VDD_MPU_DRA7,
+	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
+	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.mpu.addr	= TPS659038_REG_ADDR_SMPS12,
+	.mpu.pmic	= &tps659038,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+	.eve.value	= VDD_EVE_DRA7,
+	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
+	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.eve.addr	= TPS659038_REG_ADDR_SMPS45,
+	.eve.pmic	= &tps659038,
+	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+	.gpu.value	= VDD_GPU_DRA7,
+	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
+	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.gpu.addr	= TPS659038_REG_ADDR_SMPS6,
+	.gpu.pmic	= &tps659038,
+	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+	.core.value	= VDD_CORE_DRA7,
+	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
+	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.core.addr	= TPS659038_REG_ADDR_SMPS7,
+	.core.pmic	= &tps659038,
+
+	.iva.value	= VDD_IVA_DRA7,
+	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
+	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.iva.addr	= TPS659038_REG_ADDR_SMPS8,
+	.iva.pmic	= &tps659038,
+	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+struct vcores_data dra722_volts = {
+	.mpu.value	= VDD_MPU_DRA7,
+	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
+	.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.mpu.addr	= TPS65917_REG_ADDR_SMPS1,
+	.mpu.pmic	= &tps659038,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+	.core.value	= VDD_CORE_DRA7,
+	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
+	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.core.addr	= TPS65917_REG_ADDR_SMPS2,
+	.core.pmic	= &tps659038,
+
+	/*
+	 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
+	 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
+	 */
+	.gpu.value	= VDD_GPU_DRA7,
+	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
+	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.gpu.addr	= TPS65917_REG_ADDR_SMPS3,
+	.gpu.pmic	= &tps659038,
+	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+	.eve.value	= VDD_EVE_DRA7,
+	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
+	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.eve.addr	= TPS65917_REG_ADDR_SMPS3,
+	.eve.pmic	= &tps659038,
+	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+	.iva.value	= VDD_IVA_DRA7,
+	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
+	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.iva.addr	= TPS65917_REG_ADDR_SMPS3,
+	.iva.pmic	= &tps659038,
+	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
 /**
  * @brief board_init
  *
@@ -390,6 +466,21 @@ void do_board_detect(void)
 }
 #endif	/* CONFIG_SPL_BUILD */
 
+void vcores_init(void)
+{
+	if (board_is_dra74x_evm()) {
+		*omap_vcores = &dra752_volts;
+	} else if (board_is_dra72x_evm()) {
+		*omap_vcores = &dra722_volts;
+	} else {
+		/* If EEPROM is not populated */
+		if (is_dra72x())
+			*omap_vcores = &dra722_volts;
+		else
+			*omap_vcores = &dra752_volts;
+	}
+}
+
 void set_muxconf_regs(void)
 {
 	do_set_mux32((*ctrl)->control_padconf_core_base,
-- 
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