From 2e95004deb6e33e33bf1b8a92a38cd2115bac4c2 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Tue, 24 Nov 2009 20:12:12 +0300 Subject: mpc83xx: Add NAND boot support for MPC8315E-RDB boards The core support for NAND booting is there already, so this patch is pretty straightforward. There is one trick though: top level Makefile expects nand_spl to be in nand_spl/board/$(BOARDDIR), but we can fully reuse the code from mpc8313erdb boards, and so to not duplicate the code we just symlink nand_spl/board/freescale/mpc8315erdb to mpc8313erdb. Signed-off-by: Anton Vorontsov o silence make during ln echo o update documentation o and avoid: $ ./MAKEALL MPC8315ERDB_NAND Configuring for MPC8315ERDB board... sdram.o: In function `fixed_sdram': /home/r1aaha/git/u-boot/nand_spl/board/freescale/mpc8313erdb/sdram.c:72: undefined reference to `udelay' by renaming udelay -> __udelay in the spirit of commit 3eb90bad651fab39cffba750ec4421a9c01d60e7 "Generic udelay() with watchdog support". Signed-off-by: Kim Phillips --- board/freescale/mpc8315erdb/config.mk | 8 ++++++ board/freescale/mpc8315erdb/mpc8315erdb.c | 42 +++++++++++++++++++++++++++++++ board/freescale/mpc8315erdb/sdram.c | 9 ++++++- 3 files changed, 58 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/mpc8315erdb/config.mk b/board/freescale/mpc8315erdb/config.mk index f76826495e..bf972fbe56 100644 --- a/board/freescale/mpc8315erdb/config.mk +++ b/board/freescale/mpc8315erdb/config.mk @@ -1 +1,9 @@ +ifndef NAND_SPL +ifeq ($(CONFIG_MK_NAND), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +endif +endif + +ifndef TEXT_BASE TEXT_BASE = 0xFE000000 +endif diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index dea4d6fe7a..d5e71dc522 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -32,6 +32,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -45,6 +47,8 @@ int board_early_init_f(void) return 0; } +#ifndef CONFIG_NAND_SPL + static u8 read_board_info(void) { u8 val8; @@ -220,3 +224,41 @@ int board_eth_init(bd_t *bis) cpu_eth_init(bis); /* Initialize TSECs first */ return pci_eth_init(bis); } + +#else /* CONFIG_NAND_SPL */ + +int checkboard(void) +{ + puts("Board: Freescale MPC8315ERDB\n"); + return 0; +} + +void board_init_f(ulong bootflag) +{ + board_early_init_f(); + NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), + CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + puts("NAND boot... "); + init_timebase(); + initdram(0); + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (gd->flags & GD_FLG_SILENT) + return; + + if (c == '\n') + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); + + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); +} + +#endif /* CONFIG_NAND_SPL */ diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c index ead7b1e0de..fe8ec1eab8 100644 --- a/board/freescale/mpc8315erdb/sdram.c +++ b/board/freescale/mpc8315erdb/sdram.c @@ -54,6 +54,7 @@ static void resume_from_sleep(void) * This is useful for faster booting in configs where the RAM is unlikely * to be changed, or for things like NAND booting where space is tight. */ +#ifndef CONFIG_SYS_RAMBOOT static long fixed_sdram(void) { volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; @@ -68,7 +69,7 @@ static long fixed_sdram(void) * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], * or the DDR2 controller may fail to initialize correctly. */ - udelay(50000); + __udelay(50000); im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; @@ -100,6 +101,12 @@ static long fixed_sdram(void) return msize; } +#else +static long fixed_sdram(void) +{ + return CONFIG_SYS_DDR_SIZE * 1024 * 1024; +} +#endif /* CONFIG_SYS_RAMBOOT */ phys_size_t initdram(int board_type) { -- cgit v1.2.1 From 1dee9be683c9b0f060452aaf1a97a34fae87f07a Mon Sep 17 00:00:00 2001 From: Reinhard Arlt Date: Tue, 8 Dec 2009 09:13:08 +0100 Subject: mpc83xx: Add support for MPC8349 esd caddy2 The caddy2 is a variant of the already supported vme8349. So we just add the differences to this board port. To better support those two boards we switched from fixed SDRAM configuration to usage of spd_sdram(). This is done by providing a board specific SPD EEPROM routine with different values for both boards. Signed-off-by: Reinhard Arlt Signed-off-by: Stefan Roese changed to use mkconfig -t option instead, plus misc codingstyle fixes. Signed-off-by: Kim Phillips --- board/esd/vme8349/vme8349.c | 195 +++++++++++++++++++++++++++++++------------- 1 file changed, 138 insertions(+), 57 deletions(-) (limited to 'board') diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c index e3bc15112d..b0ebad72b2 100644 --- a/board/esd/vme8349/vme8349.c +++ b/board/esd/vme8349/vme8349.c @@ -38,63 +38,13 @@ #endif #include #include +#include +#include +#include +#include void ddr_enable_ecc(unsigned int dram_size); -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size>>1, ddr_size_log2++) { - if (ddr_size & 1) - return -1; - } - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & - LAWAR_SIZE); - -#if (CONFIG_SYS_DDR_SIZE == 512) - im->ddr.csbnds[0].csbnds = 0x0000001f; -#else -#warning Currently any DDR size other than 512MiB is not supported -#endif - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG | 0x00330000; - - /* currently we use only one CS, so disable the other banks */ - im->ddr.csbnds[1].csbnds = 0x00000000; - im->ddr.csbnds[2].csbnds = 0x00000000; - im->ddr.csbnds[3].csbnds = 0x00000000; - im->ddr.cs_config[1] = 0; - im->ddr.cs_config[2] = 0; - im->ddr.cs_config[3] = 0; - - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - sync(); - udelay(200); - - /* enable DDR controller */ - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - return msize; -} - phys_size_t initdram(int board_type) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; @@ -103,10 +53,10 @@ phys_size_t initdram(int board_type) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - /* DDR SDRAM - Main SODIMM */ + /* DDR SDRAM - Main memory */ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; - msize = fixed_sdram(); + msize = spd_sdram(); #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* @@ -124,17 +74,148 @@ phys_size_t initdram(int board_type) int checkboard(void) { - puts("Board: esd VME8349\n"); +#ifdef VME_CADDY2 + puts("Board: esd VME-CADDY/2\n"); +#else + puts("Board: esd VME-CPU/8349\n"); +#endif return 0; } +#ifdef VME_CADDY2 +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} +#endif + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif } #endif + +int misc_init_r() +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + + clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0); + + return 0; +} + +/* + * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2 + * and VME-CADDY/2) have different SDRAM configurations. + */ +#ifdef VME_CADDY2 +#define SMALL_RAM 0xff +#define LARGE_RAM 0x00 +#else +#define SMALL_RAM 0x00 +#define LARGE_RAM 0xff +#endif + +#define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM)) + +static spd_eeprom_t default_spd_eeprom = { + SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */ + SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */ + SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */ + SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */ + SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */ + SPD_VAL(0x00, 0x00), /* 05 */ + SPD_VAL(0x40, 0x40), /* 06 */ + SPD_VAL(0x00, 0x00), /* 07 */ + SPD_VAL(0x05, 0x05), /* 08 */ + SPD_VAL(0x30, 0x30), /* 09 */ + SPD_VAL(0x45, 0x45), /* 10 */ + SPD_VAL(0x02, 0x02), /* 11 ecc used */ + SPD_VAL(0x82, 0x82), /* 12 */ + SPD_VAL(0x10, 0x10), /* 13 */ + SPD_VAL(0x08, 0x08), /* 14 */ + SPD_VAL(0x00, 0x00), /* 15 */ + SPD_VAL(0x0c, 0x0c), /* 16 */ + SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */ + SPD_VAL(0x38, 0x38), /* 18 */ + SPD_VAL(0x00, 0x00), /* 19 */ + SPD_VAL(0x02, 0x02), /* 20 */ + SPD_VAL(0x00, 0x00), /* 21 */ + SPD_VAL(0x03, 0x03), /* 22 */ + SPD_VAL(0x3d, 0x3d), /* 23 */ + SPD_VAL(0x45, 0x45), /* 24 */ + SPD_VAL(0x50, 0x50), /* 25 */ + SPD_VAL(0x45, 0x45), /* 26 */ + SPD_VAL(0x3c, 0x3c), /* 27 */ + SPD_VAL(0x28, 0x28), /* 28 */ + SPD_VAL(0x3c, 0x3c), /* 29 */ + SPD_VAL(0x2d, 0x2d), /* 30 */ + SPD_VAL(0x20, 0x80), /* 31 */ + SPD_VAL(0x20, 0x20), /* 32 */ + SPD_VAL(0x27, 0x27), /* 33 */ + SPD_VAL(0x10, 0x10), /* 34 */ + SPD_VAL(0x17, 0x17), /* 35 */ + SPD_VAL(0x3c, 0x3c), /* 36 */ + SPD_VAL(0x1e, 0x1e), /* 37 */ + SPD_VAL(0x1e, 0x1e), /* 38 */ + SPD_VAL(0x00, 0x00), /* 39 */ + SPD_VAL(0x00, 0x06), /* 40 */ + SPD_VAL(0x37, 0x37), /* 41 */ + SPD_VAL(0x4b, 0x7f), /* 42 */ + SPD_VAL(0x80, 0x80), /* 43 */ + SPD_VAL(0x18, 0x18), /* 44 */ + SPD_VAL(0x22, 0x22), /* 45 */ + SPD_VAL(0x00, 0x00), /* 46 */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + SPD_VAL(0x10, 0x10), /* 62 */ + SPD_VAL(0x7e, 0x1d), /* 63 */ + { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' }, + SPD_VAL(0x00, 0x00), /* 72 */ +#ifdef VME_CADDY2 + { "vme-caddy/2 ram " } +#else + { "vme-cpu/2 ram " } +#endif +}; + +int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int old_bus = I2C_GET_BUS(); + unsigned int l, sum; + int valid = 0; + + I2C_SET_BUS(0); + + if (i2c_read(chip, addr, alen, buffer, len) == 0) + if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) { + sum = 0; + for (l = 0; l < 63; l++) + sum = (sum + buffer[l]) & 0xff; + if (sum == buffer[63]) + valid = 1; + else + printf("Invalid checksum in EEPROM %02x %02x\n", + sum, buffer[63]); + } + + if (valid == 0) { + memcpy(buffer, (void *)&default_spd_eeprom, len); + sum = 0; + for (l = 0; l < 63; l++) + sum = (sum + buffer[l]) & 0xff; + if (sum != buffer[63]) + printf("Invalid checksum in FLASH %02x %02x\n", + sum, buffer[63]); + buffer[63] = sum; + } + + I2C_SET_BUS(old_bus); + + return 0; +} -- cgit v1.2.1 From a0daa2e06f05d97c03c59b656d50371319bf29ec Mon Sep 17 00:00:00 2001 From: Reinhard Arlt Date: Tue, 8 Dec 2009 09:21:41 +0100 Subject: mpc83xx: vme8349: Fix power up reset sequence for tsi148 Remove PCI reset, if there is a monarch PMC module. Signed-off-by: Reinhard Arlt Signed-off-by: Stefan Roese convert clrbits_be32 + setbits_be32 to clrsetbits_be32, use out_be32 to set gcr. Signed-off-by: Kim Phillips --- board/esd/vme8349/pci.c | 33 +++++++++++++++++++++++++-------- board/esd/vme8349/vme8349pin.h | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 8 deletions(-) create mode 100644 board/esd/vme8349/vme8349pin.h (limited to 'board') diff --git a/board/esd/vme8349/pci.c b/board/esd/vme8349/pci.c index d15203c145..94fd32a6fa 100644 --- a/board/esd/vme8349/pci.c +++ b/board/esd/vme8349/pci.c @@ -2,6 +2,9 @@ * pci.c -- esd VME8349 PCI board support. * Copyright (c) 2006 Wind River Systems, Inc. * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. + * Copyright (c) 2009 esd gmbh. + * + * Reinhard Arlt * * Based on MPC8349 PCI support but w/o PIB related code. * @@ -32,6 +35,7 @@ #include #include #include +#include "vme8349pin.h" DECLARE_GLOBAL_DATA_PTR; @@ -93,17 +97,22 @@ pci_init_board(void) udelay(2000); /* - * Assert/deassert PCI reset + * Assert/deassert VME reset */ - setbits_be32(&immr->gpio[0].dat, 0x00800000); - setbits_be32(&immr->gpio[0].dir, 0x00800000); - setbits_be32(&immr->gpio[1].dir, 0x08800000); + clrsetbits_be32(&immr->gpio[1].dat, + GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N, + GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N); + setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N | + GPIO2_TSI_POWERUP_RESET_N | + GPIO2_VME_RESET_N | + GPIO2_L_RESET_EN_N); + clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON); udelay(200); - setbits_be32(&immr->gpio[1].dat, 0x08000000); + setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N); udelay(200); - setbits_be32(&immr->gpio[1].dat, 0x08800000); + setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N); udelay(600000); - clrbits_be32(&immr->gpio[1].dat, 0x00100000); + clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N); /* Configure PCI Local Access Windows */ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; @@ -114,6 +123,14 @@ pci_init_board(void) udelay(2000); - if (monarch == 0) + if (monarch == 0) { mpc83xx_pci_init(1, reg, 0); + } else { + /* + * Release PCI RST Output signal + */ + out_be32(&immr->pci_ctrl[0].gcr, 0); + udelay(2000); + out_be32(&immr->pci_ctrl[0].gcr, 1); + } } diff --git a/board/esd/vme8349/vme8349pin.h b/board/esd/vme8349/vme8349pin.h new file mode 100644 index 0000000000..d1fd1b203f --- /dev/null +++ b/board/esd/vme8349/vme8349pin.h @@ -0,0 +1,36 @@ +/* + * vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition. + * Copyright (c) 2009 esd gmbh. + * + * Reinhard Arlt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __VME8349PIN_H__ +#define __VME8349PIN_H__ + +#define GPIO2_V_SCON 0x80000000 /* In: from tsi148 1: is syscon */ +#define GPIO2_VME_RESET_N 0x20000000 /* Out: to tsi148 */ +#define GPIO2_TSI_PLL_RESET_N 0x08000000 /* Out: to tsi148 */ +#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148 */ +#define GPIO2_L_RESET_EN_N 0x00100000 /* Out: 0:vme can assert cpu lrst*/ + +#endif /* of ifndef __VME8349PIN_H__ */ -- cgit v1.2.1