From ec35e12331512cf5ed0f22005d7b6fb4ccc35969 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 17 May 2016 11:56:39 +0100 Subject: MIPS: Move CONFIG_SYS_TEXT_BASE to Kconfig Move CONFIG_SYS_TEXT_BASE to Kconfig, and add default values in board Kconfig files matching what was present in their config headers. This will make it cleaner to conditionalise the value for Malta based on 32 vs 64 bit builds. Signed-off-by: Paul Burton --- board/tplink/wdr4300/Kconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'board/tplink/wdr4300/Kconfig') diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig index 902abf560d..65785bdb9c 100644 --- a/board/tplink/wdr4300/Kconfig +++ b/board/tplink/wdr4300/Kconfig @@ -12,4 +12,7 @@ config SYS_BOARD config SYS_CONFIG_NAME default "tplink_wdr4300" +config SYS_TEXT_BASE + default 0xa1000000 + endif -- cgit v1.2.1 From ace3be4f15875d74344336b9754c14274f940969 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 27 May 2016 14:28:04 +0100 Subject: MIPS: Move cache sizes to Kconfig Move details of the L1 cache line sizes & total sizes into Kconfig, defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is introduced to allow platforms to select auto-detection of cache sizes, and it defaults to being enabled if none of the cache sizes are set by the configuration (ie. sizes are all the default 0), and code is adjusted to #ifdef on that rather than on the definition of the sizes (which will always be defined even if 0). Signed-off-by: Paul Burton --- board/tplink/wdr4300/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'board/tplink/wdr4300/Kconfig') diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig index 65785bdb9c..ded7f9b179 100644 --- a/board/tplink/wdr4300/Kconfig +++ b/board/tplink/wdr4300/Kconfig @@ -15,4 +15,13 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0xa1000000 +config SYS_DCACHE_SIZE + default 32768 + +config SYS_ICACHE_SIZE + default 65536 + +config SYS_CACHELINE_SIZE + default 32 + endif -- cgit v1.2.1 From 372286217f050bfd57695001d59f618c52822f40 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 27 May 2016 14:28:05 +0100 Subject: MIPS: Split I & D cache line size config Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck --- board/tplink/wdr4300/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'board/tplink/wdr4300/Kconfig') diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig index ded7f9b179..67a0228773 100644 --- a/board/tplink/wdr4300/Kconfig +++ b/board/tplink/wdr4300/Kconfig @@ -18,10 +18,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 32768 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 65536 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 endif -- cgit v1.2.1