From 61f66fd5a81b97478e9d14326c1059baa6626680 Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Fri, 25 Jul 2014 22:23:19 +0300 Subject: keystone2: use EFUSE_BOOTROM information to configure PLLs This patch reads EFUSE_BOOTROM register to see the maximum supported clock for CORE and TETRIS PLLs and configure them accordingly. Acked-by: Murali Karicheri Signed-off-by: Vitaly Andrianov Signed-off-by: Ivan Khoronzhuk --- board/ti/ks2_evm/board_k2e.c | 23 +++++++++++++++++++---- board/ti/ks2_evm/board_k2hk.c | 29 +++++++++++++++++++++++++---- 2 files changed, 44 insertions(+), 8 deletions(-) (limited to 'board/ti/ks2_evm') diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index d2499b7244..5472a43c43 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -25,15 +25,30 @@ unsigned int external_clk[ext_clk_count] = { [usb_clk] = 100000000, }; -static struct pll_init_data pll_config[] = { - CORE_PLL_1200, - PASS_PLL_1000, +static struct pll_init_data core_pll_config[] = { + CORE_PLL_800, + CORE_PLL_850, + CORE_PLL_1000, + CORE_PLL_1250, + CORE_PLL_1350, + CORE_PLL_1400, + CORE_PLL_1500, }; + +static struct pll_init_data pa_pll_config = + PASS_PLL_1000; + #if defined(CONFIG_BOARD_EARLY_INIT_F) int board_early_init_f(void) { - init_plls(ARRAY_SIZE(pll_config), pll_config); + int speed; + + speed = get_max_dev_speed(); + init_pll(&core_pll_config[speed]); + + init_pll(&pa_pll_config); + return 0; } #endif diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index a369d6bd63..6fb3d2123d 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -8,6 +8,7 @@ */ #include +#include #include #include @@ -28,12 +29,23 @@ unsigned int external_clk[ext_clk_count] = { [rp1_clk] = 123456789 }; -static struct pll_init_data pll_config[] = { - CORE_PLL_1228, - PASS_PLL_983, +static struct pll_init_data core_pll_config[] = { + CORE_PLL_799, + CORE_PLL_999, + CORE_PLL_1200, +}; + +static struct pll_init_data tetris_pll_config[] = { + TETRIS_PLL_800, + TETRIS_PLL_1000, TETRIS_PLL_1200, + TETRIS_PLL_1350, + TETRIS_PLL_1400, }; +static struct pll_init_data pa_pll_config = + PASS_PLL_983; + #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET struct eth_priv_t eth_priv_cfg[] = { { @@ -75,7 +87,16 @@ int get_num_eth_ports(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { - init_plls(ARRAY_SIZE(pll_config), pll_config); + int speed; + + speed = get_max_dev_speed(); + init_pll(&core_pll_config[speed]); + + init_pll(&pa_pll_config); + + speed = get_max_arm_speed(); + init_pll(&tetris_pll_config[speed]); + return 0; } #endif -- cgit v1.2.1