From 7445207f0fa495108736a5642b5b98aef3aed757 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 4 Jun 2014 10:26:52 +0900 Subject: nand_spl: remove simpc8313 support Commit 3d5a335c announced that all the nand_spl boards would be removed before v2014.07 release. Also update README.scrapyard. Signed-off-by: Masahiro Yamada --- board/sheldon/simpc8313/Makefile | 8 -- board/sheldon/simpc8313/README.simpc8313 | 80 -------------- board/sheldon/simpc8313/sdram.c | 177 ------------------------------- board/sheldon/simpc8313/simpc8313.c | 150 -------------------------- 4 files changed, 415 deletions(-) delete mode 100644 board/sheldon/simpc8313/Makefile delete mode 100644 board/sheldon/simpc8313/README.simpc8313 delete mode 100644 board/sheldon/simpc8313/sdram.c delete mode 100644 board/sheldon/simpc8313/simpc8313.c (limited to 'board/sheldon/simpc8313') diff --git a/board/sheldon/simpc8313/Makefile b/board/sheldon/simpc8313/Makefile deleted file mode 100644 index a824c41d9c..0000000000 --- a/board/sheldon/simpc8313/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := simpc8313.o sdram.o diff --git a/board/sheldon/simpc8313/README.simpc8313 b/board/sheldon/simpc8313/README.simpc8313 deleted file mode 100644 index b362c6aeea..0000000000 --- a/board/sheldon/simpc8313/README.simpc8313 +++ /dev/null @@ -1,80 +0,0 @@ -Sheldon Instruments SIMPC8313 Board ------------------------------------------ - -1. Board Switches and Jumpers - - S2 is used to set CFG_RESET_SOURCE. - - To boot the image in Large page NAND flash, use these DIP - switch settings for S2: - - +----------+ ON - | * * **** | - | * * | - +----------+ - 12345678 - - To boot the image in Small page NAND flash, use these DIP - switch settings for S2: - - +----------+ ON - | *** **** | - | * | - +----------+ - 12345678 - (where the '*' indicates the position of the tab of the switch.) - -2. Memory Map - The memory map looks like this: - - 0x0000_0000 0x1fff_ffff DDR 512M - 0x8000_0000 0x8fff_ffff PCI MEM 256M - 0x9000_0000 0x9fff_ffff PCI_MMIO 256M - 0xe000_0000 0xe00f_ffff IMMR 1M - 0xe200_0000 0xe20f_ffff PCI IO 16M - 0xe280_0000 0xe280_7fff NAND FLASH (CS0) 32K - or - 0xe280_0000 0xe281_ffff NAND FLASH (CS0) 128K - 0xff00_0000 0xff00_7fff FPGA (CS1) 1M - -3. Compilation - - Assuming you're using BASH (or similar) as your shell: - - export CROSS_COMPILE=your-cross-compiler-prefix- - make distclean - make SIMPC8313_LP_config - (or make SIMPC8313_SP_config, depending on the page size - of your NAND flash) - make - -4. Downloading and Flashing Images - -4.1 Reflash U-boot Image using U-boot - - =>run update_uboot - - You may want to try - =>tftp $loadaddr $uboot - first, to make sure that the TFTP load will succeed before it - goes ahead and wipes out your current firmware. And of course, - if the new u-boot doesn't boot, you can plug the board into - your PCI slot and with the supplied driver and sample app - you can reburn a working u-boot. - -4.2 Downloading and Booting Linux Kernel - - Ensure that all networking-related environment variables are set - properly (including ipaddr, serverip, gatewayip (if needed), - netmask, ethaddr, eth1addr, fdtfile, and bootfile). - - =>tftp $loadaddr uImage - =>nand write $loadaddr kernel $filesize - =>tftp $loadaddr $fdtfile - =>nand write $loadaddr 7e0000 1800 - - =>boot - -5 Notes - - The console baudrate for SIMPC8313 is 115200bps. diff --git a/board/sheldon/simpc8313/sdram.c b/board/sheldon/simpc8313/sdram.c deleted file mode 100644 index 7c12fe851c..0000000000 --- a/board/sheldon/simpc8313/sdram.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 - * Copyright (C) Sheldon Instruments, Inc. 2008 - * - * Author: Ron Madrid - * - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static long fixed_sdram(void); - -#if defined(CONFIG_NAND_SPL) -void si_wait_i2c(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - - while (!(__raw_readb(&im->i2c[0].sr) & 0x02)) - ; - - __raw_writeb(0x00, &im->i2c[0].sr); - - sync(); - - return; -} - -void si_read_i2c(u32 lbyte, int count, u8 *buffer) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 i; - u8 chip = 0x50 << 1; /* boot sequencer I2C */ - u32 ubyte = (lbyte & 0xff00) >> 8; - - lbyte &= 0xff; - - /* - * Set up controller - */ - __raw_writeb(0x3f, &im->i2c[0].fdr); - __raw_writeb(0x00, &im->i2c[0].adr); - __raw_writeb(0x00, &im->i2c[0].sr); - __raw_writeb(0x00, &im->i2c[0].dr); - - while (__raw_readb(&im->i2c[0].sr) & 0x20) - ; - - /* - * Writing address to device - */ - __raw_writeb(0xb0, &im->i2c[0].cr); - sync(); - __raw_writeb(chip, &im->i2c[0].dr); - si_wait_i2c(); - - __raw_writeb(0xb0, &im->i2c[0].cr); - sync(); - __raw_writeb(ubyte, &im->i2c[0].dr); - si_wait_i2c(); - - __raw_writeb(lbyte, &im->i2c[0].dr); - si_wait_i2c(); - - __raw_writeb(0xb4, &im->i2c[0].cr); - sync(); - __raw_writeb(chip + 1, &im->i2c[0].dr); - si_wait_i2c(); - - __raw_writeb(0xa0, &im->i2c[0].cr); - sync(); - - /* - * Dummy read - */ - __raw_readb(&im->i2c[0].dr); - - si_wait_i2c(); - - /* - * Read actual data - */ - for (i = 0; i < count; i++) - { - if (i == (count - 2)) /* Reached next to last byte, No ACK */ - __raw_writeb(0xa8, &im->i2c[0].cr); - if (i == (count - 1)) /* Reached last byte, STOP */ - __raw_writeb(0x88, &im->i2c[0].cr); - - /* Read byte of data */ - buffer[i] = __raw_readb(&im->i2c[0].dr); - - if (i == (count - 1)) - break; - si_wait_i2c(); - } - - return; -} -#endif /* CONFIG_NAND_SPL */ - -phys_size_t initdram(int board_type) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile fsl_lbc_t *lbc = &im->im_lbc; - u32 msize; - - if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - __raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar); - - msize = fixed_sdram(); - - /* Local Bus setup lbcr and mrtpr */ - __raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr); - __raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr); - sync(); - - /* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); -} - -/************************************************************************* - * fixed sdram init -- reads values from boot sequencer I2C - ************************************************************************/ -static long fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msizelog2, msize = 1; -#if defined(CONFIG_NAND_SPL) - u32 i; - const u8 bytecount = 135; - u8 buffer[bytecount]; - u32 addr, data; - - si_read_i2c(0, bytecount, buffer); - - for (i = 18; i < bytecount; i += 7){ - addr = (u32)buffer[i]; - addr <<= 8; - addr |= (u32)buffer[i + 1]; - addr <<= 2; - data = (u32)buffer[i + 2]; - data <<= 8; - data |= (u32)buffer[i + 3]; - data <<= 8; - data |= (u32)buffer[i + 4]; - data <<= 8; - data |= (u32)buffer[i + 5]; - - __raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr)); - } - - sync(); - - /* enable DDR controller */ - __raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg); -#endif /* (CONFIG_NAND_SPL) */ - - msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1); - msize <<= (msizelog2 - 20); - - return msize; -} diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c deleted file mode 100644 index 31406fa66d..0000000000 --- a/board/sheldon/simpc8313/simpc8313.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 - * Copyright (C) Sheldon Instruments, Inc. 2008 - * - * Author: Ron Madrid - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_NAND_SPL -int checkboard(void) -{ - puts("Board: Sheldon Instruments SIMPC8313\n"); - return 0; -} - -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - struct pci_region *reg[] = { pci_regions }; - - /* Enable all 3 PCI_CLK_OUTPUTs. */ - clk->occr |= 0xe0000000; - - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - mpc83xx_pci_init(1, reg); -} - -/* - * Miscellaneous late-boot configurations - */ -int misc_init_r(void) -{ - int rc = 0; - immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - fsl_lbc_t *lbus = &immap->im_lbc; - u32 *mxmr = &lbus->mamr; /* Pointer to mamr */ - - /* UPM Table Configuration Code */ - static uint UPMATable[] = { - /* Read Single-Beat (RSS) */ - 0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - /* Read Burst (RBS) */ - 0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c, - 0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - /* Write Single-Beat (WSS) */ - 0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - /* Write Burst (WBS) */ - 0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00, - 0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c, - 0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - /* Refresh Timer (RTS) */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - /* Exception Condition (EXS) */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 - }; - - upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); - - /* Set LUPWAIT to be active low and enabled */ - out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS); - - return rc; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} -#endif -#else /* CONFIG_NAND_SPL */ -void board_init_f(ulong bootflag) -{ - NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); - puts("NAND boot... "); - init_timebase(); - initdram(0); - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd, - CONFIG_SYS_NAND_U_BOOT_RELOC); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - nand_boot(); -} - -void putc(char c) -{ - if (gd->flags & GD_FLG_SILENT) - return; - - if (c == '\n') - NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); - - NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); -} -#endif -- cgit v1.2.1