From afabb498b749b48ca3ee7e833fe1501e2d6993cb Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 12 Sep 2010 06:21:37 +0200 Subject: ppc4xx: Big header cleanup part 2, mostly PPC405 related This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. As a part from this cleanup, the GPIO definitions for PPC405EP are corrected. The high and low parts of the registers (for example CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in the wrong order. This patch now fixes this issue by switching these xxxH and xxxL values. This brings the GPIO 405EP port in sync with all other PPC4xx ports. Signed-off-by: Stefan Roese --- board/sc3/sc3.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'board/sc3/sc3.c') diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c index 63927f7298..f148ad6983 100644 --- a/board/sc3/sc3.c +++ b/board/sc3/sc3.c @@ -331,16 +331,16 @@ int board_early_init_f (void) } /* Code decompression disabled */ - mtdcr (KIAR, KCONF); - mtdcr (KIDR, 0x2B); + mtdcr (DCP0_CFGADDR, KCONF); + mtdcr (DCP0_CFGDATA, 0x2B); /* CPC0_ER: enable sleep mode of (currently) unused components */ /* CPC0_FR: force unused components into sleep mode */ - mtdcr (CPMER, 0x3F800000); - mtdcr (CPMFR, 0x14000000); + mtdcr (CPC0_ER, 0x3F800000); + mtdcr (CPC0_FR, 0x14000000); /* set PLB priority */ - mtdcr (0x87, 0x08000000); + mtdcr (PLB0_ACR, 0x08000000); /* --------------- DMA stuff ------------------------------------- */ mtdcr (0x126, 0x49200000); -- cgit v1.2.1