From 927753aeb93f100d73b7ed034238633df41891bc Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 24 Jul 2015 09:22:12 +0200 Subject: ARM: bcm283x: Allocate all mailbox buffers cacheline aligned The mailbox buffer is required to be at least 16 bytes aligned, but for cache invalidation and/or flush it needs to be cacheline aligned. Use ALLOC_CACHE_ALIGN_BUFFER for all mailbox buffer allocations. Signed-off-by: Alexander Stein Acked-by: Stephen Warren Tested-by: Stephen Warren --- board/raspberrypi/rpi/rpi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'board/raspberrypi') diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 96fe870645..d21750e2a0 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -182,7 +182,7 @@ u32 rpi_board_rev = 0; int dram_init(void) { - ALLOC_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1, 16); + ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1); int ret; BCM2835_MBOX_INIT_HDR(msg); @@ -212,7 +212,7 @@ static void set_fdtfile(void) static void set_usbethaddr(void) { - ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16); + ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1); int ret; if (!models[rpi_board_rev].has_onboard_eth) @@ -245,7 +245,7 @@ int misc_init_r(void) static int power_on_module(u32 module) { - ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16); + ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1); int ret; BCM2835_MBOX_INIT_HDR(msg_pwr); @@ -269,7 +269,7 @@ static int power_on_module(u32 module) static void get_board_rev(void) { - ALLOC_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1, 16); + ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1); int ret; const char *name; @@ -324,7 +324,7 @@ int board_init(void) int board_mmc_init(bd_t *bis) { - ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16); + ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1); int ret; power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI); -- cgit v1.2.1