From ab0df36fc7db9dda0b786b909f653e279dfeb9cf Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Fri, 29 Aug 2008 21:09:49 +0200 Subject: avr32: refactor the portmux/gpio code - Separate the portmux configuration functionality from the GPIO pin control API. - Separate the controller-specific code from the chip-specific code. - Allow "ganged" port configuration (multiple pins at once). - Add more flexibility to the "canned" peripheral select functions: - Allow using more than 23 address bits, more chip selects, as well as NAND- and CF-specific pins. - Make the MACB SPEED pin optional, and choose between MII/RMII using a parameter instead of an #ifdef. - Make it possible to use other MMC slots than slot 0, and support different MMC/SDCard data bus widths. - Use more reasonable pull-up defaults; floating pins may consume a lot of power. - Get rid of some custom portmux code from the mimc200 board code. The old gpio/portmux API couldn't really handle its requirements, but the new one can. - Add documentation. The end result is slightly smaller code for all boards. Which isn't really the point, but at least it isn't any larger. This has been verified on ATSTK1002 and ATNGW100. I'd appreciate if the board maintainers could help me test this on their boards. In particular, the mimc200 port has lost a lot of code, so I'm hoping Mark can help me out. Signed-off-by: Haavard Skinnemoen Cc: Hans-Christian Egtvedt Cc: Mark Jackson Cc: Alex Raimondi Cc: Julien May Changes since v1: * Enable pullup on NWAIT * Add missing include to portmux-pio.h * Rename CONFIG_PIO2 -> CONFIG_PORTMUX_PIO to match docs --- board/mimc/mimc200/mimc200.c | 88 +++++++++++--------------------------------- 1 file changed, 21 insertions(+), 67 deletions(-) (limited to 'board/mimc') diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c index 4ece11ac87..4da467860e 100644 --- a/board/mimc/mimc200/mimc200.c +++ b/board/mimc/mimc200/mimc200.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #define SM_PM_GCCTRL 0x0060 @@ -53,98 +54,51 @@ int board_early_init_f(void) /* Enable SDRAM in the EBI mux */ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); - gpio_enable_ebi(); - gpio_enable_usart1(); - - /* enable higher address lines for larger flash devices */ - gpio_select_periph_A(GPIO_PIN_PE16, 0); /* ADDR23 */ - gpio_select_periph_A(GPIO_PIN_PE17, 0); /* ADDR24 */ - gpio_select_periph_A(GPIO_PIN_PE18, 0); /* ADDR25 */ - - /* enable data flash chip select */ - gpio_select_periph_A(GPIO_PIN_PE25, 0); /* NCS2 */ + /* Enable 26 address bits and NCS2 */ + portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); /* de-assert "force sys reset" pin */ - gpio_set_value(GPIO_PIN_PD15, 1); /* FORCE RESET */ - gpio_select_pio(GPIO_PIN_PD15, GPIOF_OUTPUT); + portmux_select_gpio(PORTMUX_PORT_D, 1 << 15, + PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); /* init custom i/o */ /* cpu type inputs */ - gpio_select_pio(GPIO_PIN_PE19, 0); - gpio_select_pio(GPIO_PIN_PE20, 0); - gpio_select_pio(GPIO_PIN_PE23, 0); + portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23), + PORTMUX_DIR_INPUT); /* main board type inputs */ - gpio_select_pio(GPIO_PIN_PB19, 0); - gpio_select_pio(GPIO_PIN_PB29, 0); + portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29), + PORTMUX_DIR_INPUT); /* DEBUG input (use weak pullup) */ - gpio_select_pio(GPIO_PIN_PE21, GPIOF_PULLUP); + portmux_select_gpio(PORTMUX_PORT_E, 1 << 21, + PORTMUX_DIR_INPUT | PORTMUX_PULL_UP); /* are we suppressing the console ? */ - if (gpio_get_value(GPIO_PIN_PE21) == 1) + if (gpio_get_value(GPIO_PIN_PE(21)) == 1) gd->flags |= GD_FLG_SILENT; /* reset phys */ - gpio_select_pio(GPIO_PIN_PE24, 0); - gpio_set_value(GPIO_PIN_PC18, 1); /* PHY RESET */ - gpio_select_pio(GPIO_PIN_PC18, GPIOF_OUTPUT); + portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT); + portmux_select_gpio(PORTMUX_PORT_C, 1 << 18, + PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); /* GCLK0 - 10MHz clock */ writel(0x00000004, (void *)SM_BASE + SM_PM_GCCTRL); - gpio_select_periph_A(GPIO_PIN_PA30, 0); + portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30, PORTMUX_FUNC_A, 0); udelay(5000); /* release phys reset */ - gpio_set_value(GPIO_PIN_PC18, 0); /* PHY RESET (Release) */ + gpio_set_value(GPIO_PIN_PC(18), 0); /* PHY RESET (Release) */ #if defined(CONFIG_MACB) /* init macb0 pins */ - gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */ - gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */ - gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */ - gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */ - gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */ - gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */ - gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */ - gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */ - gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */ - gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */ -#if !defined(CONFIG_RMII) - gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */ - gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */ - gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */ - gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */ - gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */ - gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */ - gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */ - gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */ -#endif - - /* init macb1 pins */ - gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */ - gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */ - gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */ - gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */ - gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */ - gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */ - gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */ - gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */ - gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */ - gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */ -#if !defined(CONFIG_RMII) - gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */ - gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */ - gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */ - gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */ - gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */ - gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */ - gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */ - gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */ -#endif + portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); + portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); #endif #if defined(CONFIG_MMC) - gpio_enable_mmci(); + portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); #endif return 0; -- cgit v1.2.1 From 25e6854d42c11046a468576179b5494f850311b2 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Sun, 31 Aug 2008 18:46:35 +0200 Subject: avr32: use board_early_init_r instead of board_init_info Replace the avr32-specific board_init_info hook by the standard board_early_init_r hook and make it optional. board_early_init_r() runs somewhat earlier than board_init_info used to do, but this isn't a problem for any of the in-tree boards. Signed-off-by: Haavard Skinnemoen --- board/mimc/mimc200/mimc200.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'board/mimc') diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c index 4da467860e..c30bcb6d32 100644 --- a/board/mimc/mimc200/mimc200.c +++ b/board/mimc/mimc200/mimc200.c @@ -124,10 +124,11 @@ phys_size_t initdram(int board_type) return actual_size; } -void board_init_info(void) +int board_early_init_r(void) { gd->bd->bi_phy_id[0] = 0x01; gd->bd->bi_phy_id[1] = 0x03; + return 0; } /* SPI chip select control */ -- cgit v1.2.1 From a69a42338dd25408f9fd5390a83bc501749c7e1b Mon Sep 17 00:00:00 2001 From: Mark Jackson Date: Fri, 3 Oct 2008 11:48:57 +0100 Subject: MIMC200 board now uses CONFIG_DISABLE_CONSOLE Changed MIMC200 board setup and config to use CONFIG_DISABLE_CONSOLE. Also fixed default uImage location. Signed-off-by: Mark Jackson Signed-off-by: Haavard Skinnemoen --- board/mimc/mimc200/mimc200.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/mimc') diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c index 8516dcb828..fd497b2520 100644 --- a/board/mimc/mimc200/mimc200.c +++ b/board/mimc/mimc200/mimc200.c @@ -82,7 +82,7 @@ int board_early_init_f(void) /* are we suppressing the console ? */ if (gpio_get_value(GPIO_PIN_PE21) == 1) - gd->flags |= GD_FLG_SILENT; + gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE); /* reset phys */ gpio_select_pio(GPIO_PIN_PE24, 0); -- cgit v1.2.1 From 80534886a72a0088eef9e781a8e0b7d04ea41f36 Mon Sep 17 00:00:00 2001 From: Mark Jackson Date: Mon, 24 Nov 2008 12:10:56 +0000 Subject: MIMC200: tidy GCLK init code Change the MIMC200 startup code to use the built-in (rather than hard-coded) funtions for setting up gclk outputs. We'll also move the code to the new, more-appropriate board_postclk_init() routine. Signed-off-by: Mark Jackson Signed-off-by: Haavard Skinnemoen --- board/mimc/mimc200/mimc200.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'board/mimc') diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c index ec83b9d4a9..62c0943f57 100644 --- a/board/mimc/mimc200/mimc200.c +++ b/board/mimc/mimc200/mimc200.c @@ -30,8 +30,6 @@ #include #include -#define SM_PM_GCCTRL 0x0060 - DECLARE_GLOBAL_DATA_PTR; static const struct sdram_config sdram_config = { @@ -83,10 +81,6 @@ int board_early_init_f(void) portmux_select_gpio(PORTMUX_PORT_C, 1 << 18, PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); - /* GCLK0 - 10MHz clock */ - writel(0x00000004, (void *)SM_BASE + SM_PM_GCCTRL); - portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30, PORTMUX_FUNC_A, 0); - udelay(5000); /* release phys reset */ @@ -132,6 +126,14 @@ int board_early_init_r(void) return 0; } +int board_postclk_init(void) +{ + /* Use GCLK0 as 10MHz output */ + gclk_enable_output(0, PORTMUX_DRIVE_LOW); + gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000); + return 0; +} + /* SPI chip select control */ #ifdef CONFIG_ATMEL_SPI #include -- cgit v1.2.1 From 58a518c3d8a2c7de11d414e8b903495daee7dc7e Mon Sep 17 00:00:00 2001 From: Mark Jackson Date: Fri, 13 Feb 2009 15:48:18 +0000 Subject: Setup extra MIMC200 chip selects Added code to setup the extra Flash and FRAM chip selects as used on the MIMC200 board. V2 moves the init code from the common "cpu.c" file into the board specific setup file. Signed-off-by: Mark Jackson Signed-off-by: Haavard Skinnemoen --- board/mimc/mimc200/mimc200.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'board/mimc') diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c index 62c0943f57..6df741e397 100644 --- a/board/mimc/mimc200/mimc200.c +++ b/board/mimc/mimc200/mimc200.c @@ -30,6 +30,8 @@ #include #include +#include "../../../cpu/at32ap/hsmc3.h" + DECLARE_GLOBAL_DATA_PTR; static const struct sdram_config sdram_config = { @@ -86,6 +88,18 @@ int board_early_init_f(void) /* release phys reset */ gpio_set_value(GPIO_PIN_PC(18), 0); /* PHY RESET (Release) */ + /* setup Data Flash chip select (NCS2) */ + hsmc3_writel(MODE2, 0x20121003); + hsmc3_writel(CYCLE2, 0x000a0009); + hsmc3_writel(PULSE2, 0x0a060806); + hsmc3_writel(SETUP2, 0x00030102); + + /* setup FRAM chip select (NCS3) */ + hsmc3_writel(MODE3, 0x10120001); + hsmc3_writel(CYCLE3, 0x001e001d); + hsmc3_writel(PULSE3, 0x08040704); + hsmc3_writel(SETUP3, 0x02050204); + #if defined(CONFIG_MACB) /* init macb0 pins */ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); -- cgit v1.2.1