From b2e02d28653edac48d6def9791f2fa0ebc491498 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:36 +0800 Subject: x86: Add basic support to queensbay platform and crownbay board Implement minimum required functions for the basic support to queensbay platform and crownbay board. Currently the implementation is to call fsp_init() in the car_init(). We may move that call to cpu_init_f() in the future. Signed-off-by: Bin Meng Acked-by: Simon Glass --- board/intel/crownbay/crownbay.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 board/intel/crownbay/crownbay.c (limited to 'board/intel/crownbay/crownbay.c') diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c new file mode 100644 index 0000000000..8c6df98bf7 --- /dev/null +++ b/board/intel/crownbay/crownbay.c @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, 4) + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + lpc47m_enable_serial(SERIAL_DEV, UART0_BASE); + + return 0; +} -- cgit v1.2.1 From b71eec3129c2626bfb1e98141b317d958e3cf384 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:38 +0800 Subject: x86: ich6-gpio: Add Intel Tunnel Creek GPIO support Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng Acked-by: Simon Glass --- board/intel/crownbay/crownbay.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'board/intel/crownbay/crownbay.c') diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index 8c6df98bf7..54670d3ac7 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -19,3 +19,8 @@ int board_early_init_f(void) return 0; } + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) +{ + return; +} -- cgit v1.2.1 From 0ff65eb99c3ed4d452b9c74dae8c4f736d92303f Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:45 +0800 Subject: x86: crownbay: Enable Intel E1000 NIC support We don't have driver for the Intel Topcliff PCH Gigabit Ethernet controller for now, so enable the Intle E1000 NIC support, which can be plugged into any PCIe slot on the Crown Bay board. Signed-off-by: Bin Meng Acked-by: Simon Glass --- board/intel/crownbay/crownbay.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'board/intel/crownbay/crownbay.c') diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index 54670d3ac7..2a254efe3d 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #define SERIAL_DEV PNP_DEV(0x2e, 4) @@ -24,3 +25,8 @@ void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) { return; } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} -- cgit v1.2.1