From d4ca31c40e8888b36635967522ec7ea03fd7e70b Mon Sep 17 00:00:00 2001
From: wdenk <wdenk>
Date: Fri, 2 Jan 2004 14:00:00 +0000
Subject: * Cleanup lowboot code for MPC5200

* Minor code cleanup (coding style)

* Patch by Reinhard Meyer, 30 Dec 2003:
  - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE,
  - added CONFIG_PHY_ADDR to include/configs/IceCube.h,
  - turned debug print of PHY registers into a function (called in two places)
  - added support for EMK MPC5200 based modules

* Fix MPC8xx PLPRCR_MFD_SHIFT typo

* Add support for TQM866M modules

* Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash)

* Fix a few compiler warnings
---
 board/incaip/memsetup.S | 61 ++++++++++++++++++++++++-------------------------
 1 file changed, 30 insertions(+), 31 deletions(-)

(limited to 'board/incaip')

diff --git a/board/incaip/memsetup.S b/board/incaip/memsetup.S
index 70d2885bca..b438484643 100644
--- a/board/incaip/memsetup.S
+++ b/board/incaip/memsetup.S
@@ -13,7 +13,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -27,35 +27,35 @@
 #include <asm/regdef.h>
 
 
-#define EBU_MODUL_BASE          0xB8000200
-#define EBU_CLC(value)          0x0000(value)
-#define EBU_CON(value)          0x0010(value)
-#define EBU_ADDSEL0(value)      0x0020(value)
-#define EBU_ADDSEL1(value)      0x0024(value)
-#define EBU_ADDSEL2(value)      0x0028(value)
-#define EBU_BUSCON0(value)      0x0060(value)
-#define EBU_BUSCON1(value)      0x0064(value)
-#define EBU_BUSCON2(value)      0x0068(value)
-
-#define MC_MODUL_BASE           0xBF800000
-#define MC_ERRCAUSE(value)      0x0100(value)
-#define MC_ERRADDR(value)       0x0108(value)
-#define MC_IOGP(value)          0x0800(value)
-#define MC_SELFRFSH(value)      0x0A00(value)
-#define MC_CTRLENA(value)       0x1000(value)
-#define MC_MRSCODE(value)       0x1008(value)
-#define MC_CFGDW(value)         0x1010(value)
-#define MC_CFGPB0(value)        0x1018(value)
-#define MC_LATENCY(value)       0x1038(value)
-#define MC_TREFRESH(value)      0x1040(value)
-
-#define CGU_MODUL_BASE          0xBF107000
-#define CGU_PLL1CR(value)       0x0008(value)
-#define CGU_DIVCR(value)        0x0010(value)
-#define CGU_MUXCR(value)        0x0014(value)
-#define CGU_PLL1SR(value)       0x000C(value)
-
-	.set	noreorder		
+#define EBU_MODUL_BASE		0xB8000200
+#define EBU_CLC(value)		0x0000(value)
+#define EBU_CON(value)		0x0010(value)
+#define EBU_ADDSEL0(value)	0x0020(value)
+#define EBU_ADDSEL1(value)	0x0024(value)
+#define EBU_ADDSEL2(value)	0x0028(value)
+#define EBU_BUSCON0(value)	0x0060(value)
+#define EBU_BUSCON1(value)	0x0064(value)
+#define EBU_BUSCON2(value)	0x0068(value)
+
+#define MC_MODUL_BASE		0xBF800000
+#define MC_ERRCAUSE(value)	0x0100(value)
+#define MC_ERRADDR(value)	0x0108(value)
+#define MC_IOGP(value)		0x0800(value)
+#define MC_SELFRFSH(value)	0x0A00(value)
+#define MC_CTRLENA(value)	0x1000(value)
+#define MC_MRSCODE(value)	0x1008(value)
+#define MC_CFGDW(value)		0x1010(value)
+#define MC_CFGPB0(value)	0x1018(value)
+#define MC_LATENCY(value)	0x1038(value)
+#define MC_TREFRESH(value)	0x1040(value)
+
+#define CGU_MODUL_BASE		0xBF107000
+#define CGU_PLL1CR(value)	0x0008(value)
+#define CGU_DIVCR(value)	0x0010(value)
+#define CGU_MUXCR(value)	0x0014(value)
+#define CGU_PLL1SR(value)	0x000C(value)
+
+	.set	noreorder
 
 
 /*
@@ -234,4 +234,3 @@ memsetup:
 	j	ra
 	nop
 	.end	memsetup
-
-- 
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