From 28a966715be78fc35147086e68fc80aeb21235b1 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 18 Oct 2010 13:46:49 -0700 Subject: Adding fixed sdram setting for cornet_ds board 800, 900, 1000, 1200MT/s data rate parameters are added for fixed sdram setting. SPD based parameters and fixed parameters can be toggled by hwconfig. To use fixed parameters, hwconfig=fsl_ddr:sdram=fixed To use SPD parameters, hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1 Signed-off-by: York Sun Signed-off-by: Kumar Gala --- board/freescale/corenet_ds/Makefile | 3 +- board/freescale/corenet_ds/corenet_ds.c | 15 -- board/freescale/corenet_ds/ddr.c | 131 +++++++++++- board/freescale/corenet_ds/p4080ds_ddr.c | 356 +++++++++++++++++++++++++++++++ 4 files changed, 488 insertions(+), 17 deletions(-) create mode 100644 board/freescale/corenet_ds/p4080ds_ddr.c (limited to 'board/freescale') diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile index 8aa725523a..7a56fa2ce3 100644 --- a/board/freescale/corenet_ds/Makefile +++ b/board/freescale/corenet_ds/Makefile @@ -27,7 +27,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS-y += $(BOARD).o -COBJS-$(CONFIG_DDR_SPD) += ddr.o +COBJS-y += ddr.o +COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o COBJS-$(CONFIG_PCI) += pci.o COBJS-y += law.o COBJS-y += tlb.o diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 48d95d6a63..68c63ac027 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include @@ -196,20 +195,6 @@ int misc_init_r(void) return 0; } -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size; - - puts("Initializing....\n"); - - dram_size = fsl_ddr_sdram(); - - setup_ddr_tlbs(dram_size / 0x100000); - - puts(" DDR: "); - return dram_size; -} - #ifdef CONFIG_MP void board_lmb_reserve(struct lmb *lmb) { diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 18adf2f9c5..2ee018868b 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -8,9 +8,103 @@ #include #include - +#include +#include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num); + + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +extern fixed_ddr_parm_t fixed_ddr_parm_0[]; +#if (CONFIG_NUM_DDR_CONTROLLERS == 2) +extern fixed_ddr_parm_t fixed_ddr_parm_1[]; +#endif + +phys_size_t fixed_sdram(void) +{ + int i; + sys_info_t sysinfo; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + unsigned int lawbar1_target_id; + + get_sys_info(&sysinfo); + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, sysinfo.freqDDRBus)); + + for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { + if ((sysinfo.freqDDRBus > fixed_ddr_parm_0[i].min_freq) && + (sysinfo.freqDDRBus <= fixed_ddr_parm_0[i].max_freq)) { + memcpy(&ddr_cfg_regs, + fixed_ddr_parm_0[i].ddr_settings, + sizeof(ddr_cfg_regs)); + break; + } + } + + if (fixed_ddr_parm_0[i].max_freq == 0) + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, sysinfo.freqDDRBus)); + + ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + +#if (CONFIG_NUM_DDR_CONTROLLERS == 2) + memcpy(&ddr_cfg_regs, + fixed_ddr_parm_1[i].ddr_settings, + sizeof(ddr_cfg_regs)); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1); +#endif + + /* + * setup laws for DDR. If not interleaving, presuming half memory on + * DDR1 and the other half on DDR2 + */ + if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) { + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, + LAW_TRGT_IF_DDR_INTRLV) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + } else { +#if (CONFIG_NUM_DDR_CONTROLLERS == 2) + /* We require both controllers have identical DIMMs */ + lawbar1_target_id = LAW_TRGT_IF_DDR_1; + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size / 2, + lawbar1_target_id) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + lawbar1_target_id = LAW_TRGT_IF_DDR_2; + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2, + ddr_size / 2, + lawbar1_target_id) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } +#else + lawbar1_target_id = LAW_TRGT_IF_DDR_1; + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, + lawbar1_target_id) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } +#endif + } + return ddr_size; +} static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) { @@ -190,3 +284,38 @@ void fsl_ddr_board_options(memctl_options_t *popts, /* Enable ZQ calibration */ popts->zq_en = 1; } + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + int use_spd = 0; + + puts("Initializing...."); + +#ifdef CONFIG_DDR_SPD + /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ + if (hwconfig_sub("fsl_ddr", "sdram")) { + if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd")) + use_spd = 1; + else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed")) + use_spd = 0; + else + use_spd = 1; + } else + use_spd = 1; +#endif + + if (use_spd) { + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + } else { + puts("using fixed parameters\n"); + dram_size = fixed_sdram(); + } + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c new file mode 100644 index 0000000000..4ad89ff48a --- /dev/null +++ b/board/freescale/corenet_ds/p4080ds_ddr.c @@ -0,0 +1,356 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#define DATARATE_800MHZ 800000000 +#define DATARATE_900MHZ 900000000 +#define DATARATE_1000MHZ 1000000000 +#define DATARATE_1200MHZ 1200000000 +#define DATARATE_1300MHZ 1300000000 + +#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 +#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 +#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45 +#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912 +#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40 +#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000 +#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100 +#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104 +#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944 +#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF +#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830 +#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000 +#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100 +#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104 +#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844 +#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce +#define CONFIG_SYS_DDR_MODE_1_900 0x00441620 +#define CONFIG_SYS_DDR_MODE_2_900 0x00080000 +#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100 +#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc +#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 +#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 + +#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 +#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202 +#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 +#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_TIMING_4 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5 0x02401400 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 +#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000 +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = { + .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = { + .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = { + .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = { + .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800}, + {DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900}, + {DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000}, + {DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200}, + {0, 0, NULL} +}; + +fixed_ddr_parm_t fixed_ddr_parm_1[] = { + {DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800_2nd}, + {DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900_2nd}, + {DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000_2nd}, + {DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200_2nd}, + {0, 0, NULL} +}; -- cgit v1.2.1