From f64bd7c038468de7b6cfa47e88dd0f5ce6c38504 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 7 May 2013 11:19:55 +0530 Subject: powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL e500v2 processor does not support 8K page size TLB entries. So create new TLB entry only during NAND SPL boot. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Andy Fleming --- board/freescale/p1010rdb/tlb.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'board/freescale/p1010rdb') diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 7a8690a90d..0a8159a6a5 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -43,9 +43,14 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#ifdef CONFIG_SPL_NAND_MINIMAL SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_8K, 1), + 0, 10, BOOKE_PAGESZ_4K, 1), +#endif /* *I*G* - CCSRBAR */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, -- cgit v1.2.1