From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/freescale/mpc8313erdb/mpc8313erdb.c | 42 ++++++++++++++-------------- board/freescale/mpc8313erdb/sdram.c | 46 +++++++++++++++---------------- 2 files changed, 44 insertions(+), 44 deletions(-) (limited to 'board/freescale/mpc8313erdb') diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index ebb703d3ec..9ffd4bff87 100644 --- a/board/freescale/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -36,8 +36,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { -#ifndef CFG_8313ERDB_BROKEN_PMC - volatile immap_t *im = (immap_t *)CFG_IMMR; +#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) gd->flags |= GD_FLG_SILENT; @@ -55,28 +55,28 @@ int checkboard(void) #ifndef CONFIG_NAND_SPL static struct pci_region pci_regions[] = { { - bus_start: CFG_PCI1_MEM_BASE, - phys_start: CFG_PCI1_MEM_PHYS, - size: CFG_PCI1_MEM_SIZE, + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, flags: PCI_REGION_MEM | PCI_REGION_PREFETCH }, { - bus_start: CFG_PCI1_MMIO_BASE, - phys_start: CFG_PCI1_MMIO_PHYS, - size: CFG_PCI1_MMIO_SIZE, + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, flags: PCI_REGION_MEM }, { - bus_start: CFG_PCI1_IO_BASE, - phys_start: CFG_PCI1_IO_PHYS, - size: CFG_PCI1_IO_SIZE, + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, flags: PCI_REGION_IO } }; void pci_init_board(void) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; struct pci_region *reg[] = { pci_regions }; @@ -88,14 +88,14 @@ void pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; -#ifndef CFG_8313ERDB_BROKEN_PMC +#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; #endif @@ -135,13 +135,13 @@ void ft_board_setup(void *blob, bd_t *bd) void board_init_f(ulong bootflag) { board_early_init_f(); - NS16550_init((NS16550_t)(CFG_IMMR + 0x4500), - CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE); + NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), + CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); puts("NAND boot... "); init_timebase(); initdram(0); - relocate_code(CFG_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, - CFG_NAND_U_BOOT_RELOC); + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, + CONFIG_SYS_NAND_U_BOOT_RELOC); } void board_init_r(gd_t *gd, ulong dest_addr) @@ -155,8 +155,8 @@ void putc(char c) return; if (c == '\n') - NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), '\r'); + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); - NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), c); + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); } #endif diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 128cd40575..99e8a43f5d 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CFG_8313ERDB_BROKEN_PMC +#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC static void resume_from_sleep(void) { u32 magic = *(u32 *)0; @@ -58,15 +58,15 @@ static void resume_from_sleep(void) */ static long fixed_sdram(void) { - u32 msize = CFG_DDR_SIZE * 1024 * 1024; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; -#ifndef CFG_RAMBOOT - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; +#ifndef CONFIG_SYS_RAMBOOT + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; /* * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], @@ -75,29 +75,29 @@ static long fixed_sdram(void) udelay(50000); im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; - im->ddr.cs_config[0] = CFG_DDR_CONFIG; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; /* Currently we use only one CS, so disable the other bank. */ im->ddr.cs_config[1] = 0; - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; -#ifndef CFG_8313ERDB_BROKEN_PMC +#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - im->ddr.sdram_cfg = CFG_SDRAM_CFG | SDRAM_CFG_BI; + im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI; else #endif - im->ddr.sdram_cfg = CFG_SDRAM_CFG; + im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE_2; + im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; sync(); /* enable DDR controller */ @@ -109,7 +109,7 @@ static long fixed_sdram(void) phys_size_t initdram(int board_type) { - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; volatile lbus83xx_t *lbc = &im->lbus; u32 msize; @@ -120,11 +120,11 @@ phys_size_t initdram(int board_type) msize = fixed_sdram(); /* Local Bus setup lbcr and mrtpr */ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; sync(); -#ifndef CFG_8313ERDB_BROKEN_PMC +#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) resume_from_sleep(); #endif -- cgit v1.2.1