From e4f69d1bd21a12049744989d2dd6b5199c9b8f23 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Fri, 24 Oct 2008 12:59:12 +0000 Subject: ColdFire: Fix M5329EVB and M5373EVB nand issue Fix compilation issue caused by a few mismatches. Provide proper nand chip select enable/disable in nand_hwcontrol() rather than in board_nand_init() just enable once. Remove redundant local nand driver functions - nand_read_byte(), nand_write_byte() and nand_dev_ready() to use common nand driver. Signed-off-by: TsiChung Liew --- board/freescale/m5329evb/nand.c | 57 +++++++++++++++-------------------------- 1 file changed, 20 insertions(+), 37 deletions(-) (limited to 'board/freescale/m5329evb/nand.c') diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index 82492f69db..cf27dda2ff 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -36,56 +36,42 @@ DECLARE_GLOBAL_DATA_PTR; #include #define SET_CLE 0x10 -#define CLR_CLE ~SET_CLE #define SET_ALE 0x08 -#define CLR_ALE ~SET_ALE -static void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { struct nand_chip *this = mtdinfo->priv; -/* volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; TODO: handle wp */ - u32 nand_baseaddr = (u32) this->IO_ADDR_W; + volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - nand_baseaddr |= SET_CLE; - else - nand_baseaddr &= CLR_CLE; - if ( ctrl & NAND_ALE ) - nand_baseaddr |= SET_ALE; - else - nand_baseaddr &= CLR_ALE; - } - this->IO_ADDR_W = (void __iomem *)(nand_baseaddr); + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} + IO_ADDR_W &= ~(SET_ALE | SET_CLE); + *nCE &= 0xFFFB; -static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte) -{ - struct nand_chip *this = mtdinfo->priv; - *((volatile u8 *)(this->IO_ADDR_W)) = byte; -} + if (ctrl & NAND_NCE) + *nCE |= 0x0004; + if (ctrl & NAND_CLE) + IO_ADDR_W |= SET_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= SET_ALE; -static u8 nand_read_byte(struct mtd_info *mtdinfo) -{ - struct nand_chip *this = mtdinfo->priv; - return (u8) (*((volatile u8 *)this->IO_ADDR_R)); -} + this->IO_ADDR_W = (void *)IO_ADDR_W; + } -static int nand_dev_ready(struct mtd_info *mtdinfo) -{ - return 1; + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); } int board_nand_init(struct nand_chip *nand) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - *((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004; - - /* set up pin configuration */ + /* + * set up pin configuration - enabled 2nd output buffer's signals + * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) + * to use nCE signal + */ gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; gpio->pddr_timer |= 0x08; gpio->ppd_timer |= 0x08; @@ -95,9 +81,6 @@ int board_nand_init(struct nand_chip *nand) nand->chip_delay = 50; nand->ecc.mode = NAND_ECC_SOFT; nand->cmd_ctrl = nand_hwcontrol; - nand->read_byte = nand_read_byte; - nand->write_byte = nand_write_byte; - nand->dev_ready = nand_dev_ready; return 0; } -- cgit v1.2.1