From e04f9d0c2f5dec275eb550317c6bad2d8bbfb209 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 4 May 2016 10:20:22 +0800 Subject: board/freescale: Update ddr clk_adjust This patch updates clk_adjust to actual value for boards with T-series and LS-series SoCs to match the setting of clk_adjust in latest ddr driver. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- board/freescale/ls1021aqds/ddr.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'board/freescale/ls1021aqds') diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h index f819c99dba..b39b561dc1 100644 --- a/board/freescale/ls1021aqds/ddr.h +++ b/board/freescale/ls1021aqds/ddr.h @@ -31,21 +31,21 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ #ifdef CONFIG_SYS_FSL_DDR4 - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 4, 8, 0x090A0B0B, 0x0C0D0E0C,}, - {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, - {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 8, 8, 0x090A0B0B, 0x0C0D0E0C,}, + {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, + {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,}, #elif defined(CONFIG_SYS_FSL_DDR3) - {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, - {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, #else #error DDR type not defined #endif -- cgit v1.2.1